Release v1.0.3
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index cdc70e3..e57e823 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -315,6 +315,11 @@
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
#endif
#if defined(STM32H7)
@@ -643,6 +648,10 @@
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
#endif /* STM32G4 */
#if defined(STM32H7)
@@ -1531,18 +1540,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
diff --git a/Inc/stm32l5xx_hal.h b/Inc/stm32l5xx_hal.h
index 63a0922..a587772 100644
--- a/Inc/stm32l5xx_hal.h
+++ b/Inc/stm32l5xx_hal.h
@@ -38,21 +38,20 @@
*/
/* Exported types ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
+/** @defgroup HAL_Exported_Types HAL Exported Types
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
-#define HAL_TICK_FREQ_10HZ 100U
-#define HAL_TICK_FREQ_100HZ 10U
-#define HAL_TICK_FREQ_1KHZ 1U
-#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
-
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
/**
* @}
*/
@@ -61,6 +60,11 @@
* @}
*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
@@ -252,7 +256,14 @@
* @}
*/
+/**
+ * @}
+ */
+
/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+ * @{
+ */
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
* @{
@@ -473,19 +484,15 @@
* @}
*/
+/**
+ * @}
+ */
+
/* Private macros ------------------------------------------------------------*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
-#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \
- ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \
- ((__FREQ__) == HAL_TICK_FREQ_1KHZ))
-
-/**
- * @}
- */
-
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
* @{
*/
@@ -549,6 +556,10 @@
* @}
*/
+/**
+ * @}
+ */
+
/* Exported variables --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
@@ -556,7 +567,7 @@
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
-extern uint32_t uwTickFreq;
+extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
@@ -591,8 +602,8 @@
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
-uint32_t HAL_GetTickFreq(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
@@ -611,8 +622,6 @@
*/
/* DBGMCU Peripheral Control functions *****************************************/
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
diff --git a/Inc/stm32l5xx_hal_adc.h b/Inc/stm32l5xx_hal_adc.h
index dc2e4e6..efa2372 100644
--- a/Inc/stm32l5xx_hal_adc.h
+++ b/Inc/stm32l5xx_hal_adc.h
@@ -184,7 +184,7 @@
This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
-#endif
+#endif /* ADC_CFGR_DFSDMCFG */
} ADC_InitTypeDef;
/**
@@ -333,7 +333,7 @@
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
+#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
@@ -360,7 +360,7 @@
typedef struct __ADC_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
@@ -475,7 +475,7 @@
* @{
*/
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -688,7 +688,6 @@
* @}
*/
-
/** @defgroup ADC_Event_type ADC Event type
* @{
*/
@@ -1001,7 +1000,7 @@
#else
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @brief Enable ADC interrupt.
@@ -1150,7 +1149,7 @@
* @arg @ref ADC_CHANNEL_VBAT
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
- *
+ *
* (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
* (6) On STM32L5, parameter available on devices with several ADC instances.\n
* (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
@@ -1192,7 +1191,7 @@
* @arg @ref ADC_CHANNEL_VBAT (4)
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
- *
+ *
* (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
* (6) On STM32L5, parameter available on devices with several ADC instances.\n
* (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
@@ -1246,7 +1245,7 @@
* @arg @ref ADC_CHANNEL_VBAT
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
- *
+ *
* (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
* (6) On STM32L5, parameter available on devices with several ADC instances.\n
* (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
@@ -1295,7 +1294,7 @@
* @arg @ref ADC_CHANNEL_VBAT
* @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6)
* @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6)
- *
+ *
* (2) On STM32L5, parameter available only on ADC instance: ADC2.\n
* (6) On STM32L5, parameter available on devices with several ADC instances.\n
* (7) On STM32L5, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)).
@@ -1366,7 +1365,7 @@
*/
#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Helper macro to select the ADC common instance
@@ -1437,10 +1436,10 @@
*/
#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
- __ADC_RESOLUTION_TARGET__) \
- __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \
- (__ADC_RESOLUTION_CURRENT__), \
- (__ADC_RESOLUTION_TARGET__))
+ __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+ (__ADC_RESOLUTION_CURRENT__),\
+ (__ADC_RESOLUTION_TARGET__))
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
@@ -1460,10 +1459,10 @@
*/
#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \
- (__ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+ (__ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
@@ -1475,7 +1474,7 @@
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
- * @note On this STM32 serie, calibration data of internal voltage reference
+ * @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
@@ -1491,9 +1490,9 @@
* @retval Analog reference voltage (unit: mV)
*/
#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1522,7 +1521,7 @@
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
@@ -1542,10 +1541,10 @@
*/
#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1596,13 +1595,13 @@
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \
- (__TEMPSENSOR_TYP_CALX_V__), \
- (__TEMPSENSOR_CALX_TEMP__), \
- (__VREFANALOG_VOLTAGE__), \
- (__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__))
+ __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+ (__TEMPSENSOR_TYP_CALX_V__),\
+ (__TEMPSENSOR_CALX_TEMP__),\
+ (__VREFANALOG_VOLTAGE__),\
+ (__TEMPSENSOR_ADC_DATA__),\
+ (__ADC_RESOLUTION__))
/**
* @}
diff --git a/Inc/stm32l5xx_hal_adc_ex.h b/Inc/stm32l5xx_hal_adc_ex.h
index 1adc733..2dae7e8 100644
--- a/Inc/stm32l5xx_hal_adc_ex.h
+++ b/Inc/stm32l5xx_hal_adc_ex.h
@@ -346,7 +346,7 @@
ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
-#endif
+#endif /* ADC_CFGR_DFSDMCFG */
/**
* @}
*/
@@ -364,7 +364,7 @@
ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
ADC_SMPR1_SMP0)
-#endif
+#endif /* ADC_SMPR1_SMPPLUS */
/**
* @}
*/
@@ -378,7 +378,7 @@
#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG))
#else
#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
-#endif
+#endif /* ADC_CFGR_DFSDMCFG */
/**
* @}
*/
@@ -388,11 +388,11 @@
* @{
*/
#define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
-#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
+#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
/**
* @}
*/
-#endif
+#endif /* ADC_CFGR_DFSDMCFG */
/**
* @}
@@ -415,7 +415,7 @@
* Usage of this macro is not the Standard way of multimode
* configuration and can lead to have HAL ADC handles status
* misaligned. Usage of this macro must be limited to cases
- * mentionned above.
+ * mentioned above.
* @param __HANDLE__ ADC handle.
* @retval None
*/
@@ -458,7 +458,8 @@
* @param __RANKNB__ Rank number.
* @retval None
*/
-#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\
+ & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
/**
* @brief Configure ADC injected context queue
@@ -649,49 +650,49 @@
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \
- (((__CHANNEL__) == ADC_CHANNEL_0) || \
- ((__CHANNEL__) == ADC_CHANNEL_1) || \
- ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_6) || \
- ((__CHANNEL__) == ADC_CHANNEL_7) || \
- ((__CHANNEL__) == ADC_CHANNEL_8) || \
- ((__CHANNEL__) == ADC_CHANNEL_9) || \
- ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || \
- ((__CHANNEL__) == ADC_CHANNEL_12) || \
- ((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_14) || \
- ((__CHANNEL__) == ADC_CHANNEL_15) || \
- ((__CHANNEL__) == ADC_CHANNEL_16) || \
- ((__CHANNEL__) == ADC_CHANNEL_17) || \
- ((__CHANNEL__) == ADC_CHANNEL_18) || \
- ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \
- ((((__HANDLE__)->Instance) == ADC2) && \
- (((__CHANNEL__) == ADC_CHANNEL_1) || \
- ((__CHANNEL__) == ADC_CHANNEL_2) || \
- ((__CHANNEL__) == ADC_CHANNEL_3) || \
- ((__CHANNEL__) == ADC_CHANNEL_4) || \
- ((__CHANNEL__) == ADC_CHANNEL_5) || \
- ((__CHANNEL__) == ADC_CHANNEL_6) || \
- ((__CHANNEL__) == ADC_CHANNEL_7) || \
- ((__CHANNEL__) == ADC_CHANNEL_8) || \
- ((__CHANNEL__) == ADC_CHANNEL_9) || \
- ((__CHANNEL__) == ADC_CHANNEL_10) || \
- ((__CHANNEL__) == ADC_CHANNEL_11) || \
- ((__CHANNEL__) == ADC_CHANNEL_12) || \
- ((__CHANNEL__) == ADC_CHANNEL_13) || \
- ((__CHANNEL__) == ADC_CHANNEL_14) || \
- ((__CHANNEL__) == ADC_CHANNEL_15) || \
- ((__CHANNEL__) == ADC_CHANNEL_16) || \
- ((__CHANNEL__) == ADC_CHANNEL_17) || \
- ((__CHANNEL__) == ADC_CHANNEL_18) || \
- ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \
- ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))))
+ (((__CHANNEL__) == ADC_CHANNEL_0) || \
+ ((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_14) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_18) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \
+ ((((__HANDLE__)->Instance) == ADC2) && \
+ (((__CHANNEL__) == ADC_CHANNEL_1) || \
+ ((__CHANNEL__) == ADC_CHANNEL_2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_3) || \
+ ((__CHANNEL__) == ADC_CHANNEL_4) || \
+ ((__CHANNEL__) == ADC_CHANNEL_5) || \
+ ((__CHANNEL__) == ADC_CHANNEL_6) || \
+ ((__CHANNEL__) == ADC_CHANNEL_7) || \
+ ((__CHANNEL__) == ADC_CHANNEL_8) || \
+ ((__CHANNEL__) == ADC_CHANNEL_9) || \
+ ((__CHANNEL__) == ADC_CHANNEL_10) || \
+ ((__CHANNEL__) == ADC_CHANNEL_11) || \
+ ((__CHANNEL__) == ADC_CHANNEL_12) || \
+ ((__CHANNEL__) == ADC_CHANNEL_13) || \
+ ((__CHANNEL__) == ADC_CHANNEL_14) || \
+ ((__CHANNEL__) == ADC_CHANNEL_15) || \
+ ((__CHANNEL__) == ADC_CHANNEL_16) || \
+ ((__CHANNEL__) == ADC_CHANNEL_17) || \
+ ((__CHANNEL__) == ADC_CHANNEL_18) || \
+ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \
+ ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))))
/**
* @brief Verify the ADC channel setting in differential mode.
@@ -922,7 +923,7 @@
((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )
#else
#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
-#endif
+#endif /* ADC_CFGR_DFSDMCFG */
/**
* @brief Return the DFSDM configuration mode.
@@ -936,7 +937,7 @@
#define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
#else
#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
-#endif
+#endif /* ADC_CFGR_DFSDMCFG */
/**
* @}
@@ -1001,7 +1002,8 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+ ADC_InjectionConfTypeDef *sConfigInjected);
#if defined(ADC_MULTIMODE_SUPPORT)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
#endif /* ADC_MULTIMODE_SUPPORT */
diff --git a/Inc/stm32l5xx_hal_comp.h b/Inc/stm32l5xx_hal_comp.h
index 4659a44..d12456c 100644
--- a/Inc/stm32l5xx_hal_comp.h
+++ b/Inc/stm32l5xx_hal_comp.h
@@ -588,7 +588,7 @@
* @}
*/
-/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
+/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
* @{
*/
#define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
@@ -607,7 +607,7 @@
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) ) \
)
-/* Note: On this STM32 serie, comparator input minus parameters are */
+/* Note: On this STM32 series, comparator input minus parameters are */
/* the same on all COMP instances. */
/* However, comparator instance kept as macro parameter for */
/* compatibility with other STM32 families. */
diff --git a/Inc/stm32l5xx_hal_crc.h b/Inc/stm32l5xx_hal_crc.h
index d5a6982..1c3bf15 100644
--- a/Inc/stm32l5xx_hal_crc.h
+++ b/Inc/stm32l5xx_hal_crc.h
@@ -267,7 +267,6 @@
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
-
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
diff --git a/Inc/stm32l5xx_hal_cryp.h b/Inc/stm32l5xx_hal_cryp.h
index 20648b5..24db3c7 100644
--- a/Inc/stm32l5xx_hal_cryp.h
+++ b/Inc/stm32l5xx_hal_cryp.h
@@ -64,9 +64,10 @@
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
- uint32_t HeaderSize; /*!< The size of header buffer in word */
+ uint32_t HeaderSize; /*!< The size of header buffer */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
- uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+ uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
Vector only once and to skip configuration for consecutive processings.
This parameter can be a value of @ref CRYP_Configuration_Skip */
@@ -265,6 +266,17 @@
* @}
*/
+/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
+ * @{
+ */
+
+#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
+#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
+
+/**
+ * @}
+ */
+
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
@@ -568,10 +580,11 @@
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
- (((((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || ((ALGO) == CRYP_AES_CTR)) && \
+ (((((ALGO) == CRYP_AES_CTR)) && \
((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
(((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
- (((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
+ (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
+ ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
/**
* @}
diff --git a/Inc/stm32l5xx_hal_dfsdm.h b/Inc/stm32l5xx_hal_dfsdm.h
index cead7c6..0b5c43b 100644
--- a/Inc/stm32l5xx_hal_dfsdm.h
+++ b/Inc/stm32l5xx_hal_dfsdm.h
@@ -302,8 +302,8 @@
/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
* @{
*/
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */
-#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for output clock is system clock */
+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_fdcan.h b/Inc/stm32l5xx_hal_fdcan.h
index 58b6858..a7f77b7 100644
--- a/Inc/stm32l5xx_hal_fdcan.h
+++ b/Inc/stm32l5xx_hal_fdcan.h
@@ -316,52 +316,53 @@
typedef struct
{
uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
- This parameter can be a value of @ref FDCAN_protocol_error_code */
+ This parameter can be a value of @ref FDCAN_protocol_error_code */
- uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
- frame with its BRS flag set.
- This parameter can be a value of @ref FDCAN_protocol_error_code */
+ uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase
+ of a CAN FD format frame with its BRS flag set.
+ This parameter can be a value of @ref FDCAN_protocol_error_code */
uint32_t Activity; /*!< Specifies the FDCAN module communication state.
- This parameter can be a value of @ref FDCAN_communication_state */
+ This parameter can be a value of @ref FDCAN_communication_state */
uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
This parameter can be:
- 0 : The FDCAN is in Error_Active state
- - 1 : The FDCAN is in Error_Passive state */
+ - 1 : The FDCAN is in Error_Passive state */
uint32_t Warning; /*!< Specifies the FDCAN module warning status.
This parameter can be:
- - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
- - 1 : at least one of error counters has reached the Error_Warning limit of 96 */
+ - 0 : error counters (RxErrorCnt and TxErrorCnt)
+ are below the Error_Warning limit of 96
+ - 1 : at least one of error counters has reached the Error_Warning limit of 96 */
uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
This parameter can be:
- 0 : The FDCAN is not in Bus_Off state
- - 1 : The FDCAN is in Bus_Off state */
+ - 1 : The FDCAN is in Bus_Off state */
uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
This parameter can be:
- 0 : Last received CAN FD message did not have its ESI flag set
- - 1 : Last received CAN FD message had its ESI flag set */
+ - 1 : Last received CAN FD message had its ESI flag set */
uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
This parameter can be:
- 0 : Last received CAN FD message did not have its BRS flag set
- - 1 : Last received CAN FD message had its BRS flag set */
+ - 1 : Last received CAN FD message had its BRS flag set */
- uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status
- This parameter can be:
+ uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received
+ since last protocol status.This parameter can be:
- 0 : No CAN FD message received
- - 1 : CAN FD message received */
+ - 1 : CAN FD message received */
uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
This parameter can be:
- 0 : No protocol exception event occurred since last read access
- - 1 : Protocol exception event occurred */
+ - 1 : Protocol exception event occurred */
uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
- This parameter can be a number between 0 and 127 */
+ This parameter can be a number between 0 and 127 */
} FDCAN_ProtocolStatusTypeDef;
@@ -371,21 +372,22 @@
typedef struct
{
uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
- This parameter can be a number between 0 and 255 */
+ This parameter can be a number between 0 and 255 */
uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
- This parameter can be a number between 0 and 127 */
+ This parameter can be a number between 0 and 127 */
uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
This parameter can be:
- 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
- - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
+ - 1 : The Receive Error Counter (RxErrorCnt)
+ has reached the error passive level of 128 */
uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
This parameter can be a number between 0 and 255.
This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
- TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
+ TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
} FDCAN_ErrorCountersTypeDef;
@@ -795,21 +797,21 @@
* @{
*/
#define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */
-#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */
-#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */
-#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */
-#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */
-#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */
-#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */
-#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */
-#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */
-#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
-#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
-#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
-#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
-#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
-#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
-#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
+#define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */
+#define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */
+#define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */
+#define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */
+#define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */
+#define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */
+#define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */
+#define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */
+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */
+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */
+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */
+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */
+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */
+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */
+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */
/**
* @}
*/
@@ -1037,9 +1039,9 @@
*/
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
+ (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
@@ -1133,19 +1135,26 @@
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
/* Callbacks Register/UnRegister functions ***********************************/
-HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+ pFDCAN_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxEventFifoCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_RxFifo0CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_RxFifo1CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_ErrorStatusCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
/**
@@ -1157,7 +1166,9 @@
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
-HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd,
+ uint32_t NonMatchingExt, uint32_t RejectRemoteStd,
+ uint32_t RejectRemoteExt);
HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
@@ -1166,12 +1177,14 @@
HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
+ uint32_t TimeoutPeriod);
HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
+ uint32_t TdcFilter);
HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
@@ -1188,12 +1201,15 @@
/* Control functions **********************************************************/
HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
+ uint8_t *pTxData);
uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
-HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
+ FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
@@ -1210,7 +1226,8 @@
*/
/* Interrupts management ******************************************************/
HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
-HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
+ uint32_t BufferIndexes);
HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
/**
diff --git a/Inc/stm32l5xx_hal_flash.h b/Inc/stm32l5xx_hal_flash.h
index 3215d85..b325729 100644
--- a/Inc/stm32l5xx_hal_flash.h
+++ b/Inc/stm32l5xx_hal_flash.h
@@ -82,8 +82,11 @@
@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
@ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
- @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_DUALBANK,
- @ref FLASH_OB_USER_SRAM2_PAR and @ref FLASH_OB_USER_SRAM2_RST */
+ @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_SWAP_BANK,
+ @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_DBANK,
+ @ref FLASH_OB_USER_SRAM2_PAR, @ref FLASH_OB_USER_SRAM2_RST,
+ @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
+ @ref FLASH_OB_USER_PA15_PUPEN and @ref FLASH_OB_USER_TZEN */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC).
This parameter must be a value of @ref FLASH_OB_WMSEC */
@@ -108,13 +111,13 @@
*/
typedef struct
{
- HAL_LockTypeDef Lock; /* FLASH locking object */
- uint32_t ErrorCode; /* FLASH error code */
- uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
- uint32_t Address; /* Internal variable to save address selected for program in IT context */
- uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
- uint32_t Page; /* Internal variable to define the current page which is being erased in IT context */
- uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
+ HAL_LockTypeDef Lock; /*!< FLASH locking object */
+ uint32_t ErrorCode; /*!< FLASH error code */
+ uint32_t ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
+ uint32_t Address; /*!< Internal variable to save address selected for program in IT context */
+ uint32_t Bank; /*!< Internal variable to save current bank selected during erase in IT context */
+ uint32_t Page; /*!< Internal variable to define the current page which is being erased in IT context */
+ uint32_t NbPagesToErase; /*!< Internal variable to save the remaining pages to erase in IT context */
}FLASH_ProcessTypeDef;
/**
@@ -143,9 +146,9 @@
#define FLASH_FLAG_ECCD (FLASH_ECCR_ECCD | FLASH_ECCR_ECCD2) /*!< FLASH ECC detection */
#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
- FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR)
-#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC)
-#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS)
+ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR) /*!< Flash all flags from Status Register */
+#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */
+#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */
#else
#define FLASH_FLAG_EOP FLASH_NSSR_NSEOP /*!< FLASH End of operation flag */
#define FLASH_FLAG_OPERR FLASH_NSSR_NSOPERR /*!< FLASH Operation error flag */
@@ -161,9 +164,9 @@
#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
- FLASH_FLAG_OPTWERR)
-#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC)
-#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
+ FLASH_FLAG_OPTWERR) /*!< Flash all flags from Status Register */
+#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCD | FLASH_FLAG_ECCC) /*!< Flash all flags from ECC Register */
+#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) /*!< Flash all flags */
#endif
/**
* @}
@@ -189,19 +192,19 @@
/** @defgroup FLASH_Error FLASH Error
* @{
*/
-#define HAL_FLASH_ERROR_NONE 0x00000000U
-#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
-#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
-#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
-#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
-#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
-#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
+#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< Flash no error */
+#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR /*!< Flash operation error */
+#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR /*!< Flash programming error */
+#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Flash write protection error */
+#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR /*!< Flash programming alignment error */
+#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR /*!< Flash size error */
+#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Flash programming sequence error */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#else
-#define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR
+#define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR /*!< Flash option modification error */
#endif
-#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
-#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
+#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC /*!< Flash ECC correction error */
+#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD /*!< Flash ECC detection error */
/**
* @}
*/
@@ -274,11 +277,12 @@
/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
-#define OB_RDP_LEVEL_0 ((uint32_t)0xAA)
-#define OB_RDP_LEVEL_0_5 ((uint32_t)0x55)
-#define OB_RDP_LEVEL_1 ((uint32_t)0xBB)
-#define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2
- it's no more possible to go back to level 1 or 0 */
+#define OB_RDP_LEVEL_0 ((uint32_t)0xAA) /*!< RDP level 0 code */
+#define OB_RDP_LEVEL_0_5 ((uint32_t)0x55) /*!< RDP level 0.5 code */
+#define OB_RDP_LEVEL_1 ((uint32_t)0xBB) /*!< RDP level 1 code */
+#define OB_RDP_LEVEL_2 ((uint32_t)0xCC) /*!< RDP level 2 code.
+ Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0. */
/**
* @}
*/
@@ -467,7 +471,7 @@
/** @defgroup FLASH_OB_BOOT_LOCK FLASH Option Bytes Boot Lock
* @{
*/
-#define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot lock disable */
+#define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot lock disable */
#define OB_BOOT_LOCK_ENABLE FLASH_SECBOOTADD0R_BOOT_LOCK /*!< Boot lock enable */
/**
* @}
@@ -604,6 +608,7 @@
/**
* @brief Enable the FLASH power down during Low-power run mode.
+ * @retval None
* @note Writing this bit to 0, automatically the keys are
* lost and a new unlock sequence is necessary to re-write it to 1.
*/
@@ -614,6 +619,7 @@
/**
* @brief Disable the FLASH power down during Low-power run mode.
+ * @retval None
* @note Writing this bit to 1, automatically the keys are
* loss and a new unlock sequence is necessary to re-write it to 0.
*/
@@ -624,13 +630,13 @@
/**
* @brief Enable the FLASH power down during Low-Power sleep mode
- * @retval none
+ * @retval None
*/
#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
/**
* @brief Disable the FLASH power down during Low-Power sleep mode
- * @retval none
+ * @retval None
*/
#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
@@ -643,58 +649,90 @@
* @{
*/
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
- * @brief Enable the specified FLASH interrupt.
+ * @brief Enable secure FLASH interrupts from the secure world.
* @param __INTERRUPT__ FLASH interrupt.
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_OPERR: Error Interrupt
* @arg FLASH_IT_ECCC: ECC Correction Interrupt
- * @retval none
+ * @retval None
*/
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Enable secure FLASH interrupts from the secure world */
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
} while(0)
-/* Enable non-secure FLASH interrupts from the secure world */
-#define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
- if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
- } while(0)
-#else
-/* Enable non-secure FLASH interrupts from the non-secure world */
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
- if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
- } while(0)
-#endif /* __ARM_FEATURE_CMSE */
-
/**
- * @brief Disable the specified FLASH interrupt.
+ * @brief Enable non-secure FLASH interrupts from the secure world.
* @param __INTERRUPT__ FLASH interrupt.
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_OPERR: Error Interrupt
* @arg FLASH_IT_ECCC: ECC Correction Interrupt
- * @retval none
+ * @retval None
*/
+#define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
+ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+ } while(0)
+#else
+/**
+ * @brief Enable non-secure FLASH interrupts from the non-secure world.
+ * @param __INTERRUPT__ FLASH interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_OPERR: Error Interrupt
+ * @arg FLASH_IT_ECCC: ECC Correction Interrupt
+ * @retval None
+ */
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
+ if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+ } while(0)
+#endif /* __ARM_FEATURE_CMSE */
+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/* Disable secure FLASH interrupts from the secure world */
+/**
+ * @brief Disable secure FLASH interrupts from the secure world.
+ * @param __INTERRUPT__ FLASH interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_OPERR: Error Interrupt
+ * @arg FLASH_IT_ECCC: ECC Correction Interrupt
+ * @retval None
+ */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
} while(0)
-/* Disable non-secure FLASH interrupts from the secure world */
+/**
+ * @brief Disable non-secure FLASH interrupts from the secure world.
+ * @param __INTERRUPT__ FLASH interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_OPERR: Error Interrupt
+ * @arg FLASH_IT_ECCC: ECC Correction Interrupt
+ * @retval None
+ */
#define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
} while(0)
#else
-/* Disable non-secure FLASH interrupts from the non-secure world */
+/**
+ * @brief Disable non-secure FLASH interrupts from the non-secure world.
+ * @param __INTERRUPT__ FLASH interrupt.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+ * @arg FLASH_IT_OPERR: Error Interrupt
+ * @arg FLASH_IT_ECCC: ECC Correction Interrupt
+ * @retval None
+ */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
} while(0)
#endif /* __ARM_FEATURE_CMSE */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
- * @brief Check whether the specified FLASH flag is set or not.
+ * @brief Check whether the specified secure FLASH flags from the secure world is set or not.
* @param __FLAG__ specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
@@ -710,26 +748,57 @@
* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/* Get secure FLASH flags from the secure world */
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \
(READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__))))
-/* Get non-secure FLASH flags from the secure world */
+/**
+ * @brief Check whether the specified non-secure FLASH flags from the secure world is set or not.
+ * @param __FLAG__ specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+ * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+ * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+ * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+ * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
#define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)))
#else
-/* Get non-secure FLASH flags from the non-secure world */
+/**
+ * @brief Check whether the specified non-secure FLASH flags from the non-secure world is set or not.
+ * @param __FLAG__ specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+ * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+ * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+ * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+ * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)))
#endif /* __ARM_FEATURE_CMSE */
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/**
- * @brief Clear the FLASH's pending flags.
+ * @brief Clear secure FLASH flags from the secure world.
* @param __FLAG__ specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
@@ -745,18 +814,48 @@
* @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
* @retval None
*/
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/* Clear secure FLASH flags from the secure world */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\
if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR)) != 0U) { WRITE_REG(FLASH->SECSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); } \
} while(0)
-/* Clear non-secure FLASH flags from the secure world */
+/**
+ * @brief Clear non-secure FLASH flags from the secure world.
+ * @param __FLAG__ specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+ * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+ * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure)
+ * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+ * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+ * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
+ * @retval None
+ */
#define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
} while(0)
#else
-/* Clear non-secure FLASH flags from the non-secure world */
+/**
+ * @brief Clear non-secure FLASH flags from the non-secure world.
+ * @param __FLAG__ specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+ * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+ * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
+ * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+ * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+ * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+ * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure)
+ * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+ * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+ * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
+ * @retval None
+ */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->NSSR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
} while(0)
@@ -843,6 +942,10 @@
#define FLASH_PAGE_SIZE 0x00000800U
#define FLASH_PAGE_SIZE_128_BITS 0x00001000U
+#define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE)
+#define FLASH_PAGE_NB_PER_BANK (FLASH_BANK_SIZE / FLASH_PAGE_SIZE)
+#define FLASH_PAGE_NB_128_BITS (FLASH_SIZE / FLASH_PAGE_SIZE_128_BITS)
+
#define FLASH_TIMEOUT_VALUE 1000u /* 1 s */
#define FLASH_NON_SECURE_MASK 0x80000000U
diff --git a/Inc/stm32l5xx_hal_flash_ex.h b/Inc/stm32l5xx_hal_flash_ex.h
index 511df85..5b423f1 100644
--- a/Inc/stm32l5xx_hal_flash_ex.h
+++ b/Inc/stm32l5xx_hal_flash_ex.h
@@ -36,23 +36,30 @@
* @{
*/
-/* Exported types ------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/** @addtogroup FLASH_Exported_Types FLASH Exported Types
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASH Extended Private Constants
+ * @{
+ */
+#define FLASH_BLOCKBASED_NB_REG (4U) /*!< Number of block-based registers available */
+/**
+ * @}
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Block-based security structure definition
*/
-#define FLASH_BLOCKBASED_NB_REG (4U)
-
typedef struct
{
uint32_t Bank; /*!< Configuration of the associated bank of Block-based Secure Area.
This parameter must be a value of @ref FLASH_Banks */
uint32_t BBAttributesType; /*!< Block-Based Attributes type.
- This parameter must be a value of @ref FLASH_BB_Attributes */
+ This parameter must be a value of @ref FLASHEx_BB_Attributes */
uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration of a page.
0 means non-secure, 1 means secure */
} FLASH_BBAttributesTypeDef;
@@ -62,10 +69,11 @@
#endif
/* Exported constants --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Constants
+/** @defgroup FLASHEx_Exported_Constants FLASH Extended Exported Constants
* @{
*/
-/** @defgroup PRIV_MODE_CFG FLASH privilege mode configuration
+
+/** @defgroup FLASHEx_PRIV_MODE_CFG FLASH privilege mode configuration
* @{
*/
#define FLASH_PRIV_GRANTED 0x00000000U /*!< access to Flash registers is granted */
@@ -75,7 +83,7 @@
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/** @defgroup SEC_INVERSION_CFG FLASH security inversion configuration
+/** @defgroup FLASHEx_SEC_INVERSION_CFG FLASH security inversion configuration
* @{
*/
#define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */
@@ -85,7 +93,7 @@
*/
#endif
-/** @defgroup LVE_PIN_CFG FLASH LVE pin configuration
+/** @defgroup FLASHEx_LVE_PIN_CFG FLASH LVE pin configuration
* @{
*/
#define FLASH_LVE_PIN_CTRL 0x00000000U /*!< LVEA/B FLASH pin controlled by power controller */
@@ -94,13 +102,14 @@
* @}
*/
-/** @defgroup FLASH_BB_Attributes FLASH Block-Base Attributes
+/** @defgroup FLASHEx_BB_Attributes FLASH Block-Based Attributes
* @{
*/
#define FLASH_BB_SEC 0x00000001U /*!< Flash Block-Based Security Attributes */
/**
* @}
*/
+
/**
* @}
*/
@@ -129,6 +138,7 @@
* @}
*/
+/* Extended Peripheral Control functions ************************************/
/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
@@ -158,7 +168,7 @@
*/
/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
+/** @defgroup FLASHEx_Private_Macros FLASH Extended Private Macros
* @{
*/
#define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) == FLASH_PRIV_GRANTED) || \
diff --git a/Inc/stm32l5xx_hal_hash.h b/Inc/stm32l5xx_hal_hash.h
index c652e87..5f36ec2 100644
--- a/Inc/stm32l5xx_hal_hash.h
+++ b/Inc/stm32l5xx_hal_hash.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -31,7 +31,7 @@
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
-#if defined (HASH)
+
/** @addtogroup HASH
* @{
*/
@@ -605,7 +605,7 @@
/**
* @}
*/
-#endif /* HASH*/
+
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_hash_ex.h b/Inc/stm32l5xx_hal_hash_ex.h
index 6ed3fc1..a6617a1 100644
--- a/Inc/stm32l5xx_hal_hash_ex.h
+++ b/Inc/stm32l5xx_hal_hash_ex.h
@@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -31,7 +31,7 @@
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
-#if defined (HASH)
+
/** @addtogroup HASHEx
* @{
*/
@@ -149,7 +149,7 @@
/**
* @}
*/
-#endif /* HASH*/
+
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_i2c.h b/Inc/stm32l5xx_hal_i2c.h
index ce7ab05..16e6acd 100644
--- a/Inc/stm32l5xx_hal_i2c.h
+++ b/Inc/stm32l5xx_hal_i2c.h
@@ -495,7 +495,8 @@
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
+ (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
@@ -521,7 +522,8 @@
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
+ (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
@@ -541,7 +543,7 @@
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
- : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+ : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
@@ -583,7 +585,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+ pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
@@ -598,49 +601,70 @@
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
@@ -732,7 +756,8 @@
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
-#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
@@ -743,13 +768,15 @@
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
-#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
+#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
+ (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
+ ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
diff --git a/Inc/stm32l5xx_hal_i2c_ex.h b/Inc/stm32l5xx_hal_i2c_ex.h
index be85807..1068396 100644
--- a/Inc/stm32l5xx_hal_i2c_ex.h
+++ b/Inc/stm32l5xx_hal_i2c_ex.h
@@ -38,7 +38,6 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
@@ -72,24 +71,51 @@
*/
/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
+/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
+ * @{
+ */
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
-/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
- * @brief Extended features functions
+/** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions
* @{
*/
-
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions
+ * @{
+ */
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+/**
+ * @}
+ */
+
+/** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions
+ * @{
+ */
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
@@ -105,7 +131,7 @@
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
- ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+ ((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
@@ -117,9 +143,6 @@
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4))
-
-
-
/**
* @}
*/
@@ -141,14 +164,6 @@
* @}
*/
-/**
- * @}
- */
-
-/**
- * @}
- */
-
#ifdef __cplusplus
}
#endif
diff --git a/Inc/stm32l5xx_hal_icache.h b/Inc/stm32l5xx_hal_icache.h
index d7606b8..fffefd4 100644
--- a/Inc/stm32l5xx_hal_icache.h
+++ b/Inc/stm32l5xx_hal_icache.h
@@ -216,7 +216,12 @@
*/
/* Exported functions -------------------------------------------------------*/
-/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions
+/** @addtogroup ICACHE_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup ICACHE_Exported_Functions_Group1
+ * @brief Initialization and control functions
* @{
*/
/* Peripheral Control functions **********************************************/
@@ -229,11 +234,8 @@
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void);
/******* Invalidate in non-blocking mode (Interrupt) */
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void);
-
-/******* IRQHandler and Callbacks used in non-blocking modes (Interrupt) */
-void HAL_ICACHE_IRQHandler(void);
-void HAL_ICACHE_InvalidateCompleteCallback(void);
-void HAL_ICACHE_ErrorCallback(void);
+/******* Wait for Invalidate complete in blocking mode (Polling) */
+HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void);
/******* Performance instruction cache monitoring functions */
HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType);
@@ -242,6 +244,27 @@
uint32_t HAL_ICACHE_Monitor_GetHitValue(void);
uint32_t HAL_ICACHE_Monitor_GetMissValue(void);
+/**
+ * @}
+ */
+
+/** @addtogroup ICACHE_Exported_Functions_Group2
+ * @brief IRQ and callback functions
+ * @{
+ */
+/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */
+void HAL_ICACHE_IRQHandler(void);
+void HAL_ICACHE_InvalidateCompleteCallback(void);
+void HAL_ICACHE_ErrorCallback(void);
+
+/**
+ * @}
+ */
+
+/** @addtogroup ICACHE_Exported_Functions_Group3
+ * @brief Memory remapped regions functions
+ * @{
+ */
/******* Memory remapped regions functions */
HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, ICACHE_RegionConfigTypeDef *sRegionConfig);
HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region);
@@ -250,6 +273,10 @@
* @}
*/
+/**
+ * @}
+ */
+
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
diff --git a/Inc/stm32l5xx_hal_irda.h b/Inc/stm32l5xx_hal_irda.h
index a2e970a..84194c1 100644
--- a/Inc/stm32l5xx_hal_irda.h
+++ b/Inc/stm32l5xx_hal_irda.h
@@ -78,7 +78,8 @@
/**
* @brief HAL IRDA State definition
- * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
+ * @note HAL IRDA State value is a combination of 2 different substates:
+ * gState and RxState (see @ref IRDA_State_Definition).
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -248,7 +249,8 @@
Value is allowed for RxState only */
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
+ Value is result of combination (Or) between
+ gState and RxState values */
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
@@ -571,9 +573,14 @@
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+ ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))):\
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+ ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))):\
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -587,10 +594,14 @@
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
+ ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
+ ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << \
+ ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -606,8 +617,8 @@
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
@@ -621,9 +632,10 @@
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
- (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
+ & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
+ & ((uint32_t)0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
diff --git a/Inc/stm32l5xx_hal_lptim.h b/Inc/stm32l5xx_hal_lptim.h
index acb3aa5..c1a2b83 100644
--- a/Inc/stm32l5xx_hal_lptim.h
+++ b/Inc/stm32l5xx_hal_lptim.h
@@ -128,7 +128,7 @@
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
Note: When using repetition counter the UpdateMode field must be set to
- LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable bahavior may occur.
+ LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable behavior may occur.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
} LPTIM_InitTypeDef;
diff --git a/Inc/stm32l5xx_hal_mmc.h b/Inc/stm32l5xx_hal_mmc.h
index 8d6482e..0acdd14 100644
--- a/Inc/stm32l5xx_hal_mmc.h
+++ b/Inc/stm32l5xx_hal_mmc.h
@@ -52,7 +52,7 @@
HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
- HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
+ HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfer State */
HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
}HAL_MMC_StateTypeDef;
/**
@@ -339,10 +339,12 @@
/**
* @brief
*/
-#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
-#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
-#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
-#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
+#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */
+#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */
+#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */
+#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */
+#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */
+#define eMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
/**
* @}
@@ -685,6 +687,7 @@
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout);
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_mmc_ex.h b/Inc/stm32l5xx_hal_mmc_ex.h
index 1255478..91d0990 100644
--- a/Inc/stm32l5xx_hal_mmc_ex.h
+++ b/Inc/stm32l5xx_hal_mmc_ex.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L5xx_HAL_MMC_EX_H
@@ -35,7 +35,7 @@
/** @addtogroup MMCEx
* @brief SD HAL extended module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup MMCEx_Exported_Types MMCEx Exported Types
@@ -44,7 +44,7 @@
/** @defgroup MMCEx_Exported_Types_Group1 MMC Internal DMA Buffer structure
* @{
- */
+ */
typedef enum
{
MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */
@@ -53,20 +53,20 @@
}HAL_MMCEx_DMABuffer_MemoryTypeDef;
-/**
+/**
* @}
*/
-
-/**
+
+/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
* @{
*/
-
+
/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
* @{
*/
@@ -83,11 +83,11 @@
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -95,7 +95,7 @@
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
+
/**
* @}
*/
@@ -108,6 +108,6 @@
#endif
-#endif /* STM32L5xx_HAL_MMCEx_H */
+#endif /* STM32L5xx_HAL_MMCEx_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l5xx_hal_nand.h b/Inc/stm32l5xx_hal_nand.h
index b7f6cd8..947f9c6 100644
--- a/Inc/stm32l5xx_hal_nand.h
+++ b/Inc/stm32l5xx_hal_nand.h
@@ -89,10 +89,10 @@
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
- for 8 bits adressing or words for 16 bits addressing */
+ for 8 bits addressing or words for 16 bits addressing */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
- for 8 bits adressing or words for 16 bits addressing */
+ for 8 bits addressing or words for 16 bits addressing */
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
@@ -130,9 +130,9 @@
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp Init callback */
- void (* MspDeInitCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND Msp DeInit callback */
- void (* ItCallback) ( struct __NAND_HandleTypeDef * hnand); /*!< NAND IT callback */
+ void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
+ void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
+ void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
#endif
} NAND_HandleTypeDef;
@@ -145,7 +145,7 @@
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
-}HAL_NAND_CallbackIDTypeDef;
+} HAL_NAND_CallbackIDTypeDef;
/**
* @brief HAL NAND Callback pointer definition
@@ -160,8 +160,8 @@
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
- * @{
- */
+ * @{
+ */
/** @brief Reset NAND handle state
* @param __HANDLE__ specifies the NAND handle.
@@ -191,7 +191,8 @@
*/
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
@@ -214,15 +215,23 @@
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
@@ -230,7 +239,8 @@
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
-HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
#endif
@@ -271,33 +281,33 @@
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
-#define NAND_DEVICE ((uint32_t)0x80000000)
-#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
+#define NAND_DEVICE 0x80000000UL
+#define NAND_WRITE_TIMEOUT 0x01000000UL
-#define CMD_AREA ((uint32_t)(1UL<<16U)) /* A16 = CLE high */
-#define ADDR_AREA ((uint32_t)(1UL<<17U)) /* A17 = ALE high */
+#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
+#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
-#define NAND_CMD_AREA_A ((uint8_t)0x00)
-#define NAND_CMD_AREA_B ((uint8_t)0x01)
-#define NAND_CMD_AREA_C ((uint8_t)0x50)
-#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
+#define NAND_CMD_AREA_A 0x00U
+#define NAND_CMD_AREA_B 0x01U
+#define NAND_CMD_AREA_C 0x50U
+#define NAND_CMD_AREA_TRUE1 0x30U
-#define NAND_CMD_WRITE0 ((uint8_t)0x80)
-#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
-#define NAND_CMD_ERASE0 ((uint8_t)0x60)
-#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
-#define NAND_CMD_READID ((uint8_t)0x90)
-#define NAND_CMD_STATUS ((uint8_t)0x70)
-#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
-#define NAND_CMD_RESET ((uint8_t)0xFF)
+#define NAND_CMD_WRITE0 0x80U
+#define NAND_CMD_WRITE_TRUE1 0x10U
+#define NAND_CMD_ERASE0 0x60U
+#define NAND_CMD_ERASE1 0xD0U
+#define NAND_CMD_READID 0x90U
+#define NAND_CMD_STATUS 0x70U
+#define NAND_CMD_LOCK_STATUS 0x7AU
+#define NAND_CMD_RESET 0xFFU
/* NAND memory status */
-#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
-#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
-#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
-#define NAND_BUSY ((uint32_t)0x00000000)
-#define NAND_ERROR ((uint32_t)0x00000001)
-#define NAND_READY ((uint32_t)0x00000040)
+#define NAND_VALID_ADDRESS 0x00000100UL
+#define NAND_INVALID_ADDRESS 0x00000200UL
+#define NAND_TIMEOUT_ERROR 0x00000400UL
+#define NAND_BUSY 0x00000000UL
+#define NAND_ERROR 0x00000001UL
+#define NAND_READY 0x00000040UL
/**
* @}
*/
@@ -314,7 +324,7 @@
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
- (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
diff --git a/Inc/stm32l5xx_hal_nor.h b/Inc/stm32l5xx_hal_nor.h
index 01388a0..60f4651 100644
--- a/Inc/stm32l5xx_hal_nor.h
+++ b/Inc/stm32l5xx_hal_nor.h
@@ -120,9 +120,11 @@
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+ uint32_t CommandSet; /*!< NOR algorithm command set and control */
+
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */
- void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */
+ void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
+ void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
#endif
} NOR_HandleTypeDef;
@@ -134,7 +136,7 @@
{
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
-}HAL_NOR_CallbackIDTypeDef;
+} HAL_NOR_CallbackIDTypeDef;
/**
* @brief HAL NOR Callback pointer definition
@@ -177,7 +179,8 @@
*/
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
@@ -196,8 +199,10 @@
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
@@ -205,7 +210,8 @@
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/* NOR callback registering/unregistering */
-HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+ pNOR_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
#endif
/**
@@ -284,7 +290,7 @@
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
- ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
diff --git a/Inc/stm32l5xx_hal_ospi.h b/Inc/stm32l5xx_hal_ospi.h
index 48cb22d..3c3fb27 100644
--- a/Inc/stm32l5xx_hal_ospi.h
+++ b/Inc/stm32l5xx_hal_ospi.h
@@ -48,45 +48,45 @@
*/
typedef struct
{
- uint32_t FifoThreshold; /* This is the threshold used by the Peripheral to generate the interrupt
- indicating that data are available in reception or free place
- is available in transmission.
- This parameter can be a value between 1 and 32 */
- uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to
- quad mode on two different devices to increase the throughput.
- This parameter can be a value of @ref OSPI_DualQuad */
- uint32_t MemoryType; /* It indicates the external device type connected to the OSPI.
- This parameter can be a value of @ref OSPI_MemoryType */
- uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI,
- it corresponds to the number of address bits required to access
- the external device.
- This parameter can be a value between 1 and 32 */
- uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select
- must remain high between commands.
- This parameter can be a value between 1 and 8 */
- uint32_t FreeRunningClock; /* It enables or not the free running clock.
- This parameter can be a value of @ref OSPI_FreeRunningClock */
- uint32_t ClockMode; /* It indicates the level of clock when the chip select is released.
- This parameter can be a value of @ref OSPI_ClockMode */
- uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration.
- This parameter can be a value of @ref OSPI_WrapSize */
- uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating
- the external clock based on the AHB clock.
- This parameter can be a value between 1 and 256 */
- uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order
- to take in account external signal delays.
- This parameter can be a value of @ref OSPI_SampleShifting */
- uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data.
- This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */
- uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and
- defines the boundary of bytes to release the chip select.
- This parameter can be a value between 0 and 31 */
- uint32_t DelayBlockBypass; /* It enables the delay block bypass, so the sampling is not affected
- by the delay block.
- This parameter can be a value of @ref OSPI_DelayBlockBypass */
- uint32_t Refresh; /* It enables the refresh rate feature. The chip select is released every
- Refresh+1 clock cycles.
- This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt
+ indicating that data are available in reception or free place
+ is available in transmission.
+ This parameter can be a value between 1 and 32 */
+ uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to
+ quad mode on two different devices to increase the throughput.
+ This parameter can be a value of @ref OSPI_DualQuad */
+ uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI.
+ This parameter can be a value of @ref OSPI_MemoryType */
+ uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI,
+ it corresponds to the number of address bits required to access
+ the external device.
+ This parameter can be a value between 1 and 32 */
+ uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select
+ must remain high between commands.
+ This parameter can be a value between 1 and 8 */
+ uint32_t FreeRunningClock; /*!< It enables or not the free running clock.
+ This parameter can be a value of @ref OSPI_FreeRunningClock */
+ uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released.
+ This parameter can be a value of @ref OSPI_ClockMode */
+ uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration.
+ This parameter can be a value of @ref OSPI_WrapSize */
+ uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating
+ the external clock based on the AHB clock.
+ This parameter can be a value between 1 and 256 */
+ uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order
+ to take in account external signal delays.
+ This parameter can be a value of @ref OSPI_SampleShifting */
+ uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data.
+ This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */
+ uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and
+ defines the boundary of bytes to release the chip select.
+ This parameter can be a value between 0 and 31 */
+ uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected
+ by the delay block.
+ This parameter can be a value of @ref OSPI_DelayBlockBypass */
+ uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every
+ Refresh+1 clock cycles.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
}OSPI_InitTypeDef;
/**
@@ -98,15 +98,15 @@
typedef struct
#endif
{
- OCTOSPI_TypeDef *Instance; /* OSPI registers base address */
- OSPI_InitTypeDef Init; /* OSPI initialization parameters */
- uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */
- __IO uint32_t XferSize; /* Number of data to transfer */
- __IO uint32_t XferCount; /* Counter of data transferred */
- DMA_HandleTypeDef *hdma; /* Handle of the DMA channel used for the transfer */
- __IO uint32_t State; /* Internal state of the OSPI HAL driver */
- __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */
- uint32_t Timeout; /* Timeout used for the OSPI external device access */
+ OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */
+ OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */
+ uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */
+ __IO uint32_t XferSize; /*!< Number of data to transfer */
+ __IO uint32_t XferCount; /*!< Counter of data transferred */
+ DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */
+ __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */
+ __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */
+ uint32_t Timeout; /*!< Timeout used for the OSPI external device access */
#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi);
void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
@@ -129,50 +129,50 @@
*/
typedef struct
{
- uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or
- to the registers for the write operation (these registers are only
- used for memory-mapped mode).
- This parameter can be a value of @ref OSPI_OperationType */
- uint32_t FlashId; /* It indicates which external device is selected for this command (it
- applies only if Dualquad is disabled in the initialization structure).
- This parameter can be a value of @ref OSPI_FlashId */
- uint32_t Instruction; /* It contains the instruction to be sent to the device.
- This parameter can be a value between 0 and 0xFFFFFFFF */
- uint32_t InstructionMode; /* It indicates the mode of the instruction.
- This parameter can be a value of @ref OSPI_InstructionMode */
- uint32_t InstructionSize; /* It indicates the size of the instruction.
- This parameter can be a value of @ref OSPI_InstructionSize */
- uint32_t InstructionDtrMode; /* It enables or not the DTR mode for the instruction phase.
- This parameter can be a value of @ref OSPI_InstructionDtrMode */
- uint32_t Address; /* It contains the address to be sent to the device.
- This parameter can be a value between 0 and 0xFFFFFFFF */
- uint32_t AddressMode; /* It indicates the mode of the address.
- This parameter can be a value of @ref OSPI_AddressMode */
- uint32_t AddressSize; /* It indicates the size of the address.
- This parameter can be a value of @ref OSPI_AddressSize */
- uint32_t AddressDtrMode; /* It enables or not the DTR mode for the address phase.
- This parameter can be a value of @ref OSPI_AddressDtrMode */
- uint32_t AlternateBytes; /* It contains the alternate bytes to be sent to the device.
- This parameter can be a value between 0 and 0xFFFFFFFF */
- uint32_t AlternateBytesMode; /* It indicates the mode of the alternate bytes.
- This parameter can be a value of @ref OSPI_AlternateBytesMode */
- uint32_t AlternateBytesSize; /* It indicates the size of the alternate bytes.
- This parameter can be a value of @ref OSPI_AlternateBytesSize */
- uint32_t AlternateBytesDtrMode; /* It enables or not the DTR mode for the alternate bytes phase.
- This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */
- uint32_t DataMode; /* It indicates the mode of the data.
- This parameter can be a value of @ref OSPI_DataMode */
- uint32_t NbData; /* It indicates the number of data transferred with this command.
- This field is only used for indirect mode.
- This parameter can be a value between 1 and 0xFFFFFFFF */
- uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase.
- This parameter can be a value of @ref OSPI_DataDtrMode */
- uint32_t DummyCycles; /* It indicates the number of dummy cycles inserted before data phase.
- This parameter can be a value between 0 and 31 */
- uint32_t DQSMode; /* It enables or not the data strobe management.
- This parameter can be a value of @ref OSPI_DQSMode */
- uint32_t SIOOMode; /* It enables or not the SIOO mode.
- This parameter can be a value of @ref OSPI_SIOOMode */
+ uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or
+ to the registers for the write operation (these registers are only
+ used for memory-mapped mode).
+ This parameter can be a value of @ref OSPI_OperationType */
+ uint32_t FlashId; /*!< It indicates which external device is selected for this command (it
+ applies only if Dualquad is disabled in the initialization structure).
+ This parameter can be a value of @ref OSPI_FlashID */
+ uint32_t Instruction; /*!< It contains the instruction to be sent to the device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
+ This parameter can be a value of @ref OSPI_InstructionMode */
+ uint32_t InstructionSize; /*!< It indicates the size of the instruction.
+ This parameter can be a value of @ref OSPI_InstructionSize */
+ uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase.
+ This parameter can be a value of @ref OSPI_InstructionDtrMode */
+ uint32_t Address; /*!< It contains the address to be sent to the device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t AddressMode; /*!< It indicates the mode of the address.
+ This parameter can be a value of @ref OSPI_AddressMode */
+ uint32_t AddressSize; /*!< It indicates the size of the address.
+ This parameter can be a value of @ref OSPI_AddressSize */
+ uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase.
+ This parameter can be a value of @ref OSPI_AddressDtrMode */
+ uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
+ This parameter can be a value of @ref OSPI_AlternateBytesMode */
+ uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes.
+ This parameter can be a value of @ref OSPI_AlternateBytesSize */
+ uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase.
+ This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */
+ uint32_t DataMode; /*!< It indicates the mode of the data.
+ This parameter can be a value of @ref OSPI_DataMode */
+ uint32_t NbData; /*!< It indicates the number of data transferred with this command.
+ This field is only used for indirect mode.
+ This parameter can be a value between 1 and 0xFFFFFFFF */
+ uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase.
+ This parameter can be a value of @ref OSPI_DataDtrMode */
+ uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase.
+ This parameter can be a value between 0 and 31 */
+ uint32_t DQSMode; /*!< It enables or not the data strobe management.
+ This parameter can be a value of @ref OSPI_DQSMode */
+ uint32_t SIOOMode; /*!< It enables or not the SIOO mode.
+ This parameter can be a value of @ref OSPI_SIOOMode */
}OSPI_RegularCmdTypeDef;
/**
@@ -180,14 +180,14 @@
*/
typedef struct
{
- uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time.
- This parameter can be a value between 0 and 255 */
- uint32_t AccessTime; /* It indicates the number of cycles for the device acces time.
- This parameter can be a value between 0 and 255 */
- uint32_t WriteZeroLatency; /* It enables or not the latency for the write access.
- This parameter can be a value of @ref OSPI_WriteZeroLatency */
- uint32_t LatencyMode; /* It configures the latency mode.
- This parameter can be a value of @ref OSPI_LatencyMode */
+ uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time.
+ This parameter can be a value between 0 and 255 */
+ uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time.
+ This parameter can be a value between 0 and 255 */
+ uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access.
+ This parameter can be a value of @ref OSPI_WriteZeroLatency */
+ uint32_t LatencyMode; /*!< It configures the latency mode.
+ This parameter can be a value of @ref OSPI_LatencyMode */
}OSPI_HyperbusCfgTypeDef;
/**
@@ -195,18 +195,18 @@
*/
typedef struct
{
- uint32_t AddressSpace; /* It indicates the address space accessed by the command.
- This parameter can be a value of @ref OSPI_AddressSpace */
- uint32_t Address; /* It contains the address to be sent tot he device.
- This parameter can be a value between 0 and 0xFFFFFFFF */
- uint32_t AddressSize; /* It indicates the size of the address.
- This parameter can be a value of @ref OSPI_AddressSize */
- uint32_t NbData; /* It indicates the number of data transferred with this command.
- This field is only used for indirect mode.
- This parameter can be a value between 1 and 0xFFFFFFFF
- In case of autopolling mode, this parameter can be any value between 1 and 4 */
- uint32_t DQSMode; /* It enables or not the data strobe management.
- This parameter can be a value of @ref OSPI_DQSMode */
+ uint32_t AddressSpace; /*!< It indicates the address space accessed by the command.
+ This parameter can be a value of @ref OSPI_AddressSpace */
+ uint32_t Address; /*!< It contains the address to be sent tot he device.
+ This parameter can be a value between 0 and 0xFFFFFFFF */
+ uint32_t AddressSize; /*!< It indicates the size of the address.
+ This parameter can be a value of @ref OSPI_AddressSize */
+ uint32_t NbData; /*!< It indicates the number of data transferred with this command.
+ This field is only used for indirect mode.
+ This parameter can be a value between 1 and 0xFFFFFFFF
+ In case of autopolling mode, this parameter can be any value between 1 and 4 */
+ uint32_t DQSMode; /*!< It enables or not the data strobe management.
+ This parameter can be a value of @ref OSPI_DQSMode */
}OSPI_HyperbusCmdTypeDef;
/**
@@ -214,16 +214,16 @@
*/
typedef struct
{
- uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
- This parameter can be any value between 0 and 0xFFFFFFFF */
- uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
- This parameter can be any value between 0 and 0xFFFFFFFF */
- uint32_t MatchMode; /* Specifies the method used for determining a match.
- This parameter can be a value of @ref OSPI_MatchMode */
- uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
- This parameter can be a value of @ref OSPI_AutomaticStop */
- uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
- This parameter can be any value between 0 and 0xFFFF */
+ uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received.
+ This parameter can be any value between 0 and 0xFFFFFFFF */
+ uint32_t MatchMode; /*!< Specifies the method used for determining a match.
+ This parameter can be a value of @ref OSPI_MatchMode */
+ uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match.
+ This parameter can be a value of @ref OSPI_AutomaticStop */
+ uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases.
+ This parameter can be any value between 0 and 0xFFFF */
}OSPI_AutoPollingTypeDef;
/**
@@ -231,10 +231,10 @@
*/
typedef struct
{
- uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
- This parameter can be a value of @ref OSPI_TimeOutActivation */
- uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
- This parameter can be any value between 0 and 0xFFFF */
+ uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select.
+ This parameter can be a value of @ref OSPI_TimeOutActivation */
+ uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+ This parameter can be any value between 0 and 0xFFFF */
}OSPI_MemoryMappedTypeDef;
diff --git a/Inc/stm32l5xx_hal_pcd.h b/Inc/stm32l5xx_hal_pcd.h
index 92c1f3b..119848f 100644
--- a/Inc/stm32l5xx_hal_pcd.h
+++ b/Inc/stm32l5xx_hal_pcd.h
@@ -99,16 +99,16 @@
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
- PCD_TypeDef *Instance; /*!< Register base address */
- PCD_InitTypeDef Init; /*!< PCD required parameters */
- __IO uint8_t USB_Address; /*!< USB Address */
+ PCD_TypeDef *Instance; /*!< Register base address */
+ PCD_InitTypeDef Init; /*!< PCD required parameters */
+ __IO uint8_t USB_Address; /*!< USB Address */
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
- HAL_LockTypeDef Lock; /*!< PCD peripheral status */
- __IO PCD_StateTypeDef State; /*!< PCD communication state */
- __IO uint32_t ErrorCode; /*!< PCD Error code */
- uint32_t Setup[12]; /*!< Setup packet buffer */
- PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
+ HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+ __IO PCD_StateTypeDef State; /*!< PCD communication state */
+ __IO uint32_t ErrorCode; /*!< PCD Error code */
+ uint32_t Setup[12]; /*!< Setup packet buffer */
+ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
@@ -188,9 +188,9 @@
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
- * @brief macros to handle interrupts and specific clock configurations
- * @{
- */
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
@@ -233,7 +233,7 @@
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
- HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
+ HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
@@ -353,7 +353,7 @@
*/
-#define USB_WAKEUP_EXTI_LINE (0x1U << 2) /*!< USB FS EXTI Line WakeUp Interrupt */
+#define USB_WAKEUP_EXTI_LINE (0x1U << 2) /*!< USB FS EXTI Line WakeUp Interrupt */
/**
@@ -363,10 +363,10 @@
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
-#define PCD_EP0MPS_64 DEP0CTL_MPS_64
-#define PCD_EP0MPS_32 DEP0CTL_MPS_32
-#define PCD_EP0MPS_16 DEP0CTL_MPS_16
-#define PCD_EP0MPS_08 DEP0CTL_MPS_8
+#define PCD_EP0MPS_64 EP_MPS_64
+#define PCD_EP0MPS_32 EP_MPS_32
+#define PCD_EP0MPS_16 EP_MPS_16
+#define PCD_EP0MPS_08 EP_MPS_8
/**
* @}
*/
@@ -401,8 +401,8 @@
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
- * @{
- */
+ * @{
+ */
/******************** Bit definition for USB_COUNTn_RX register *************/
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
@@ -463,7 +463,7 @@
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
/* toggle first bit ? */ \
@@ -487,7 +487,7 @@
* @retval None
*/
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
/* toggle first bit ? */ \
@@ -512,7 +512,7 @@
* @retval None
*/
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
/* toggle first bit ? */ \
@@ -564,10 +564,8 @@
* @param bEpNum Endpoint Number.
* @retval TRUE = endpoint in stall condition.
*/
-#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
- == USB_EP_TX_STALL)
-#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
- == USB_EP_RX_STALL)
+#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
+#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
/**
* @brief set & clear EP_KIND bit.
@@ -576,7 +574,7 @@
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
@@ -584,7 +582,7 @@
} while(0) /* PCD_SET_EP_KIND */
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
\
@@ -616,7 +614,7 @@
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
\
@@ -624,7 +622,7 @@
} while(0) /* PCD_CLEAR_RX_EP_CTR */
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
\
@@ -638,7 +636,7 @@
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) do { \
- register uint16_t _wEPVal; \
+ uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
@@ -646,7 +644,7 @@
} while(0) /* PCD_RX_DTOG */
#define PCD_TX_DTOG(USBx, bEpNum) do { \
- register uint16_t _wEPVal; \
+ uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
@@ -659,7 +657,7 @@
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
@@ -670,7 +668,7 @@
} while(0) /* PCD_CLEAR_RX_DTOG */
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
@@ -688,7 +686,7 @@
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) do { \
- register uint16_t _wRegVal; \
+ uint16_t _wRegVal; \
\
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
\
@@ -714,8 +712,8 @@
* @retval None
*/
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) do { \
- register __IO uint16_t *_wRegVal; \
- register uint32_t _wRegBase = (uint32_t)USBx; \
+ __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
@@ -723,8 +721,8 @@
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) do { \
- register __IO uint16_t *_wRegVal; \
- register uint32_t _wRegBase = (uint32_t)USBx; \
+ __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
@@ -783,8 +781,8 @@
} while(0) /* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) do { \
- register uint32_t _wRegBase = (uint32_t)(USBx); \
- register __IO uint16_t *pdwReg; \
+ uint32_t _wRegBase = (uint32_t)(USBx); \
+ __IO uint16_t *pdwReg; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
@@ -799,8 +797,8 @@
* @retval None
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) do { \
- register uint32_t _wRegBase = (uint32_t)(USBx); \
- register __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)(USBx); \
+ __IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
@@ -808,8 +806,8 @@
} while(0)
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) do { \
- register uint32_t _wRegBase = (uint32_t)(USBx); \
- register __IO uint16_t *_wRegVal; \
+ uint32_t _wRegBase = (uint32_t)(USBx); \
+ __IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
@@ -887,7 +885,7 @@
} while(0) /* SetEPDblBuf0Count*/
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) do { \
- register uint32_t _wBase = (uint32_t)(USBx); \
+ uint32_t _wBase = (uint32_t)(USBx); \
__IO uint16_t *_wEPRegVal; \
\
if ((bDir) == 0U) \
@@ -910,7 +908,7 @@
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) do { \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
- } while(0) /* PCD_SET_EP_DBUF_CNT */
+ } while(0) /* PCD_SET_EP_DBUF_CNT */
/**
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
diff --git a/Inc/stm32l5xx_hal_rcc.h b/Inc/stm32l5xx_hal_rcc.h
index 381dadc..b92ec92 100644
--- a/Inc/stm32l5xx_hal_rcc.h
+++ b/Inc/stm32l5xx_hal_rcc.h
@@ -53,7 +53,7 @@
This parameter must be a value of @ref RCC_PLL_Clock_Source */
uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
- This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
+ This parameter must be a value of @ref RCC_PLLM_Clock_Divider */
uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 8 and Max_Data = 86 */
@@ -65,7 +65,7 @@
This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
uint32_t PLLR; /*!< PLLR: Division for the main system clock.
- User have to set the PLLR parameter correctly to not exceed max frequency 80MHZ.
+ User has to set the PLLR parameter correctly to not exceed max frequency 110MHZ.
This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
} RCC_PLLInitTypeDef;
@@ -113,7 +113,7 @@
} RCC_OscInitTypeDef;
/**
- * @brief RCC System, AHB and APB busses clock configuration structure definition
+ * @brief RCC System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
@@ -123,8 +123,8 @@
uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
This parameter can be a value of @ref RCC_System_Clock_Source */
- uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
- This parameter can be a value of @ref RCC_AHB_Clock_Source */
+ uint32_t AHBCLKDivider; /*!< The AHBx clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+ This parameter can be a value of @ref RCC_AHBx_Clock_Source */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
@@ -247,6 +247,29 @@
* @}
*/
+/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
+ * @{
+ */
+#define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */
+#define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */
+#define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */
+#define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */
+#define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */
+#define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */
+#define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */
+#define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */
+#define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */
+#define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */
+#define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */
+#define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */
+#define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */
+#define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */
+#define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */
+#define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */
+/**
+ * @}
+ */
+
/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
* @{
*/
@@ -312,7 +335,7 @@
#define RCC_PLLSOURCE_NONE 0U /*!< No clock selected as PLL entry clock source */
#define RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as PLL entry clock source */
#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_0|RCC_PLLCFGR_PLLSRC_1) /*!< HSE clock selected as PLL entry clock source */
+#define RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as PLL entry clock source */
/**
* @}
*/
@@ -333,7 +356,7 @@
#define RCC_PLLSAI1SOURCE_NONE 0U /*!< No clock selected as PLLSAI1 entry clock source */
#define RCC_PLLSAI1SOURCE_MSI RCC_PLLSAI1CFGR_PLLSAI1SRC_0 /*!< MSI clock selected as PLLSAI1 entry clock source */
#define RCC_PLLSAI1SOURCE_HSI RCC_PLLSAI1CFGR_PLLSAI1SRC_1 /*!< HSI clock selected as PLLSAI1 entry clock source */
-#define RCC_PLLSAI1SOURCE_HSE (RCC_PLLSAI1CFGR_PLLSAI1SRC_0|RCC_PLLSAI1CFGR_PLLSAI1SRC_1) /*!< HSE clock selected as PLLSAI1 entry clock source */
+#define RCC_PLLSAI1SOURCE_HSE (RCC_PLLSAI1CFGR_PLLSAI1SRC_1 | RCC_PLLSAI1CFGR_PLLSAI1SRC_0) /*!< HSE clock selected as PLLSAI1 entry clock source */
/**
* @}
*/
@@ -354,7 +377,7 @@
#define RCC_PLLSAI2SOURCE_NONE 0U /*!< No clock selected as PLLSAI2 entry clock source */
#define RCC_PLLSAI2SOURCE_MSI RCC_PLLSAI2CFGR_PLLSAI2SRC_0 /*!< MSI clock selected as PLLSAI2 entry clock source */
#define RCC_PLLSAI2SOURCE_HSI RCC_PLLSAI2CFGR_PLLSAI2SRC_1 /*!< HSI clock selected as PLLSAI2 entry clock source */
-#define RCC_PLLSAI2SOURCE_HSE (RCC_PLLSAI2CFGR_PLLSAI2SRC_0|RCC_PLLSAI2CFGR_PLLSAI2SRC_1) /*!< HSE clock selected as PLLSAI2 entry clock source */
+#define RCC_PLLSAI2SOURCE_HSE (RCC_PLLSAI2CFGR_PLLSAI2SRC_1 | RCC_PLLSAI2CFGR_PLLSAI2SRC_0) /*!< HSE clock selected as PLLSAI2 entry clock source */
/**
* @}
*/
@@ -370,18 +393,18 @@
/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
* @{
*/
-#define RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
-#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
-#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
-#define RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
-#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
-#define RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
-#define RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
-#define RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
-#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
-#define RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
-#define RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
-#define RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
+#define RCC_MSIRANGE_0 0UL /*!< MSI = 100 kHz */
+#define RCC_MSIRANGE_1 RCC_CR_MSIRANGE_0 /*!< MSI = 200 kHz */
+#define RCC_MSIRANGE_2 RCC_CR_MSIRANGE_1 /*!< MSI = 400 kHz */
+#define RCC_MSIRANGE_3 (RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 800 kHz */
+#define RCC_MSIRANGE_4 RCC_CR_MSIRANGE_2 /*!< MSI = 1 MHz */
+#define RCC_MSIRANGE_5 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_0) /*!< MSI = 2 MHz */
+#define RCC_MSIRANGE_6 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1) /*!< MSI = 4 MHz */
+#define RCC_MSIRANGE_7 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 8 MHz */
+#define RCC_MSIRANGE_8 RCC_CR_MSIRANGE_3 /*!< MSI = 16 MHz */
+#define RCC_MSIRANGE_9 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_0) /*!< MSI = 24 MHz */
+#define RCC_MSIRANGE_10 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1) /*!< MSI = 32 MHz */
+#define RCC_MSIRANGE_11 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 48 MHz */
/**
* @}
*/
@@ -400,10 +423,10 @@
/** @defgroup RCC_System_Clock_Source System Clock Source
* @{
*/
-#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
-#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
-#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+#define RCC_SYSCLKSOURCE_MSI 0UL /*!< MSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
+#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
+#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW /*!< PLL selection as system clock */
/**
* @}
*/
@@ -411,26 +434,26 @@
/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
* @{
*/
-#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_MSI 0UL /*!< MSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS /*!< PLL used as system clock */
/**
* @}
*/
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+/** @defgroup RCC_AHBx_Clock_Source AHBx Clock Source
* @{
*/
-#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+#define RCC_SYSCLK_DIV1 0UL /*!< SYSCLK not divided */
+#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
+#define RCC_SYSCLK_DIV4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
+#define RCC_SYSCLK_DIV8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
+#define RCC_SYSCLK_DIV16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
+#define RCC_SYSCLK_DIV64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
+#define RCC_SYSCLK_DIV128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
+#define RCC_SYSCLK_DIV256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
+#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 512 */
/**
* @}
*/
@@ -438,11 +461,11 @@
/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
* @{
*/
-#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+#define RCC_HCLK_DIV1 0UL /*!< HCLK not divided */
+#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_2 /*!< HCLK divided by 2 */
+#define RCC_HCLK_DIV4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK divided by 4 */
+#define RCC_HCLK_DIV8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK divided by 8 */
+#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1 /*!< HCLK divided by 16 */
/**
* @}
*/
@@ -486,11 +509,11 @@
/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
* @{
*/
-#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
-#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
-#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
-#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
-#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
+#define RCC_MCODIV_1 0UL /*!< MCO not divided */
+#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
+#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
+#define RCC_MCODIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
+#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
/**
* @}
*/
@@ -532,7 +555,7 @@
/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
-#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
+#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System failure detection flag */
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
@@ -1509,8 +1532,6 @@
#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) != 0U)
-
#if defined(USB)
#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) != 0U)
#endif /* USB */
@@ -1568,8 +1589,6 @@
#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CAN1EN) == 0U)
-
#if defined(USB)
#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBFSEN) == 0U)
#endif /* USB */
@@ -1655,7 +1674,7 @@
* @brief Force or release AHB1 peripheral reset.
* @{
*/
-#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
+#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFUL)
#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
@@ -1670,7 +1689,7 @@
#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST)
-#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
+#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000UL)
#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
@@ -1692,7 +1711,7 @@
* @brief Force or release AHB2 peripheral reset.
* @{
*/
-#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
+#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFUL)
#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
@@ -1729,7 +1748,7 @@
#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_SDMMC1RST)
-#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
+#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000UL)
#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
@@ -1773,14 +1792,14 @@
* @brief Force or release AHB3 peripheral reset.
* @{
*/
-#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFUL)
#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_OSPI1RST)
-#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
+#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000UL)
#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
@@ -1794,7 +1813,10 @@
* @brief Force or release APB1 peripheral reset.
* @{
*/
-#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
+#define __HAL_RCC_APB1_FORCE_RESET() do { \
+ WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFUL); \
+ WRITE_REG(RCC->APB1RSTR2, 0xFFFFFFFFUL); \
+ } while(0)
#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
@@ -1853,7 +1875,10 @@
#define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
-#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
+#define __HAL_RCC_APB1_RELEASE_RESET() do { \
+ WRITE_REG(RCC->APB1RSTR1, 0x00000000UL); \
+ WRITE_REG(RCC->APB1RSTR2, 0x00000000UL); \
+ } while(0)
#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
@@ -1919,7 +1944,7 @@
* @brief Force or release APB2 peripheral reset.
* @{
*/
-#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
+#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFUL)
#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
@@ -1944,7 +1969,7 @@
#define __HAL_RCC_DFSDM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DFSDM1RST)
-#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
+#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000UL)
#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
@@ -2177,8 +2202,6 @@
#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
-
#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
@@ -2240,8 +2263,6 @@
#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN)
-
#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_DAC1SMEN)
@@ -2515,8 +2536,6 @@
#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) != 0U)
-
#if defined(USB)
#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) != 0U)
#endif /* USB */
@@ -2574,8 +2593,6 @@
#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
-#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CAN1SMEN) == 0U)
-
#if defined(USB)
#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBFSSMEN) == 0U)
#endif /* USB */
@@ -2795,10 +2812,10 @@
* @note The MSI clock range after reset can be modified on the fly.
* @param __MSIRANGEVALUE__ specifies the MSI clock range.
* This parameter must be one of the following values:
- * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
- * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
- * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
- * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
+ * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 kHz
+ * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 kHz
+ * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 kHz
+ * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 kHz
* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
@@ -2832,10 +2849,10 @@
/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
* @retval MSI clock range.
* This parameter must be one of the following values:
- * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 KHz
- * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 KHz
- * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 KHz
- * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 KHz
+ * @arg @ref RCC_MSIRANGE_0 MSI clock is around 100 kHz
+ * @arg @ref RCC_MSIRANGE_1 MSI clock is around 200 kHz
+ * @arg @ref RCC_MSIRANGE_2 MSI clock is around 400 kHz
+ * @arg @ref RCC_MSIRANGE_3 MSI clock is around 800 kHz
* @arg @ref RCC_MSIRANGE_4 MSI clock is around 1 MHz
* @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz
* @arg @ref RCC_MSIRANGE_6 MSI clock is around 4 MHz (default after Reset)
@@ -3042,7 +3059,7 @@
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
*
* @param __PLLM__ specifies the division factor for PLL VCO input clock.
- * This parameter must be a number between Min_Data = 1 and Max_Data = 16.
+ * This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 4 to 16 MHz. It is recommended to select a frequency
* of 16 MHz to limit PLL jitter.
@@ -3054,12 +3071,14 @@
*
* @param __PLLP__ specifies the division factor for SAI clock.
* This parameter must be a number in the range (2 to 31).
+ *
* @param __PLLQ__ specifies the division factor for USB FS, SDMMC1, RNG and FDCAN clocks.
* This parameter must be in the range (2, 4, 6 or 8).
* @note If the USB FS is used in your application, you have to set the
* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
* the SDMMC1, RNG and FDCAN need a frequency lower than or equal to 48 MHz
* to work correctly.
+ *
* @param __PLLR__ specifies the division factor for the main system clock.
* @note You have to set the PLLR parameter correctly to not exceed 80MHZ.
* This parameter must be in the range (2, 4, 6 or 8).
@@ -3079,10 +3098,10 @@
/** @brief Macro to get the oscillator used as PLL clock source.
* @retval The oscillator used as PLL clock source. The returned value can be one
* of the following:
- * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
- * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+ * @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source.
+ * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source.
+ * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source.
+ * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source.
*/
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
@@ -3121,10 +3140,10 @@
* @brief Macro to configure the system clock source.
* @param __SYSCLKSOURCE__ specifies the system clock source.
* This parameter can be one of the following values:
- * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
- * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
+ * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
* @retval None
*/
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
@@ -3133,10 +3152,10 @@
/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
* of the following:
- * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
- * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock.
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock.
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock.
+ * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock.
*/
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
@@ -3259,16 +3278,16 @@
* @arg @ref RCC_IT_PLLSAI2RDY PLLSAI2 ready interrupt
* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
- * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+ * @retval The pending state of __INTERRUPT__ (TRUE or FALSE).
*/
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_RCC_GET_IT(__INTERRUPT__) (READ_BIT(RCC->CIFR, (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Set RMVF bit to clear the reset flags.
* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
* @retval None
*/
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
/** @brief Check whether the selected RCC flag is set or not.
* @param __FLAG__ specifies the flag to check.
@@ -3292,11 +3311,11 @@
* @arg @ref RCC_FLAG_LPWRRST Low Power reset
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
- ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
- ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
- ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
- ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == CR_REG_INDEX) ? RCC->CR : \
+ ((((__FLAG__) >> 5U) == CRRCR_REG_INDEX) ? RCC->CRRCR : \
+ ((((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
+ ((((__FLAG__) >> 5U) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR)))) & \
+ (1UL << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
? 1U : 0U)
/**
diff --git a/Inc/stm32l5xx_hal_rcc_ex.h b/Inc/stm32l5xx_hal_rcc_ex.h
index aa329e0..7984b13 100644
--- a/Inc/stm32l5xx_hal_rcc_ex.h
+++ b/Inc/stm32l5xx_hal_rcc_ex.h
@@ -1842,14 +1842,14 @@
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
/**
- * @brief Enable the automatic hardware adjustement of TRIM bits.
+ * @brief Enable the automatic hardware adjustment of TRIM bits.
* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
* @retval None
*/
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
/**
- * @brief Enable or disable the automatic hardware adjustement of TRIM bits.
+ * @brief Enable or disable the automatic hardware adjustment of TRIM bits.
* @retval None
*/
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
diff --git a/Inc/stm32l5xx_hal_rng.h b/Inc/stm32l5xx_hal_rng.h
index 1549f39..8de7190 100644
--- a/Inc/stm32l5xx_hal_rng.h
+++ b/Inc/stm32l5xx_hal_rng.h
@@ -22,7 +22,7 @@
#define STM32L5xx_HAL_RNG_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -81,7 +81,7 @@
typedef struct __RNG_HandleTypeDef
#else
typedef struct
-#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
{
RNG_TypeDef *Instance; /*!< Register base address */
@@ -91,7 +91,7 @@
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
- __IO uint32_t ErrorCode; /*!< RNG Error code */
+ __IO uint32_t ErrorCode; /*!< RNG Error code */
uint32_t RandomNumber; /*!< Last Generated RNG Data */
@@ -171,14 +171,14 @@
/** @defgroup RNG_Error_Definition RNG Error Definition
* @{
*/
-#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
+#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
-#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
+#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
/**
* @}
*/
@@ -204,7 +204,7 @@
} while(0U)
#else
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @brief Enables the RNG peripheral.
@@ -284,7 +284,7 @@
* @}
*/
-/* Include HASH HAL Extended module */
+/* Include RNG HAL Extended module */
#include "stm32l5xx_hal_rng_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup RNG_Exported_Functions RNG Exported Functions
@@ -301,7 +301,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
+ pRNG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
@@ -348,8 +349,8 @@
((IT) == RNG_IT_SEI))
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
- ((FLAG) == RNG_FLAG_CECS) || \
- ((FLAG) == RNG_FLAG_SECS))
+ ((FLAG) == RNG_FLAG_CECS) || \
+ ((FLAG) == RNG_FLAG_SECS))
/**
* @brief Verify the RNG Clock Error Detection mode.
diff --git a/Inc/stm32l5xx_hal_rng_ex.h b/Inc/stm32l5xx_hal_rng_ex.h
index 56c2aab..a766409 100644
--- a/Inc/stm32l5xx_hal_rng_ex.h
+++ b/Inc/stm32l5xx_hal_rng_ex.h
@@ -22,7 +22,7 @@
#define STM32L5xx_HAL_RNG_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -32,7 +32,8 @@
* @{
*/
-#if defined (RNG)
+#if defined(RNG)
+#if defined(RNG_CR_CONDRST)
/** @defgroup RNGEx RNGEx
* @brief RNG Extension HAL module driver
@@ -70,40 +71,40 @@
*/
/** @defgroup RNGEX_Clock_Divider_Factor Value used to configure an internal
- * programmable divider acting on the incoming RNG clock
+ * programmable divider acting on the incoming RNG clock
* @{
*/
#define RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
#define RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
- /*!< 2 RNG clock cycles per internal RNG clock */
+/*!< 2 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
- /*!< 4 RNG clock cycles per internal RNG clock */
+/*!< 4 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
- /*!< 8 RNG clock cycles per internal RNG clock */
+/*!< 8 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
- /*!< 16 RNG clock cycles per internal RNG clock */
+/*!< 16 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
- /*!< 32 RNG clock cycles per internal RNG clock */
+/*!< 32 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
- /*!< 64 RNG clock cycles per internal RNG clock */
+/*!< 64 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
- /*!< 128 RNG clock cycles per internal RNG clock */
+/*!< 128 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
- /*!< 256 RNG clock cycles per internal RNG clock */
+/*!< 256 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
- /*!< 512 RNG clock cycles per internal RNG clock */
+/*!< 512 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
- /*!< 1024 RNG clock cycles per internal RNG clock */
+/*!< 1024 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
- /*!< 2048 RNG clock cycles per internal RNG clock */
+/*!< 2048 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
- /*!< 4096 RNG clock cycles per internal RNG clock */
+/*!< 4096 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
- /*!< 8192 RNG clock cycles per internal RNG clock */
+/*!< 8192 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
- /*!< 16384 RNG clock cycles per internal RNG clock */
+/*!< 16384 RNG clock cycles per internal RNG clock */
#define RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
- /*!< 32768 RNG clock cycles per internal RNG clock */
+/*!< 32768 RNG clock cycles per internal RNG clock */
/**
* @}
*/
@@ -183,8 +184,8 @@
/**
- * @}
- */
+ * @}
+ */
/* Private functions ---------------------------------------------------------*/
/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
@@ -211,6 +212,11 @@
* @}
*/
+/** @addtogroup RNGEx_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
+
/**
* @}
*/
@@ -223,6 +229,11 @@
* @}
*/
+/**
+ * @}
+ */
+
+#endif /* RNG_CR_CONDRST */
#endif /* RNG */
/**
diff --git a/Inc/stm32l5xx_hal_sd.h b/Inc/stm32l5xx_hal_sd.h
index 95bac6c..ae45839 100644
--- a/Inc/stm32l5xx_hal_sd.h
+++ b/Inc/stm32l5xx_hal_sd.h
@@ -56,7 +56,7 @@
HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receiving State */
- HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
+ HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfer State */
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
}HAL_SD_StateTypeDef;
/**
diff --git a/Inc/stm32l5xx_hal_sd_ex.h b/Inc/stm32l5xx_hal_sd_ex.h
index 8471840..c45ff20 100644
--- a/Inc/stm32l5xx_hal_sd_ex.h
+++ b/Inc/stm32l5xx_hal_sd_ex.h
@@ -15,7 +15,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32L5xx_HAL_SD_EX_H
@@ -35,7 +35,7 @@
/** @addtogroup SDEx
* @brief SD HAL extended module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup SDEx_Exported_Types SDEx Exported Types
@@ -44,7 +44,7 @@
/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
* @{
- */
+ */
typedef enum
{
SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */
@@ -52,24 +52,24 @@
}HAL_SDEx_DMABuffer_MemoryTypeDef;
-
-/**
+/**
* @}
*/
-
-/**
+
+/**
* @}
- */
+ */
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
* @{
*/
-
+
/** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions
* @{
*/
+
HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
@@ -83,11 +83,11 @@
/**
* @}
*/
-
+
/**
* @}
*/
-
+
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
@@ -95,7 +95,7 @@
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-
+
/**
* @}
*/
@@ -108,6 +108,6 @@
#endif
-#endif /* stm32l5xx_HAL_SD_EX_H */
+#endif /* stm32l5xx_HAL_SD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l5xx_hal_smartcard.h b/Inc/stm32l5xx_hal_smartcard.h
index 9fe5df2..7fb3afb 100644
--- a/Inc/stm32l5xx_hal_smartcard.h
+++ b/Inc/stm32l5xx_hal_smartcard.h
@@ -52,7 +52,8 @@
where usart_ker_ckpres is the USART input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
+ This parameter @ref SMARTCARD_Word_Length can only be
+ set to 9 (8 data + 1 parity bits). */
uint32_t StopBits; /*!< Specifies the number of stop bits.
This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
@@ -76,13 +77,14 @@
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
- uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
- Selecting the single sample method increases the receiver tolerance to clock
- deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
+ uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote
+ is selected. Selecting the single sample method increases
+ the receiver tolerance to clock deviations. This parameter can be a value
+ of @ref SMARTCARD_OneBit_Sampling. */
uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
- This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
- by 2 to give the division factor of the source clock frequency */
+ This parameter can be any value from 0x01 to 0x1F. Prescaler value is
+ multiplied by 2 to give the division factor of the source clock frequency */
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
@@ -111,7 +113,7 @@
} SMARTCARD_InitTypeDef;
/**
- * @brief SMARTCARD advanced features initalization structure definition
+ * @brief SMARTCARD advanced features initialization structure definition
*/
typedef struct
{
@@ -141,14 +143,16 @@
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref SMARTCARD_MSB_First */
- uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
- relevant flag is available) or once guard time period has elapsed.
- This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
+ uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
+ relevant flag is available) or once guard time period has elapsed.
+ This parameter can be a value
+ of @ref SMARTCARDEx_Transmission_Completion_Indication. */
} SMARTCARD_AdvFeatureInitTypeDef;
/**
* @brief HAL SMARTCARD State definition
- * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
+ * @note HAL SMARTCARD State value is a combination of 2 different substates:
+ * gState and RxState (see @ref SMARTCARD_State_Definition).
* - gState contains SMARTCARD state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
@@ -215,7 +219,8 @@
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used.
- This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */
+ This parameter can be a value of
+ @ref SMARTCARDEx_FIFO_mode. */
void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
@@ -227,12 +232,14 @@
HAL_LockTypeDef Lock; /*!< Locking object */
- __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management
- and also related to Tx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+ __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global
+ Handle management and also related to Tx operations.
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
- This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+ This parameter can be a value
+ of @ref HAL_SMARTCARD_StateTypeDef */
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
@@ -312,23 +319,26 @@
/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
* @{
*/
-#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
- Value is allowed for gState and RxState */
-#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
- Value is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value
+ is allowed for gState and RxState */
+#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for
+ use. Value is allowed for gState
+ and RxState */
#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
- Value is allowed for gState only */
+ Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
- Value is allowed for gState only */
+ Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
-#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
- Not to be used for neither gState nor RxState.
- Value is result of combination (Or) between gState and RxState values */
+#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception
+ process is ongoing Not to be used for
+ neither gState nor RxState.
+ Value is result of combination (Or)
+ between gState and RxState values */
#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
- Value is allowed for gState only */
+ Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
- Value is allowed for gState only */
+ Value is allowed for gState only */
/**
* @}
*/
@@ -664,7 +674,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before
+ * guard time interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -677,9 +688,16 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval None
*/
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -689,7 +707,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard
+ * time interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -702,9 +721,16 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval None
*/
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U <<\
+ ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -714,7 +740,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -728,7 +755,9 @@
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
+ & ((uint32_t)0x01U << (((__INTERRUPT__)\
+ & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U)\
+ ? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -738,7 +767,8 @@
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
- * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)
+ * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
+ * interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
@@ -751,9 +781,15 @@
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
- (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x01U)?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
+ SMARTCARD_CR_POS) == 0x02U)?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) &\
+ ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__))\
+ & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
@@ -1101,7 +1137,8 @@
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
- HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
diff --git a/Inc/stm32l5xx_hal_smbus.h b/Inc/stm32l5xx_hal_smbus.h
index 3aa8598..3b4248a 100644
--- a/Inc/stm32l5xx_hal_smbus.h
+++ b/Inc/stm32l5xx_hal_smbus.h
@@ -65,7 +65,7 @@
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
- uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
+ uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
@@ -358,7 +358,8 @@
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define SMBUS_IT_RXI I2C_CR1_RXIE
#define SMBUS_IT_TXI I2C_CR1_TXIE
-#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
+#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | \
+ SMBUS_IT_TXI)
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
@@ -408,10 +409,10 @@
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
- (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
- (__HANDLE__)->MspInitCallback = NULL; \
- (__HANDLE__)->MspDeInitCallback = NULL; \
- } while(0)
+ (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
+ (__HANDLE__)->MspInitCallback = NULL; \
+ (__HANDLE__)->MspDeInitCallback = NULL; \
+ } while(0)
#else
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
#endif
@@ -462,7 +463,8 @@
*
* @retval The new state of __IT__ (SET or RESET).
*/
-#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
+ ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SMBUS flag is set or not.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -488,7 +490,8 @@
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
-#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
+ (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the SMBUS Handle.
@@ -539,15 +542,15 @@
*/
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
- ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+ ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
- ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
+ ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
+ ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
((MASK) == SMBUS_OA2_MASK01) || \
@@ -565,47 +568,49 @@
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
- ((PEC) == SMBUS_PEC_ENABLE))
+ ((PEC) == SMBUS_PEC_ENABLE))
-#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
- ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
+#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
+ ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
-#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
- ((MODE) == SMBUS_AUTOEND_MODE) || \
- ((MODE) == SMBUS_SOFTEND_MODE) || \
- ((MODE) == SMBUS_SENDPEC_MODE) || \
- ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
- ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
+#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
+ ((MODE) == SMBUS_AUTOEND_MODE) || \
+ ((MODE) == SMBUS_SOFTEND_MODE) || \
+ ((MODE) == SMBUS_SENDPEC_MODE) || \
+ ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
+ ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
- ((REQUEST) == SMBUS_GENERATE_START_READ) || \
- ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
- ((REQUEST) == SMBUS_NO_STARTSTOP))
+ ((REQUEST) == SMBUS_GENERATE_START_READ) || \
+ ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
+ ((REQUEST) == SMBUS_NO_STARTSTOP))
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
- ((REQUEST) == SMBUS_FIRST_FRAME) || \
- ((REQUEST) == SMBUS_NEXT_FRAME) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
- ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
- ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME) || \
+ ((REQUEST) == SMBUS_NEXT_FRAME) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
+ ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
-#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
-#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
+ (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
+#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
+ (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
- (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
@@ -613,7 +618,8 @@
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
-#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
+ ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
@@ -629,8 +635,8 @@
*/
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
+ * @{
+ */
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
@@ -642,7 +648,8 @@
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+ pSMBUS_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);
@@ -653,28 +660,33 @@
*/
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @{
- */
+ * @{
+ */
/* IO operation functions *****************************************************/
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
- * @{
- */
+ * @{
+ */
/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout);
/**
* @}
*/
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
- * @{
- */
+ * @{
+ */
/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
@@ -685,8 +697,8 @@
*/
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
@@ -703,8 +715,8 @@
*/
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @{
- */
+ * @{
+ */
/* Peripheral State and Errors functions **************************************************/
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
diff --git a/Inc/stm32l5xx_hal_spi.h b/Inc/stm32l5xx_hal_spi.h
index fe22f78..bf569c4 100644
--- a/Inc/stm32l5xx_hal_spi.h
+++ b/Inc/stm32l5xx_hal_spi.h
@@ -582,7 +582,7 @@
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
/** @brief Check whether the specified SPI flag is set or not.
- * @param __SR__ copy of SPI SR regsiter.
+ * @param __SR__ copy of SPI SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
@@ -596,10 +596,11 @@
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
* @retval SET or RESET.
*/
-#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
+#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
+ ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
- * @param __CR2__ copy of SPI CR2 regsiter.
+ * @param __CR2__ copy of SPI CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
@@ -607,15 +608,16 @@
* @arg SPI_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
+ (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
* This parameter can be a value of @ref SPI_Mode
* @retval None
*/
-#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
- ((__MODE__) == SPI_MODE_MASTER))
+#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
+ ((__MODE__) == SPI_MODE_MASTER))
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Direction Mode.
@@ -663,33 +665,33 @@
* This parameter can be a value of @ref SPI_Clock_Polarity
* @retval None
*/
-#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
- ((__CPOL__) == SPI_POLARITY_HIGH))
+#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
+ ((__CPOL__) == SPI_POLARITY_HIGH))
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
* @param __CPHA__ specifies the SPI Clock Phase.
* This parameter can be a value of @ref SPI_Clock_Phase
* @retval None
*/
-#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
- ((__CPHA__) == SPI_PHASE_2EDGE))
+#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
+ ((__CPHA__) == SPI_PHASE_2EDGE))
/** @brief Checks if SPI Slave Select parameter is in allowed range.
* @param __NSS__ specifies the SPI Slave Select management parameter.
* This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None
*/
-#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
- ((__NSS__) == SPI_NSS_HARD_INPUT) || \
- ((__NSS__) == SPI_NSS_HARD_OUTPUT))
+#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
+ ((__NSS__) == SPI_NSS_HARD_INPUT) || \
+ ((__NSS__) == SPI_NSS_HARD_OUTPUT))
/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
* @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
* This parameter can be a value of @ref SPI_NSSP_Mode
* @retval None
*/
-#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
- ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
+#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
+ ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
@@ -710,16 +712,16 @@
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
* @retval None
*/
-#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
- ((__BIT__) == SPI_FIRSTBIT_LSB))
+#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
+ ((__BIT__) == SPI_FIRSTBIT_LSB))
/** @brief Checks if SPI TI mode parameter is in allowed range.
* @param __MODE__ specifies the SPI TI mode.
* This parameter can be a value of @ref SPI_TI_mode
* @retval None
*/
-#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
- ((__MODE__) == SPI_TIMODE_ENABLE))
+#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
+ ((__MODE__) == SPI_TIMODE_ENABLE))
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
@@ -734,8 +736,8 @@
* This parameter can be a value of @ref SPI_CRC_length
* @retval None
*/
-#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\
- ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
+#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
+ ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
@@ -743,7 +745,9 @@
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
* @retval None
*/
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U))
+#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
+ ((__POLYNOMIAL__) <= 0xFFFFU) && \
+ (((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
diff --git a/Inc/stm32l5xx_hal_sram.h b/Inc/stm32l5xx_hal_sram.h
index d116aa4..5d4820c 100644
--- a/Inc/stm32l5xx_hal_sram.h
+++ b/Inc/stm32l5xx_hal_sram.h
@@ -61,7 +61,7 @@
typedef struct __SRAM_HandleTypeDef
#else
typedef struct
-#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
@@ -76,10 +76,10 @@
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */
- void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */
- void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */
- void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */
+ void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
+ void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
+ void (* DmaXferCpltCallback)(DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */
+ void (* DmaXferErrorCallback)(DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */
#endif
} SRAM_HandleTypeDef;
@@ -93,7 +93,7 @@
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
-}HAL_SRAM_CallbackIDTypeDef;
+} HAL_SRAM_CallbackIDTypeDef;
/**
* @brief HAL SRAM Callback pointer definition
@@ -109,8 +109,8 @@
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
- * @{
- */
+ * @{
+ */
/** @brief Reset SRAM handle state
* @param __HANDLE__ SRAM handle
@@ -136,11 +136,12 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
- * @{
- */
+ * @{
+ */
/* Initialization/de-initialization functions ********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
@@ -150,27 +151,37 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
- * @{
- */
+ * @{
+ */
/* I/O operation functions ***************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize);
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/* SRAM callback registering/unregistering */
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_DmaCallbackTypeDef pCallback);
#endif
/**
@@ -178,8 +189,8 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
- * @{
- */
+ * @{
+ */
/* SRAM Control functions ****************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
@@ -190,8 +201,8 @@
*/
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @{
- */
+ * @{
+ */
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
diff --git a/Inc/stm32l5xx_hal_tim.h b/Inc/stm32l5xx_hal_tim.h
index cfaad6c..515cfd7 100644
--- a/Inc/stm32l5xx_hal_tim.h
+++ b/Inc/stm32l5xx_hal_tim.h
@@ -319,6 +319,16 @@
} HAL_TIM_ChannelStateTypeDef;
/**
+ * @brief DMA Burst States definition
+ */
+typedef enum
+{
+ HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
+ HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
+ HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
+} HAL_TIM_DMABurstStateTypeDef;
+
+/**
* @brief HAL Active channel structures definition
*/
typedef enum
@@ -350,6 +360,7 @@
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
+ __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
@@ -389,35 +400,35 @@
*/
typedef enum
{
- HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
- ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
- ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
- ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
- ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
- ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
- ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
- ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
- ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
- ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
- ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
- ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
- ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
- ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
+ , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
+ , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
+ , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
+ , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
+ , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
+ , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
+ , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
+ , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
+ , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
+ , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
+ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
+ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
+ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
- ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
- ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
- ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
- ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
- ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
- ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
- ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
- ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
- ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
+ , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
+ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
+ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
+ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
+ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
+ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
+ , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
+ , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
+ , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
} HAL_TIM_CallbackIDTypeDef;
/**
@@ -911,7 +922,7 @@
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
-#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
+#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
(if none of the break inputs BRK and BRK2 is active) */
/**
* @}
@@ -1145,6 +1156,7 @@
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->IC_MspInitCallback = NULL; \
@@ -1173,6 +1185,7 @@
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
+ (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
} while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@@ -2002,6 +2015,8 @@
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
+
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
@@ -2253,9 +2268,15 @@
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+ uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
+ uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -2305,6 +2326,7 @@
/* Peripheral Channel state functions ************************************************/
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_tim_ex.h b/Inc/stm32l5xx_hal_tim_ex.h
index 3a766ad..7dfe059 100644
--- a/Inc/stm32l5xx_hal_tim_ex.h
+++ b/Inc/stm32l5xx_hal_tim_ex.h
@@ -199,14 +199,14 @@
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
-#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
- ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFECU) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM3) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFEFU) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM15) && ((((__REMAP__) & 0xFFFFFFFEU) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
- || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
+#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
+ ((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFECU) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM2) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM3) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFEFU) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM15) && ((((__REMAP__) & 0xFFFFFFFEU) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))) \
+ || (((__INSTANCE__) == TIM17) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
diff --git a/Inc/stm32l5xx_hal_uart.h b/Inc/stm32l5xx_hal_uart.h
index 40d6972..f6906e4 100644
--- a/Inc/stm32l5xx_hal_uart.h
+++ b/Inc/stm32l5xx_hal_uart.h
@@ -188,6 +188,17 @@
} UART_ClockSourceTypeDef;
/**
+ * @brief HAL UART Reception type definition
+ * @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
+ * It is expected to admit following values :
+ * HAL_UART_RECEPTION_STANDARD = 0x00U,
+ * HAL_UART_RECEPTION_TOIDLE = 0x01U,
+ * HAL_UART_RECEPTION_TORTO = 0x02U,
+ * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U,
+ */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
@@ -219,6 +230,8 @@
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
+ __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@@ -250,6 +263,7 @@
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */
void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */
+ void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */
@@ -284,6 +298,7 @@
* @brief HAL UART Callback pointer definition
*/
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -776,6 +791,16 @@
* @}
*/
+/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+ * @{
+ */
+#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
+#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */
+#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */
+#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */
+/**
+ * @}
+ */
/**
* @}
@@ -1173,7 +1198,7 @@
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
-#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)\
+ (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
@@ -1182,7 +1207,7 @@
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
@@ -1191,7 +1216,7 @@
* @param __CLOCKPRESCALER__ UART prescaler value.
* @retval Division result
*/
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Check whether or not UART instance is Low Power UART.
@@ -1511,6 +1536,11 @@
#include "stm32l5xx_hal_uart_ex.h"
+/* Prescaler Table used in BRR computation macros.
+ Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
+extern const uint16_t UARTPrescTable[12];
+
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UART_Exported_Functions UART Exported Functions
* @{
@@ -1534,6 +1564,9 @@
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
pUART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
@@ -1572,6 +1605,8 @@
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
/**
* @}
*/
@@ -1617,13 +1652,15 @@
* @{
*/
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout);
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/**
* @}
diff --git a/Inc/stm32l5xx_hal_uart_ex.h b/Inc/stm32l5xx_hal_uart_ex.h
index 1321493..7d2f035 100644
--- a/Inc/stm32l5xx_hal_uart_ex.h
+++ b/Inc/stm32l5xx_hal_uart_ex.h
@@ -174,6 +174,10 @@
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
/**
* @}
*/
diff --git a/Inc/stm32l5xx_hal_usart.h b/Inc/stm32l5xx_hal_usart.h
index 231eaca..91a294f 100644
--- a/Inc/stm32l5xx_hal_usart.h
+++ b/Inc/stm32l5xx_hal_usart.h
@@ -48,11 +48,15 @@
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
- Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]
+ Baud Rate Register[15:4] = ((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
- Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1
- where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.
- @note Oversampling by 8 is systematically applied to achieve high baud rates. */
+ Baud Rate Register[2:0] = (((2 * fclk_pres) /
+ ((huart->Init.BaudRate)))[3:0]) >> 1
+ where fclk_pres is the USART input clock frequency (fclk)
+ divided by a prescaler.
+ @note Oversampling by 8 is systematically applied to
+ achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USARTEx_Word_Length. */
@@ -550,9 +554,12 @@
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
@@ -572,10 +579,12 @@
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
- ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
-
+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
+ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
+ ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
+ ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \
+ ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -598,7 +607,8 @@
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
- & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
+ & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
+ USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
@@ -620,10 +630,13 @@
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
- (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
- (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET)
-
+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
+ (__HANDLE__)->Instance->CR1 : \
+ (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
+ (__HANDLE__)->Instance->CR2 : \
+ (__HANDLE__)->Instance->CR3)) & (0x01U <<\
+ (((uint16_t)(__INTERRUPT__)) &\
+ USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the USART Handle.
@@ -707,11 +720,12 @@
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user.
- * @param __CLOCKPRESCALER__ UART prescaler value.
+ * @param __CLOCKPRESCALER__ USART prescaler value.
* @retval Division result
*/
-#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
- + ((__BAUD__)/2U)) / (__BAUD__))
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
+ (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+ + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Report the USART clock source.
* @param __HANDLE__ specifies the USART Handle.
diff --git a/Inc/stm32l5xx_hal_wwdg.h b/Inc/stm32l5xx_hal_wwdg.h
index af7d849..81730c9 100644
--- a/Inc/stm32l5xx_hal_wwdg.h
+++ b/Inc/stm32l5xx_hal_wwdg.h
@@ -56,7 +56,7 @@
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
- uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
+ uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
@@ -68,17 +68,17 @@
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
- void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
+ void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
- void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
-#endif
+ void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
@@ -87,8 +87,8 @@
*/
typedef enum
{
- HAL_WWDG_EWI_CB_ID = 0x00u, /*!< WWDG EWI callback ID */
- HAL_WWDG_MSPINIT_CB_ID = 0x01u, /*!< WWDG MspInit callback ID */
+ HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
+ HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
} HAL_WWDG_CallbackIDTypeDef;
/**
@@ -96,7 +96,7 @@
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -268,9 +268,10 @@
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
diff --git a/Inc/stm32l5xx_ll_adc.h b/Inc/stm32l5xx_ll_adc.h
index 2922f0e..2cbb89c 100644
--- a/Inc/stm32l5xx_ll_adc.h
+++ b/Inc/stm32l5xx_ll_adc.h
@@ -58,7 +58,8 @@
#define ADC_SQR3_REGOFFSET (0x00000200UL)
#define ADC_SQR4_REGOFFSET (0x00000300UL)
-#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
+ | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
@@ -95,7 +96,8 @@
#define ADC_JDR3_REGOFFSET (0x00000200UL)
#define ADC_JDR4_REGOFFSET (0x00000300UL)
-#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
+ | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
@@ -178,7 +180,8 @@
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
-#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
+ | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
@@ -200,24 +203,25 @@
/* Definition of channels ID number information to be inserted into */
/* channels literals definition. */
#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
-#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
-#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
-#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
-#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
-#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
-#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
-#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
+#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
+#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
+ ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
+#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
/* Definition of channels ID bitfield information to be inserted into */
/* channels literals definition. */
@@ -321,7 +325,8 @@
#define ADC_OFR2_REGOFFSET (0x00000001UL)
#define ADC_OFR3_REGOFFSET (0x00000002UL)
#define ADC_OFR4_REGOFFSET (0x00000003UL)
-#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
+ | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
/* ADC registers bits positions */
@@ -347,7 +352,6 @@
#define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
-
/**
* @}
*/
@@ -394,7 +398,7 @@
{
uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
- @note On this STM32 serie, if ADC group injected is used, some
+ @note On this STM32 series, if ADC group injected is used, some
clock ratio constraints between ADC clock and AHB clock
must be respected. Refer to reference manual.
@@ -481,7 +485,7 @@
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
@@ -541,7 +545,7 @@
{
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
- @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
+ @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
@@ -615,7 +619,7 @@
#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
@@ -648,7 +652,7 @@
#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#if defined(ADC_MULTIMODE_SUPPORT)
#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
@@ -683,7 +687,7 @@
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
-#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */
@@ -706,7 +710,7 @@
* @{
*/
#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
+#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
@@ -839,11 +843,11 @@
* @{
*/
#define LL_ADC_REG_DFSDM_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */
-#define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
+#define LL_ADC_REG_DFSDM_TRANSFER_ENABLE (ADC_CFGR_DFSDMCFG) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */
/**
* @}
*/
-#endif
+#endif /* ADC_CFGR_DFSDMCFG */
#if defined(ADC_SMPR1_SMPPLUS)
/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
@@ -1265,7 +1269,7 @@
/* configuration (system clock versus ADC clock), */
/* and therefore must be defined in user application. */
/* Indications for estimation of ADC timeout delays, for this */
-/* STM32 serie: */
+/* STM32 series: */
/* - ADC calibration time: maximum delay is 112/fADC. */
/* (refer to device datasheet, parameter "tCAL") */
/* - ADC enable time: maximum delay is 1 conversion cycle. */
@@ -1287,22 +1291,22 @@
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tstart_vrefint"). */
/* Unit: us */
-#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
+#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
/* Delay for temperature sensor stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
/* Delay required between ADC end of calibration and ADC enable. */
-/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles */
/* are required between ADC end of calibration and ADC enable. */
/* Wait time can be computed in user application by waiting for the */
/* equivalent number of CPU cycles, by taking into account */
/* ratio of CPU clock versus ADC clock prescalers. */
/* Unit: ADC clock cycles. */
-#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
/**
* @}
@@ -1388,10 +1392,10 @@
* @retval Value between Min_Data=0 and Max_Data=18
*/
#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
- ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
- ? ( \
+ ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
+ ( \
((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
- ) \
+ ) \
: \
( \
(uint32_t)POSITION_VAL((__CHANNEL__)) \
@@ -1440,12 +1444,12 @@
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
- (((__DECIMAL_NB__) <= 9UL) \
- ? ( \
+ (((__DECIMAL_NB__) <= 9UL) ? \
+ ( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
(ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
- ) \
+ ) \
: \
( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
@@ -1598,20 +1602,20 @@
* Value "1" if the internal channel selected is available on the ADC instance selected.
*/
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
- (((__ADC_INSTANCE__) == ADC1) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
- ) \
- : \
- ((__ADC_INSTANCE__) == ADC2) \
- ? ( \
- ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
- ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
- ) \
- : \
- (0UL) \
+ (((__ADC_INSTANCE__) == ADC1) ? \
+ ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
+ ) \
+ : \
+ ((__ADC_INSTANCE__) == ADC2) ? \
+ ( \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) || \
+ ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) \
+ ) \
+ : \
+ (0UL) \
)
/**
@@ -1843,7 +1847,7 @@
*/
#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
(((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
#if defined(ADC_MULTIMODE_SUPPORT)
/**
@@ -1865,7 +1869,7 @@
: \
(__ADCx__) \
)
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Helper macro to select the ADC common instance
@@ -1886,7 +1890,7 @@
#else
#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
(ADC1_COMMON)
-#endif
+#endif /* defined(ADC1) && defined(ADC2) && defined(ADC3) */
/**
* @brief Helper macro to check if all ADC instances sharing the same
@@ -1917,7 +1921,7 @@
#else
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(LL_ADC_IsEnabled(ADC1))
-#endif
+#endif /* defined(ADC1) && defined(ADC2) && defined(ADC3) */
/**
* @brief Helper macro to define the ADC conversion data full-scale digital
@@ -1955,11 +1959,11 @@
*/
#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
- __ADC_RESOLUTION_TARGET__) \
- (((__DATA__) \
- << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
- >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
- )
+ __ADC_RESOLUTION_TARGET__) \
+(((__DATA__) \
+ << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
+)
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
@@ -1979,10 +1983,10 @@
*/
#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
- __ADC_RESOLUTION__) \
- ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
- / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
- )
+ __ADC_RESOLUTION__) \
+((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
+)
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
@@ -1994,7 +1998,7 @@
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
- * @note On this STM32 serie, calibration data of internal voltage reference
+ * @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
@@ -2010,11 +2014,12 @@
* @retval Analog reference voltage (unit: mV)
*/
#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
- / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
- (__ADC_RESOLUTION__), \
- LL_ADC_RESOLUTION_12B))
+ __ADC_RESOLUTION__) \
+(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+)
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -2043,7 +2048,7 @@
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
- * @note On this STM32 serie, calibration data of temperature sensor
+ * @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
@@ -2063,17 +2068,17 @@
*/
#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
- (__ADC_RESOLUTION__), \
- LL_ADC_RESOLUTION_12B) \
- * (__VREFANALOG_VOLTAGE__)) \
- / TEMPSENSOR_CAL_VREFANALOG) \
- - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
- ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
- ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
- ) + TEMPSENSOR_CAL1_TEMP \
- )
+ __ADC_RESOLUTION__) \
+(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
+ (__ADC_RESOLUTION__), \
+ LL_ADC_RESOLUTION_12B) \
+ * (__VREFANALOG_VOLTAGE__)) \
+ / TEMPSENSOR_CAL_VREFANALOG) \
+ - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
+ ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
+ ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+ ) + TEMPSENSOR_CAL1_TEMP \
+)
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
@@ -2124,18 +2129,17 @@
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
- __ADC_RESOLUTION__) \
- ((( ( \
- (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
- / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
- * 1000UL) \
- - \
- (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
- * 1000UL) \
- ) \
- ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
- ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
- )
+ __ADC_RESOLUTION__) \
+(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
+ * 1000UL) \
+ - \
+ (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
+ * 1000UL) \
+ ) \
+ ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
+)
/**
* @}
@@ -2191,7 +2195,7 @@
#if defined(ADC_MULTIMODE_SUPPORT)
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
{
@@ -2215,7 +2219,7 @@
/* Retrieve address of register DR */
return (uint32_t) &(ADCx->DR);
}
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
@@ -2227,11 +2231,11 @@
/**
* @brief Set parameter common to several ADC: Clock source and prescaler.
- * @note On this STM32 serie, if ADC group injected is used, some
+ * @note On this STM32 series, if ADC group injected is used, some
* clock ratio constraints between ADC clock and AHB clock
* must be respected.
* Refer to reference manual.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2311,7 +2315,7 @@
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2352,7 +2356,7 @@
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2382,7 +2386,7 @@
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -2452,7 +2456,7 @@
* both calibration factors must be concatenated.
* To perform this processing, use helper macro
* @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
@@ -2495,14 +2499,16 @@
/* "SingleDiff". */
/* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
/* containing other bits reserved for other purpose. */
- return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+ return (uint32_t)(READ_BIT(ADCx->CALFACT,
+ (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
+ ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
}
/**
* @brief Set ADC resolution.
* Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2541,7 +2547,7 @@
* @brief Set ADC conversion data alignment.
* @note Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2612,7 +2618,7 @@
* Therefore, the ADC conversion data may be outdated: does not
* correspond to the current voltage level on the selected
* ADC channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2694,7 +2700,7 @@
* to disable state using function LL_ADC_SetOffsetState().
* @note If a channel is mapped on several offsets numbers, only the offset
* with the lowest value is considered for the subtraction.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2753,7 +2759,7 @@
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg,
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
@@ -2824,7 +2830,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
}
@@ -2850,7 +2856,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
}
@@ -2862,7 +2868,7 @@
* @note This function should be needed only in case of offset to be
* enabled-disabled dynamically, and should not be needed in other cases:
* function LL_ADC_SetOffset() automatically enables the offset.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2883,7 +2889,7 @@
*/
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg,
ADC_OFR1_OFFSET1_EN,
@@ -2909,7 +2915,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
}
@@ -2918,7 +2924,7 @@
/**
* @brief Set ADC sampling time common configuration impacting
* settings of sampling time channel wise.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -2961,7 +2967,7 @@
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting trigger source to external trigger
+ * @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
@@ -2969,7 +2975,7 @@
* function @ref LL_ADC_REG_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3037,11 +3043,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
{
- register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+ __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
- register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+ uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
/* to match with triggers literals definition. */
@@ -3070,7 +3076,7 @@
/**
* @brief Set ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3131,7 +3137,7 @@
* function "LL_ADC_REG_SetSequencerChannels()".
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3223,7 +3229,7 @@
* continuous mode and sequencer discontinuous mode.
* @note It is not possible to enable both ADC auto-injected mode
* and ADC group regular sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3276,17 +3282,17 @@
* @note This function performs configuration of:
* - Channels ordering into each rank of scan sequence:
* whatever channel can be placed into whatever rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3362,7 +3368,7 @@
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
@@ -3372,7 +3378,7 @@
/**
* @brief Get ADC group regular sequence: channel on the selected
* scan sequence rank.
- * @note On this STM32 serie, ADC group regular sequencer is
+ * @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
@@ -3459,7 +3465,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
return (uint32_t)((READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
@@ -3475,7 +3481,7 @@
* conversions launched successively automatically.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3530,7 +3536,7 @@
* settings are available using function @ref LL_ADC_SetMultiDMATransfer().
* @note To configure DMA source address (peripheral address),
* use function @ref LL_ADC_DMA_GetRegAddr().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3590,7 +3596,7 @@
* @note To configure DFSDM source address (peripheral address),
* use the same function as for DMA transfer:
* function @ref LL_ADC_DMA_GetRegAddr().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -3618,7 +3624,7 @@
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DFSDMCFG));
}
-#endif
+#endif /* ADC_CFGR_DFSDMCFG */
/**
* @brief Set ADC group regular behavior in case of overrun:
@@ -3629,7 +3635,7 @@
* The default setting of overrun is data preserved.
* Therefore, for compatibility with all devices, parameter
* overrun should be set to data overwritten.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
@@ -3671,7 +3677,7 @@
* @brief Set ADC group injected conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
- * @note On this STM32 serie, setting trigger source to external trigger
+ * @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
@@ -3679,7 +3685,7 @@
* function @ref LL_ADC_INJ_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -3747,11 +3753,11 @@
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
{
- register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+ __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
- register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+ uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
/* to match with triggers literals definition. */
@@ -3780,7 +3786,7 @@
/**
* @brief Set ADC group injected conversion trigger polarity.
* Applicable only for trigger source set to external trigger.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -3820,7 +3826,7 @@
* scan direction is forward (from rank 1 to rank n).
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -3897,13 +3903,13 @@
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32L5, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4047,7 +4053,7 @@
* from ADC group regular.
* @note It is not possible to enable both ADC group injected
* auto-injected mode and sequencer discontinuous mode.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4105,7 +4111,7 @@
* on either groups regular or injected.
* @note A modification of the context mode (bit JQDIS) causes the contexts
* queue to be flushed and the register JSQR is cleared.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4155,13 +4161,13 @@
* @arg @ref LL_ADC_INJ_GetTriggerSource()
* @arg @ref LL_ADC_INJ_GetTriggerEdge()
* @arg @ref LL_ADC_INJ_GetSequencerRanks()
- * @note On this STM32 serie, to measure internal channels (VrefInt,
+ * @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32L5, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN0..5).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
@@ -4340,7 +4346,7 @@
/* because containing other bits reserved for other purpose. */
/* If parameter "TriggerSource" is set to SW start, then parameter */
/* "ExternalTriggerEdge" is discarded. */
- register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+ uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
MODIFY_REG(ADCx->JSQR,
ADC_JSQR_JEXTSEL |
ADC_JSQR_JEXTEN |
@@ -4380,7 +4386,7 @@
* Refer to device datasheet for timings values (parameters TS_vrefint,
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 serie, ADC processing time is:
+ * On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
@@ -4389,7 +4395,7 @@
* temperature sensor, ...), a sampling time minimum value
* is required.
* Refer to device datasheet.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4464,7 +4470,7 @@
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
@@ -4477,7 +4483,7 @@
* @note On this device, sampling time is on channel scope: independently
* of channel mapped on ADC group regular or injected.
* @note Conversion time is the addition of sampling time and processing time.
- * On this STM32 serie, ADC processing time is:
+ * On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
@@ -4548,7 +4554,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
@@ -4576,7 +4582,7 @@
* @note For ADC channels configured in differential mode, both inputs
* should be biased at (Vref+)/2 +/-200mV.
* (Vref+ is the analog voltage reference)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @note One or several values can be selected.
@@ -4676,7 +4682,7 @@
* @note In case of need to define a single channel to monitor
* with analog watchdog from sequencer channel definition,
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -4697,7 +4703,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4800,8 +4806,8 @@
/* in register and register position depending on parameter "AWDy". */
/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
/* containing other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
- + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
MODIFY_REG(*preg,
(AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
@@ -4823,7 +4829,7 @@
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Applicable only when the analog watchdog is set to monitor
* one channel.
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -4844,7 +4850,7 @@
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -4932,10 +4938,10 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
- + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
- register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+ uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
/* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
/* (parameter value LL_ADC_AWD_DISABLE). */
@@ -4994,7 +5000,7 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5019,7 +5025,7 @@
* impacted: the comparison of analog watchdog thresholds is done on
* oversampling final computation (after ratio and shift application):
* ADC data register bitfield [15:4] (12 most significant bits).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5046,7 +5052,7 @@
/* "AWDy". */
/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
/* containing other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_TR1_HT1 | ADC_TR1_LT1,
@@ -5061,7 +5067,7 @@
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
- * @note On this STM32 serie, there are 2 kinds of analog watchdog
+ * @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
@@ -5086,7 +5092,7 @@
* impacted: the comparison of analog watchdog thresholds is done on
* oversampling final computation (after ratio and shift application):
* ADC data register bitfield [15:4] (12 most significant bits).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either ADC groups regular or injected.
@@ -5115,7 +5121,8 @@
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
- register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+ ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
MODIFY_REG(*preg,
AWDThresholdsHighLow,
@@ -5152,12 +5159,13 @@
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+ ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
(AWDThresholdsHighLow | ADC_TR1_LT1))
- >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
- );
+ >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
+ & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
}
/**
@@ -5177,7 +5185,7 @@
* the oversampling on ADC group regular is either
* temporary stopped and continued, or resumed from start
* (oversampler buffer reset).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5231,11 +5239,11 @@
* are done from 1 trigger)
* - discontinuous mode (each conversion of oversampling ratio
* needs a trigger)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
- * @note On this STM32 serie, oversampling discontinuous mode
+ * @note On this STM32 series, oversampling discontinuous mode
* (triggered mode) can be used only when oversampling is
* set on group regular only and in resumed mode.
* @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
@@ -5275,7 +5283,7 @@
* @note This function set the 2 items of oversampling configuration:
* - ratio
* - shift
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
@@ -5364,7 +5372,7 @@
* @note If multimode configuration: the selected ADC instance is
* either master or slave depending on hardware.
* Refer to reference manual.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -5443,7 +5451,7 @@
* A macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled
* or enabled without conversion on going on group regular.
@@ -5517,7 +5525,7 @@
* - ADC resolution 10 bits can have maximum delay of 10 cycles.
* - ADC resolution 8 bits can have maximum delay of 8 cycles.
* - ADC resolution 6 bits can have maximum delay of 6 cycles.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
@@ -5592,7 +5600,7 @@
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
@@ -5615,7 +5623,7 @@
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
@@ -5643,12 +5651,12 @@
/**
* @brief Enable ADC instance internal voltage regulator.
- * @note On this STM32 serie, after ADC internal voltage regulator enable,
+ * @note On this STM32 series, after ADC internal voltage regulator enable,
* a delay for ADC internal voltage regulator stabilization
* is required before performing a ADC calibration or ADC enable.
* Refer to device datasheet, parameter tADCVREG_STUP.
* Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
@@ -5667,7 +5675,7 @@
/**
* @brief Disable ADC internal voltage regulator.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
@@ -5692,14 +5700,14 @@
/**
* @brief Enable the selected ADC instance.
- * @note On this STM32 serie, after ADC enable, a delay for
+ * @note On this STM32 series, after ADC enable, a delay for
* ADC internal analog stabilization is required before performing a
* ADC conversion start.
* Refer to device datasheet, parameter tSTAB.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled and ADC internal voltage regulator enabled.
* @rmtoll CR ADEN LL_ADC_Enable
@@ -5718,7 +5726,7 @@
/**
* @brief Disable the selected ADC instance.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be not disabled. Must be enabled without conversion on going
* on either groups regular or injected.
@@ -5738,7 +5746,7 @@
/**
* @brief Get the selected ADC instance enable state.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll CR ADEN LL_ADC_IsEnabled
@@ -5764,7 +5772,7 @@
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
- * @note On this STM32 serie, a minimum number of ADC clock cycles
+ * @note On this STM32 series, a minimum number of ADC clock cycles
* are required between ADC end of calibration and ADC enable.
* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
* @note For devices with differential mode available:
@@ -5773,7 +5781,7 @@
* (calibration run must be performed for each of these
* differential modes, if used afterwards and if the application
* requires their calibration).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADCAL LL_ADC_StartCalibration\n
@@ -5815,14 +5823,14 @@
/**
* @brief Start ADC group regular conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
@@ -5843,7 +5851,7 @@
/**
* @brief Stop ADC group regular conversion.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group regular,
* without ADC disable command on going.
@@ -5998,14 +6006,14 @@
/**
* @brief Start ADC group injected conversion.
- * @note On this STM32 serie, this function is relevant for both
+ * @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group injected,
* without conversion stop command on going on group injected,
@@ -6026,7 +6034,7 @@
/**
* @brief Stop ADC group injected conversion.
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group injected,
* without ADC disable command on going.
@@ -6085,7 +6093,7 @@
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6112,7 +6120,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6139,7 +6147,7 @@
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6166,7 +6174,7 @@
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6193,7 +6201,7 @@
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
{
- register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
@@ -6210,7 +6218,7 @@
/**
* @brief Get flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
@@ -6334,7 +6342,7 @@
/**
* @brief Clear flag ADC ready.
- * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+ * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
diff --git a/Inc/stm32l5xx_ll_comp.h b/Inc/stm32l5xx_ll_comp.h
index 8a3d438..7730a9d 100644
--- a/Inc/stm32l5xx_ll_comp.h
+++ b/Inc/stm32l5xx_ll_comp.h
@@ -306,7 +306,7 @@
*/
__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)
{
- /* Note: On this STM32 serie, window mode can be set only */
+ /* Note: On this STM32 series, window mode can be set only */
/* from COMP instance: COMP2. */
MODIFY_REG(COMPxy_COMMON->CSR, COMP_CSR_WINMODE, WindowMode);
}
@@ -376,7 +376,7 @@
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
- * @note On this STM32 serie, scaler bridge is configurable:
+ * @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
@@ -452,7 +452,7 @@
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
- * @note On this STM32 serie, scaler bridge is configurable:
+ * @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
diff --git a/Inc/stm32l5xx_ll_crs.h b/Inc/stm32l5xx_ll_crs.h
index 799a0cf..664861a 100644
--- a/Inc/stm32l5xx_ll_crs.h
+++ b/Inc/stm32l5xx_ll_crs.h
@@ -94,7 +94,7 @@
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
-#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal soucre GPIO */
+#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
diff --git a/Inc/stm32l5xx_ll_dac.h b/Inc/stm32l5xx_ll_dac.h
index cedd9b2..ca6b719 100644
--- a/Inc/stm32l5xx_ll_dac.h
+++ b/Inc/stm32l5xx_ll_dac.h
@@ -324,7 +324,7 @@
* @{
*/
#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */
-#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
+#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
/**
* @}
*/
@@ -899,7 +899,7 @@
* - @ref LL_DAC_SetOutputBuffer()
* - @ref LL_DAC_SetOutputMode()
* - @ref LL_DAC_SetOutputConnection()
- * @note On this STM32 serie, output connection depends on output mode
+ * @note On this STM32 series, output connection depends on output mode
* (normal or sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
@@ -988,7 +988,7 @@
/**
* @brief Set the output buffer for the selected DAC channel.
- * @note On this STM32 serie, when buffer is enabled, its offset can be
+ * @note On this STM32 series, when buffer is enabled, its offset can be
* trimmed: factory calibration default values can be
* replaced by user trimming values, using function
* @ref LL_DAC_SetTrimmingValue().
@@ -1031,7 +1031,7 @@
/**
* @brief Set the output connection for the selected DAC channel.
- * @note On this STM32 serie, output connection depends on output mode (normal or
+ * @note On this STM32 series, output connection depends on output mode (normal or
* sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
@@ -1061,7 +1061,7 @@
/**
* @brief Get the output connection for the selected DAC channel.
- * @note On this STM32 serie, output connection depends on output mode (normal or
+ * @note On this STM32 series, output connection depends on output mode (normal or
* sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
diff --git a/Inc/stm32l5xx_ll_dma.h b/Inc/stm32l5xx_ll_dma.h
index c870e34..2f27735 100644
--- a/Inc/stm32l5xx_ll_dma.h
+++ b/Inc/stm32l5xx_ll_dma.h
@@ -374,11 +374,11 @@
* @}
*/
-/** @defgroup DMA_LL_SEC_PRIVILEDGE_MODE PRIVILEDGE MODE
+/** @defgroup DMA_LL_SEC_PRIVILEGE_MODE PRIVILEGE MODE
* @{
*/
-#define LL_DMA_CHANNEL_NPRIV 0x00000000U /*!< Disable priviledge */
-#define LL_DMA_CHANNEL_PRIV DMA_CCR_PRIV /*!< Enable priviledge */
+#define LL_DMA_CHANNEL_NPRIV 0x00000000U /*!< Disable privilege transfer to the destination */
+#define LL_DMA_CHANNEL_PRIV DMA_CCR_PRIV /*!< Enable privilege transfer to the destination */
/**
* @}
*/
@@ -1436,7 +1436,7 @@
/**
* @brief Configure the Source and Destination addresses.
* @note This API must not be called when the DMA channel is enabled.
- * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
+ * @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
* CM0AR MA LL_DMA_ConfigAddresses
* @param DMAx DMAx Instance
diff --git a/Inc/stm32l5xx_ll_dmamux.h b/Inc/stm32l5xx_ll_dmamux.h
index eb75da9..9adb64d 100644
--- a/Inc/stm32l5xx_ll_dmamux.h
+++ b/Inc/stm32l5xx_ll_dmamux.h
@@ -306,9 +306,9 @@
#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */
#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */
#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */
-#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Ouput */
-#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Ouput */
-#define LL_DMAMUX_SYNC_LPTIM3_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from LPTIM3 Ouput */
+#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */
+#define LL_DMAMUX_SYNC_LPTIM2_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from LPTIM2 Output */
+#define LL_DMAMUX_SYNC_LPTIM3_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from LPTIM3 Output */
/**
* @}
*/
@@ -358,9 +358,9 @@
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */
-#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Ouput */
-#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Ouput */
-#define LL_DMAMUX_REQ_GEN_LPTIM3_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from LPTIM3 Ouput */
+#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */
+#define LL_DMAMUX_REQ_GEN_LPTIM2_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from LPTIM2 Output */
+#define LL_DMAMUX_REQ_GEN_LPTIM3_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from LPTIM3 Output */
/**
* @}
*/
diff --git a/Inc/stm32l5xx_ll_exti.h b/Inc/stm32l5xx_ll_exti.h
index 251aa5f..38ffe9b 100644
--- a/Inc/stm32l5xx_ll_exti.h
+++ b/Inc/stm32l5xx_ll_exti.h
@@ -1078,7 +1078,7 @@
/**
* @brief Generate a software Interrupt Event for Lines in range 32 to 63
- * @note If the interrupt is enabled on this line inthe EXTI_IMR, writing a 1 to
+ * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
* resulting in an interrupt request generation.
* This bit is cleared by clearing the corresponding bit in the EXTI_PR
diff --git a/Inc/stm32l5xx_ll_fmc.h b/Inc/stm32l5xx_ll_fmc.h
index 420e9a5..585bba8 100644
--- a/Inc/stm32l5xx_ll_fmc.h
+++ b/Inc/stm32l5xx_ll_fmc.h
@@ -41,51 +41,51 @@
*/
#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
- ((__BANK__) == FMC_NORSRAM_BANK2) || \
- ((__BANK__) == FMC_NORSRAM_BANK3) || \
- ((__BANK__) == FMC_NORSRAM_BANK4))
+ ((__BANK__) == FMC_NORSRAM_BANK2) || \
+ ((__BANK__) == FMC_NORSRAM_BANK3) || \
+ ((__BANK__) == FMC_NORSRAM_BANK4))
#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
- ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
+ ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
- ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
- ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
+ ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
+ ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
- ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
+ ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
- ((__SIZE__) == FMC_PAGE_SIZE_128) || \
- ((__SIZE__) == FMC_PAGE_SIZE_256) || \
- ((__SIZE__) == FMC_PAGE_SIZE_512) || \
- ((__SIZE__) == FMC_PAGE_SIZE_1024))
+ ((__SIZE__) == FMC_PAGE_SIZE_128) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_256) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_512) || \
+ ((__SIZE__) == FMC_PAGE_SIZE_1024))
#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
- ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
+ ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
- ((__MODE__) == FMC_ACCESS_MODE_B) || \
- ((__MODE__) == FMC_ACCESS_MODE_C) || \
- ((__MODE__) == FMC_ACCESS_MODE_D))
+ ((__MODE__) == FMC_ACCESS_MODE_B) || \
+ ((__MODE__) == FMC_ACCESS_MODE_C) || \
+ ((__MODE__) == FMC_ACCESS_MODE_D))
#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \
- ((__NBL__) == FMC_NBL_SETUPTIME_1) || \
- ((__NBL__) == FMC_NBL_SETUPTIME_2) || \
- ((__NBL__) == FMC_NBL_SETUPTIME_3))
+ ((__NBL__) == FMC_NBL_SETUPTIME_1) || \
+ ((__NBL__) == FMC_NBL_SETUPTIME_2) || \
+ ((__NBL__) == FMC_NBL_SETUPTIME_3))
#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
- ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
+ ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
- ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
+ ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
- ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
+ ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
- ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
+ ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
- ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
+ ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
- ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
+ ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
- ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
+ ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
- ((__BURST__) == FMC_WRITE_BURST_ENABLE))
+ ((__BURST__) == FMC_WRITE_BURST_ENABLE))
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
- ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
+ ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
@@ -99,18 +99,18 @@
#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
- ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
+ ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
- ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
+ ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
- ((__STATE__) == FMC_NAND_ECC_ENABLE))
+ ((__STATE__) == FMC_NAND_ECC_ENABLE))
#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
- ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
+ ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
@@ -454,7 +454,8 @@
#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
-#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
+#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0\
+ | FMC_BCRx_CPSIZE_1))
#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2)
/**
* @}
@@ -487,9 +488,9 @@
* @}
*/
- /** @defgroup FMC_Access_Mode FMC Access Mode
+/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
- */
+*/
#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
@@ -606,7 +607,7 @@
/**
* @}
*/
-
+
/* Private macro -------------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
* @{
@@ -622,7 +623,8 @@
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
-#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN)
+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+ |= FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
@@ -630,16 +632,17 @@
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
-#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)
+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
+ &= ~FMC_BCRx_MBKEN)
/**
* @}
*/
/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
- * @brief macros to handle NAND device enable/disable
- * @{
- */
+ * @brief macros to handle NAND device enable/disable
+ * @{
+ */
/**
* @brief Enable the NAND device access.
@@ -740,10 +743,14 @@
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
* @{
*/
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_InitTypeDef *Init);
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
@@ -767,8 +774,10 @@
* @{
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
@@ -779,7 +788,8 @@
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout);
/**
* @}
*/
diff --git a/Inc/stm32l5xx_ll_gpio.h b/Inc/stm32l5xx_ll_gpio.h
index ce8bbbf..326ab8b 100644
--- a/Inc/stm32l5xx_ll_gpio.h
+++ b/Inc/stm32l5xx_ll_gpio.h
@@ -943,7 +943,8 @@
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
- WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
}
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
diff --git a/Inc/stm32l5xx_ll_i2c.h b/Inc/stm32l5xx_ll_i2c.h
index 6690ccb..af98570 100644
--- a/Inc/stm32l5xx_ll_i2c.h
+++ b/Inc/stm32l5xx_ll_i2c.h
@@ -67,38 +67,38 @@
typedef struct
{
uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
- This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
+ This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
This parameter must be set by referring to the STM32CubeMX Tool and
- the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
+ the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
- This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
+ This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
uint32_t DigitalFilter; /*!< Configures the digital noise filter.
- This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
+ This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
uint32_t OwnAddress1; /*!< Specifies the device own address 1.
- This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
+ This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
- This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
+ This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
- This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
+ This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
} LL_I2C_InitTypeDef;
@@ -360,11 +360,11 @@
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
- ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
- (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
- (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
- (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
- (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
+ ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
+ (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
+ (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
+ (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
+ (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
/**
* @}
*/
@@ -578,17 +578,17 @@
*/
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
{
/* return address of TXDR register */
- data_reg_addr = (uint32_t) & (I2Cx->TXDR);
+ data_reg_addr = (uint32_t) &(I2Cx->TXDR);
}
else
{
/* return address of RXDR register */
- data_reg_addr = (uint32_t) & (I2Cx->RXDR);
+ data_reg_addr = (uint32_t) &(I2Cx->RXDR);
}
return data_reg_addr;
@@ -664,7 +664,7 @@
/**
* @brief Enable Wakeup from STOP.
- * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when Digital Filter is disabled.
* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
@@ -678,7 +678,7 @@
/**
* @brief Disable Wakeup from STOP.
- * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
* @param I2Cx I2C Instance.
@@ -691,7 +691,7 @@
/**
* @brief Check if Wakeup from STOP is enabled or disabled.
- * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
* @param I2Cx I2C Instance.
@@ -941,7 +941,7 @@
/**
* @brief Configure peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
* CR1 SMBDEN LL_I2C_SetMode
@@ -960,7 +960,7 @@
/**
* @brief Get peripheral mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
* CR1 SMBDEN LL_I2C_GetMode
@@ -978,7 +978,7 @@
/**
* @brief Enable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is drived low and
@@ -996,7 +996,7 @@
/**
* @brief Disable SMBus alert (Host or Device mode)
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
@@ -1014,7 +1014,7 @@
/**
* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
* @param I2Cx I2C Instance.
@@ -1027,7 +1027,7 @@
/**
* @brief Enable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
* @param I2Cx I2C Instance.
@@ -1040,7 +1040,7 @@
/**
* @brief Disable SMBus Packet Error Calculation (PEC).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
* @param I2Cx I2C Instance.
@@ -1053,7 +1053,7 @@
/**
* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
* @param I2Cx I2C Instance.
@@ -1066,7 +1066,7 @@
/**
* @brief Configure the SMBus Clock Timeout.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
@@ -1089,7 +1089,7 @@
/**
* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
@@ -1104,7 +1104,7 @@
/**
* @brief Get the SMBus Clock TimeoutA setting.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
* @param I2Cx I2C Instance.
@@ -1117,7 +1117,7 @@
/**
* @brief Set the SMBus Clock TimeoutA mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
@@ -1134,7 +1134,7 @@
/**
* @brief Get the SMBus Clock TimeoutA mode.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
* @param I2Cx I2C Instance.
@@ -1149,7 +1149,7 @@
/**
* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutB is disabled.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
@@ -1163,8 +1163,8 @@
}
/**
- * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
* @param I2Cx I2C Instance.
@@ -1177,7 +1177,7 @@
/**
* @brief Enable the SMBus Clock Timeout.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
@@ -1195,7 +1195,7 @@
/**
* @brief Disable the SMBus Clock Timeout.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
@@ -1213,7 +1213,7 @@
/**
* @brief Check if the SMBus Clock Timeout is enabled or disabled.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
@@ -1443,7 +1443,7 @@
/**
* @brief Enable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
@@ -1463,7 +1463,7 @@
/**
* @brief Disable Error interrupts.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
@@ -1645,7 +1645,7 @@
/**
* @brief Indicate the status of SMBus PEC error flag in reception.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When the received PEC does not match with the PEC register content.
@@ -1660,7 +1660,7 @@
/**
* @brief Indicate the status of SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When a timeout or extended clock timeout occurs.
@@ -1675,7 +1675,7 @@
/**
* @brief Indicate the status of SMBus alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When SMBus host configuration, SMBus alert enabled and
@@ -1782,7 +1782,7 @@
/**
* @brief Clear SMBus PEC error flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
* @param I2Cx I2C Instance.
@@ -1795,7 +1795,7 @@
/**
* @brief Clear SMBus Timeout detection flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
@@ -1808,7 +1808,7 @@
/**
* @brief Clear SMBus Alert flag.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
* @param I2Cx I2C Instance.
@@ -2090,7 +2090,9 @@
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
}
@@ -2123,7 +2125,7 @@
/**
* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
* This bit has no effect when RELOAD bit is set.
@@ -2139,7 +2141,7 @@
/**
* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
* @param I2Cx I2C Instance.
@@ -2152,12 +2154,12 @@
/**
* @brief Get the SMBus Packet Error byte calculated.
- * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
+ * @note Macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
-*/
+ */
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
diff --git a/Inc/stm32l5xx_ll_lptim.h b/Inc/stm32l5xx_ll_lptim.h
index d433c27..27c5486 100644
--- a/Inc/stm32l5xx_ll_lptim.h
+++ b/Inc/stm32l5xx_ll_lptim.h
@@ -159,7 +159,7 @@
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
-#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
+#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
/**
* @}
@@ -366,7 +366,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
@@ -419,7 +419,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
}
/**
@@ -785,7 +785,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
@@ -1048,7 +1048,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
@@ -1078,7 +1078,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
@@ -1100,7 +1100,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
@@ -1122,7 +1122,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
@@ -1144,7 +1144,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
@@ -1166,7 +1166,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
@@ -1188,7 +1188,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
@@ -1210,7 +1210,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
@@ -1295,7 +1295,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
@@ -1328,7 +1328,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
@@ -1361,7 +1361,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
@@ -1394,7 +1394,7 @@
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
@@ -1423,11 +1423,11 @@
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
@@ -1456,11 +1456,11 @@
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
- return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
+ return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
@@ -1489,11 +1489,11 @@
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
- return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
+ return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**
@@ -1522,7 +1522,7 @@
* @brief Indicates whether the repetition register update successfully completed interrupt (REPOKIE) is enabled.
* @rmtoll IER REPOKIE LL_LPTIM_IsEnabledIT_REPOK
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ * @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_REPOK(LPTIM_TypeDef *LPTIMx)
{
@@ -1555,7 +1555,7 @@
* @brief Indicates whether the update event interrupt (UEIE) is enabled.
* @rmtoll IER UEIE LL_LPTIM_IsEnabledIT_UE
* @param LPTIMx Low-Power Timer instance
- * @retval State of bit (1 or 0).
+ *@ retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UE(LPTIM_TypeDef *LPTIMx)
{
diff --git a/Inc/stm32l5xx_ll_lpuart.h b/Inc/stm32l5xx_ll_lpuart.h
index 1600d96..21e190d 100644
--- a/Inc/stm32l5xx_ll_lpuart.h
+++ b/Inc/stm32l5xx_ll_lpuart.h
@@ -267,18 +267,18 @@
/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
-#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
-#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
-#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
-#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
-#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
-#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
-#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
-#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
-#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
-#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
-#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
-#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
+#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
@@ -1345,7 +1345,10 @@
__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t BaudRate)
{
- LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+ if (BaudRate != 0U)
+ {
+ LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+ }
}
/**
@@ -1372,9 +1375,9 @@
*/
__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
{
- register uint32_t lpuartdiv;
- register uint32_t brrresult;
- register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+ uint32_t lpuartdiv;
+ uint32_t brrresult;
+ uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
@@ -2482,7 +2485,7 @@
*/
__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
{
diff --git a/Inc/stm32l5xx_ll_opamp.h b/Inc/stm32l5xx_ll_opamp.h
index 7c746f6..5545388 100644
--- a/Inc/stm32l5xx_ll_opamp.h
+++ b/Inc/stm32l5xx_ll_opamp.h
@@ -144,8 +144,8 @@
/** @defgroup OPAMP_LL_EC_POWERSUPPLY_RANGE OPAMP power supply range
* @{
*/
-#define LL_OPAMP_POWERSUPPLY_RANGE_LOW 0x00000000U /*!< Power supply range low. On STM32L5 serie: Vdda lower than 2.4V. */
-#define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP1_CSR_OPARANGE) /*!< Power supply range high. On STM32L5 serie: Vdda higher than 2.4V. */
+#define LL_OPAMP_POWERSUPPLY_RANGE_LOW 0x00000000U /*!< Power supply range low. On STM32L5 series: Vdda lower than 2.4V. */
+#define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP1_CSR_OPARANGE) /*!< Power supply range high. On STM32L5 series: Vdda higher than 2.4V. */
/**
* @}
*/
@@ -359,7 +359,7 @@
* @brief Set OPAMP power range.
* @note The OPAMP power range applies to several OPAMP instances
* (if several OPAMP instances available on the selected device).
- * @note On this STM32 serie, setting of this feature is conditioned to
+ * @note On this STM32 series, setting of this feature is conditioned to
* OPAMP state:
* All OPAMP instances of the OPAMP common group must be disabled.
* This check can be done with function @ref LL_OPAMP_IsEnabled() for each
@@ -433,7 +433,7 @@
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
{
- register uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPALPM));
+ uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPALPM));
return (uint32_t)(power_mode | (power_mode >> (OPAMP_CSR_OPALPM_Pos)));
}
@@ -446,7 +446,7 @@
* @ref LL_OPAMP_SetFunctionalMode().
* - calibration mode: offset calibration of the selected
* transistors differential pair NMOS or PMOS.
- * @note On this STM32 serie, during calibration, OPAMP functional
+ * @note On this STM32 series, during calibration, OPAMP functional
* mode must be set to standalone or follower mode
* (in order to open internal connections to resistors
* of PGA mode).
@@ -707,7 +707,7 @@
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
{
- register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
+ uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
return (CalibrationSelection |
(((CalibrationSelection & OPAMP_CSR_CALSEL) == 0UL) ? OPAMP_OTR_TRIMOFFSETN : OPAMP_OTR_TRIMOFFSETP));
@@ -747,7 +747,7 @@
*/
__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
{
- register uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+ uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
/* Set bits with position in register depending on parameter */
/* "TransistorsDiffPair". */
@@ -777,7 +777,7 @@
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)
{
- register const uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
+ const uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));
/* Retrieve bits with position in register depending on parameter */
/* "TransistorsDiffPair". */
@@ -797,7 +797,7 @@
/**
* @brief Enable OPAMP instance.
* @note After enable from off state, OPAMP requires a delay
- * to fullfill wake up time specification.
+ * to fulfill wake up time specification.
* Refer to device datasheet, parameter "tWAKEUP".
* @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
* @param OPAMPx OPAMP instance
diff --git a/Inc/stm32l5xx_ll_pwr.h b/Inc/stm32l5xx_ll_pwr.h
index fbbd7f9..0928d10 100644
--- a/Inc/stm32l5xx_ll_pwr.h
+++ b/Inc/stm32l5xx_ll_pwr.h
@@ -493,13 +493,11 @@
* to disable it in all cases, either to stop this pull-down or to hand over
* control to the UCPD (which should therefore be initialized before doing the disable).
* @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
- * @retval State of bit.
+ * @retval State of feature (1 : enabled; 0 : disabled).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
{
-
- return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 1UL : 0UL);
-
+ return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
}
/**
diff --git a/Inc/stm32l5xx_ll_rcc.h b/Inc/stm32l5xx_ll_rcc.h
index f6fe93b..2963597 100644
--- a/Inc/stm32l5xx_ll_rcc.h
+++ b/Inc/stm32l5xx_ll_rcc.h
@@ -191,7 +191,7 @@
/** @defgroup RCC_LL_EC_LSIPRE LSI prescaler
* @{
*/
-#define LL_RCC_LSI_DIV_1 0x00000000U /*!< LSI divided by 1 */
+#define LL_RCC_LSI_DIV_1 0UL /*!< LSI divided by 1 */
#define LL_RCC_LSI_DIV_128 RCC_CSR_LSIPRE /*!< LSI divided by 128 */
/**
* @}
@@ -200,7 +200,7 @@
/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
* @{
*/
-#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
+#define LL_RCC_LSEDRIVE_LOW 0UL /*!< Xtal mode lower driving capability */
#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
@@ -211,18 +211,18 @@
/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
* @{
*/
-#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /*!< MSI = 100 KHz */
-#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /*!< MSI = 200 KHz */
-#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /*!< MSI = 400 KHz */
-#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /*!< MSI = 800 KHz */
-#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /*!< MSI = 1 MHz */
-#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /*!< MSI = 2 MHz */
-#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /*!< MSI = 4 MHz */
-#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /*!< MSI = 8 MHz */
-#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /*!< MSI = 16 MHz */
-#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /*!< MSI = 24 MHz */
-#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /*!< MSI = 32 MHz */
-#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /*!< MSI = 48 MHz */
+#define LL_RCC_MSIRANGE_0 0UL /*!< MSI = 100 kHz */
+#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_0 /*!< MSI = 200 kHz */
+#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_1 /*!< MSI = 400 kHz */
+#define LL_RCC_MSIRANGE_3 (RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 800 kHz */
+#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_2 /*!< MSI = 1 MHz */
+#define LL_RCC_MSIRANGE_5 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_0) /*!< MSI = 2 MHz */
+#define LL_RCC_MSIRANGE_6 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1) /*!< MSI = 4 MHz */
+#define LL_RCC_MSIRANGE_7 (RCC_CR_MSIRANGE_2 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 8 MHz */
+#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_3 /*!< MSI = 16 MHz */
+#define LL_RCC_MSIRANGE_9 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_0) /*!< MSI = 24 MHz */
+#define LL_RCC_MSIRANGE_10 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1) /*!< MSI = 32 MHz */
+#define LL_RCC_MSIRANGE_11 (RCC_CR_MSIRANGE_3 | RCC_CR_MSIRANGE_1 | RCC_CR_MSIRANGE_0) /*!< MSI = 48 MHz */
/**
* @}
*/
@@ -230,10 +230,10 @@
/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
* @{
*/
-#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /*!< MSI = 1 MHz */
-#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /*!< MSI = 2 MHz */
-#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /*!< MSI = 4 MHz */
-#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /*!< MSI = 8 MHz */
+#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_2 /*!< MSI = 1 MHz */
+#define LL_RCC_MSISRANGE_5 (RCC_CSR_MSISRANGE_2 | RCC_CSR_MSISRANGE_0) /*!< MSI = 2 MHz */
+#define LL_RCC_MSISRANGE_6 (RCC_CSR_MSISRANGE_2 | RCC_CSR_MSISRANGE_1) /*!< MSI = 4 MHz */
+#define LL_RCC_MSISRANGE_7 (RCC_CSR_MSISRANGE_2 | RCC_CSR_MSISRANGE_1 | RCC_CSR_MSISRANGE_0) /*!< MSI = 8 MHz */
/**
* @}
*/
@@ -241,8 +241,8 @@
/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
* @{
*/
-#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
-#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
+#define LL_RCC_LSCO_CLKSOURCE_LSI 0UL /*!< LSI selection for low speed clock */
+#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
/**
* @}
*/
@@ -250,10 +250,10 @@
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
* @{
*/
-#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_MSI 0UL /*!< MSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_0 /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_1 /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW /*!< PLL selection as system clock */
/**
* @}
*/
@@ -261,10 +261,10 @@
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
* @{
*/
-#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI 0UL /*!< MSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_0 /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_1 /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS /*!< PLL used as system clock */
/**
* @}
*/
@@ -272,39 +272,39 @@
/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
* @{
*/
-#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+#define LL_RCC_SYSCLK_DIV_1 0UL /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 512 */
/**
* @}
*/
-/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
+/** @defgroup RCC_LL_EC_APB1_DIV APB1 prescaler
* @{
*/
-#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+#define LL_RCC_APB1_DIV_1 0UL /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_0) /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE1_2 | RCC_CFGR_PPRE1_1) /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1 /*!< HCLK divided by 16 */
/**
* @}
*/
-/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
+/** @defgroup RCC_LL_EC_APB2_DIV APB2 prescaler
* @{
*/
-#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
-#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
-#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
-#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
-#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+#define LL_RCC_APB2_DIV_1 0UL /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_2 /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_0) /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8 (RCC_CFGR_PPRE2_2 | RCC_CFGR_PPRE2_1) /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2 /*!< HCLK divided by 16 */
/**
* @}
*/
@@ -312,7 +312,7 @@
/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
* @{
*/
-#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */
+#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0UL /*!< MSI selection after wake-up from STOP */
#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */
/**
* @}
@@ -321,7 +321,7 @@
/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
* @{
*/
-#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
+#define LL_RCC_MCO1SOURCE_NOCLOCK 0UL /*!< MCO output disabled, no clock on MCO */
#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /*!< MSI selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
@@ -337,11 +337,11 @@
/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
* @{
*/
-#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
-#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
-#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
-#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
-#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
+#define LL_RCC_MCO1_DIV_1 0UL /*!< MCO not divided */
+#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO divided by 2 */
+#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO divided by 4 */
+#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO divided by 8 */
+#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO divided by 16 */
/**
* @}
*/
@@ -350,8 +350,8 @@
/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
* @{
*/
-#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
-#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
+#define LL_RCC_PERIPH_FREQUENCY_NO 0UL /*!< No clock enabled for the peripheral */
+#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFUL /*!< Frequency cannot be provided as external clock */
/**
* @}
*/
@@ -360,7 +360,7 @@
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
* @{
*/
-#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_NONE 0UL /*!< No clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
@@ -405,7 +405,7 @@
/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection
* @{
*/
-#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
+#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0UL /*!< PCLK1 clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR1_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR1_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR1_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
@@ -454,7 +454,7 @@
/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection
* @{
*/
-#define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN kernel clock source */
+#define LL_RCC_FDCAN_CLKSOURCE_HSE 0UL /*!< HSE clock used as FDCAN kernel clock source */
#define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR1_FDCANSEL_0 /*!< PLL clock used as FDCAN kernel clock source */
#define LL_RCC_FDCAN_CLKSOURCE_PLLSAI1 RCC_CCIPR1_FDCANSEL_1 /*!< PLLSAI1 clock used as FDCAN kernel clock source */
/**
@@ -481,7 +481,7 @@
/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
* @{
*/
-#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */
+#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0UL /*!< 48MHz clock from internal multiplexor used as SDMMC1 clock source */
#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /*!< PLLP clock (PLLSAI3CLK) used as SDMMC1 clock source */
/**
* @}
@@ -490,7 +490,7 @@
/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
* @{
*/
-#define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1 clock source in internal multiplexor */
+#define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0UL /*!< HSI48 clock used as SDMMC1 clock source in internal multiplexor */
#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 clock used as SDMMC1 clock source in internal multiplexor */
#define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLLQ clock used as SDMMC1 clock source in internal multiplexor */
#define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI clock used as SDMMC1 clock source in internal multiplexor */
@@ -501,7 +501,7 @@
/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
* @{
*/
-#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
+#define LL_RCC_RNG_CLKSOURCE_HSI48 0UL /*!< HSI48 clock used as RNG clock source */
#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 clock used as RNG clock source */
#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL clock used as RNG clock source */
#define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI clock used as RNG clock source */
@@ -512,7 +512,7 @@
/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
* @{
*/
-#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
+#define LL_RCC_USB_CLKSOURCE_HSI48 0UL /*!< HSI48 clock used as USB clock source */
#define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR1_CLK48MSEL_0 /*!< PLLSAI1 clock used as USB clock source */
#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR1_CLK48MSEL_1 /*!< PLL clock used as USB clock source */
#define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR1_CLK48MSEL /*!< MSI clock used as USB clock source */
@@ -523,7 +523,7 @@
/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADCx clock source selection
* @{
*/
-#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as ADC clock source */
+#define LL_RCC_ADC_CLKSOURCE_NONE 0UL /*!< No clock used as ADC clock source */
#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR1_ADCSEL_0 /*!< PLLSAI1 clock used as ADC clock source */
#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR1_ADCSEL /*!< SYSCLK clock used as ADC clock source */
/**
@@ -533,7 +533,7 @@
/** @defgroup RCC_LL_EC_DFSDM_AUDIO_CLKSOURCE Peripheral DFSDMx Audio clock source selection
* @{
*/
-#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0UL /*!< SAI1 clock used as DFSDM1 Audio clock */
#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDMSEL_0 /*!< HSI clock used as DFSDM1 Audio clock */
#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDMSEL_1 /*!< MSI clock used as DFSDM1 Audio clock */
/**
@@ -543,7 +543,7 @@
/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
* @{
*/
-#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock source */
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0UL /*!< PCLK2 clock used as DFSDM1 clock source */
#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDMSEL /*!< SYSCLK clock used as DFSDM1 clock source */
/**
* @}
@@ -552,7 +552,7 @@
/** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection
* @{
*/
-#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as OctoSPI kernel clock source */
+#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0UL /*!< SYSCLK clock used as OctoSPI kernel clock source */
#define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /*!< MSI clock used as OctoSPI kernel clock source */
#define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /*!< PLL clock used as OctoSPI kernel clock source */
/**
@@ -691,10 +691,10 @@
/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
* @{
*/
-#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as main PLL entry clock source */
-#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /*!< MSI clock selected as main PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as main PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as main PLL entry clock source */
+#define LL_RCC_PLLSOURCE_NONE 0UL /*!< No clock selected as main PLL entry clock source */
+#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_0 /*!< MSI clock selected as main PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_1 /*!< HSI16 clock selected as main PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE (RCC_PLLCFGR_PLLSRC_1 | RCC_PLLCFGR_PLLSRC_0) /*!< HSE clock selected as main PLL entry clock source */
/**
* @}
*/
@@ -702,7 +702,7 @@
/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
* @{
*/
-#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< Main PLL division factor for PLLM input by 1 */
+#define LL_RCC_PLLM_DIV_1 0UL /*!< Main PLL division factor for PLLM input by 1 */
#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 2 */
#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /*!< Main PLL division factor for PLLM input by 3 */
#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< Main PLL division factor for PLLM input by 4 */
@@ -725,7 +725,7 @@
/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
* @{
*/
-#define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
+#define LL_RCC_PLLR_DIV_2 0UL /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
@@ -773,7 +773,7 @@
/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
* @{
*/
-#define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
+#define LL_RCC_PLLQ_DIV_2 0UL /*!< Main PLL division factor for PLLQ output by 2 */
#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
@@ -784,10 +784,10 @@
/** @defgroup RCC_LL_EC_PLLSAI1SOURCE PLLSAI1 entry clock source
* @{
*/
-#define LL_RCC_PLLSAI1SOURCE_NONE 0x00000000U /*!< No clock selected as PLLSAI1 entry clock source */
-#define LL_RCC_PLLSAI1SOURCE_MSI RCC_PLLSAI1CFGR_PLLSAI1SRC_MSI /*!< MSI clock selected as PLLSAI1 entry clock source */
-#define LL_RCC_PLLSAI1SOURCE_HSI RCC_PLLSAI1CFGR_PLLSAI1SRC_HSI /*!< HSI16 clock selected as PLLSAI1 entry clock source */
-#define LL_RCC_PLLSAI1SOURCE_HSE RCC_PLLSAI1CFGR_PLLSAI1SRC_HSE /*!< HSE clock selected as PLLSAI1 entry clock source */
+#define LL_RCC_PLLSAI1SOURCE_NONE 0UL /*!< No clock selected as PLLSAI1 entry clock source */
+#define LL_RCC_PLLSAI1SOURCE_MSI RCC_PLLSAI1CFGR_PLLSAI1SRC_0 /*!< MSI clock selected as PLLSAI1 entry clock source */
+#define LL_RCC_PLLSAI1SOURCE_HSI RCC_PLLSAI1CFGR_PLLSAI1SRC_1 /*!< HSI16 clock selected as PLLSAI1 entry clock source */
+#define LL_RCC_PLLSAI1SOURCE_HSE (RCC_PLLSAI1CFGR_PLLSAI1SRC_1 | RCC_PLLSAI1CFGR_PLLSAI1SRC_0) /*!< HSE clock selected as PLLSAI1 entry clock source */
/**
* @}
*/
@@ -795,7 +795,7 @@
/** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M)
* @{
*/
-#define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */
+#define LL_RCC_PLLSAI1M_DIV_1 0UL /*!< PLLSAI1 division factor for PLLSAI1M input by 1 */
#define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 2 */
#define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /*!< PLLSAI1 division factor for PLLSAI1M input by 3 */
#define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1|RCC_PLLSAI1CFGR_PLLSAI1M_0) /*!< PLLSAI1 division factor for PLLSAI1M input by 4 */
@@ -818,7 +818,7 @@
/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
* @{
*/
-#define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
+#define LL_RCC_PLLSAI1Q_DIV_2 0UL /*!< PLLSAI1 division factor for PLLSAI1Q output by 2 */
#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /*!< PLLSAI1 division factor for PLLSAI1Q output by 4 */
#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /*!< PLLSAI1 division factor for PLLSAI1Q output by 6 */
#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /*!< PLLSAI1 division factor for PLLSAI1Q output by 8 */
@@ -866,7 +866,7 @@
/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
* @{
*/
-#define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
+#define LL_RCC_PLLSAI1R_DIV_2 0UL /*!< PLLSAI1 division factor for PLLSAI1R output by 2 */
#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /*!< PLLSAI1 division factor for PLLSAI1R output by 4 */
#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /*!< PLLSAI1 division factor for PLLSAI1R output by 6 */
#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /*!< PLLSAI1 division factor for PLLSAI1R output by 8 */
@@ -877,10 +877,10 @@
/** @defgroup RCC_LL_EC_PLLSAI2SOURCE PLLSAI2 entry clock source
* @{
*/
-#define LL_RCC_PLLSAI2SOURCE_NONE 0x00000000U /*!< No clock selected as PLLSAI2 entry clock source */
-#define LL_RCC_PLLSAI2SOURCE_MSI RCC_PLLSAI2CFGR_PLLSAI2SRC_MSI /*!< MSI clock selected as PLLSAI2 entry clock source */
-#define LL_RCC_PLLSAI2SOURCE_HSI RCC_PLLSAI2CFGR_PLLSAI2SRC_HSI /*!< HSI16 clock selected as PLLSAI2 entry clock source */
-#define LL_RCC_PLLSAI2SOURCE_HSE RCC_PLLSAI2CFGR_PLLSAI2SRC_HSE /*!< HSE clock selected as PLLSAI2 entry clock source */
+#define LL_RCC_PLLSAI2SOURCE_NONE 0UL /*!< No clock selected as PLLSAI2 entry clock source */
+#define LL_RCC_PLLSAI2SOURCE_MSI RCC_PLLSAI2CFGR_PLLSAI2SRC_0 /*!< MSI clock selected as PLLSAI2 entry clock source */
+#define LL_RCC_PLLSAI2SOURCE_HSI RCC_PLLSAI2CFGR_PLLSAI2SRC_1 /*!< HSI16 clock selected as PLLSAI2 entry clock source */
+#define LL_RCC_PLLSAI2SOURCE_HSE (RCC_PLLSAI2CFGR_PLLSAI2SRC_1 | RCC_PLLSAI2CFGR_PLLSAI2SRC_0) /*!< HSE clock selected as PLLSAI2 entry clock source */
/**
* @}
*/
@@ -888,7 +888,7 @@
/** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI2 division factor (PLLSAI2M)
* @{
*/
-#define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */
+#define LL_RCC_PLLSAI2M_DIV_1 0UL /*!< PLLSAI2 division factor for PLLSAI2M input by 1 */
#define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 2 */
#define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /*!< PLLSAI2 division factor for PLLSAI2M input by 3 */
#define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1|RCC_PLLSAI2CFGR_PLLSAI2M_0) /*!< PLLSAI2 division factor for PLLSAI2M input by 4 */
diff --git a/Inc/stm32l5xx_ll_rng.h b/Inc/stm32l5xx_ll_rng.h
index ccdc308..96ce5b1 100644
--- a/Inc/stm32l5xx_ll_rng.h
+++ b/Inc/stm32l5xx_ll_rng.h
@@ -57,8 +57,8 @@
{
uint32_t ClockErrorDetection; /*!< Clock error detection.
This parameter can be one value of @ref RNG_LL_CED.
-
- This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */
+ This parameter can be modified using unitary
+ functions @ref LL_RNG_EnableClkErrorDetect(). */
} LL_RNG_InitTypeDef;
/**
@@ -80,40 +80,25 @@
*/
/** @defgroup RNG_LL_Clock_Divider_Factor Value used to configure an internal
- * programmable divider acting on the incoming RNG clock
+ * programmable divider acting on the incoming RNG clock
* @{
*/
-#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
-#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0)
- /*!< 2 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1)
- /*!< 4 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
- /*!< 8 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2)
- /*!< 16 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
- /*!< 32 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
- /*!< 64 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
- /*!< 128 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3)
- /*!< 256 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
- /*!< 512 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
- /*!< 1024 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
- /*!< 2048 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
- /*!< 4096 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
- /*!< 8192 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
- /*!< 16384 RNG clock cycles per internal RNG clock */
-#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
- /*!< 32768 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_1 (0x00000000UL) /*!< No clock division */
+#define LL_RNG_CLKDIV_BY_2 (RNG_CR_CLKDIV_0) /*!< 2 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_4 (RNG_CR_CLKDIV_1) /*!< 4 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_8 (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 8 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_16 (RNG_CR_CLKDIV_2) /*!< 16 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_32 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 32 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_64 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 64 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_128 (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 128 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_256 (RNG_CR_CLKDIV_3) /*!< 256 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_512 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0) /*!< 512 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_1024 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1) /*!< 1024 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_2048 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 2048 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_4096 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2) /*!< 4096 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_8192 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0) /*!< 8192 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_16384 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1) /*!< 16384 RNG clock cycles per internal RNG clock */
+#define LL_RNG_CLKDIV_BY_32768 (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0) /*!< 32768 RNG clock cycles per internal RNG clock */
/**
* @}
*/
@@ -127,6 +112,7 @@
/**
* @}
*/
+
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RNG_ReadReg function
* @{
@@ -269,7 +255,7 @@
*/
__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)
{
- SET_BIT(RNGx->CR, RNG_CR_CONDRST);
+ SET_BIT(RNGx->CR, RNG_CR_CONDRST);
}
/**
@@ -302,7 +288,7 @@
*/
__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)
{
- SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
+ SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);
}
/**
@@ -324,7 +310,7 @@
*/
__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)
{
- CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
+ CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);
}
/**
@@ -624,7 +610,7 @@
* @}
*/
-#if defined (RNG_VER_3_1)
+#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control
* @{
*/
@@ -655,7 +641,7 @@
/**
* @}
*/
-#endif /*RNG_VER_3_1*/
+#endif /* RNG_VER_3_2, RNG_VER_3_1 or RNG_VER_3_0 */
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
@@ -687,6 +673,6 @@
}
#endif
-#endif /* STM32L5xx_LL_RNG_H */
+#endif /* __STM32L5xx_LL_RNG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Inc/stm32l5xx_ll_rtc.h b/Inc/stm32l5xx_ll_rtc.h
index 844f99d..4557e30 100644
--- a/Inc/stm32l5xx_ll_rtc.h
+++ b/Inc/stm32l5xx_ll_rtc.h
@@ -1496,7 +1496,7 @@
*/
__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- register uint32_t temp;
+ uint32_t temp;
temp = Format12_24 | \
(((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
@@ -1524,7 +1524,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
- register uint32_t temp;
+ uint32_t temp;
temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
@@ -1826,7 +1826,7 @@
*/
__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)
{
- register uint32_t temp;
+ uint32_t temp;
temp = (WeekDay << RTC_DR_WDU_Pos) | \
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
@@ -1854,7 +1854,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
{
- register uint32_t temp;
+ uint32_t temp;
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
@@ -2154,7 +2154,7 @@
*/
__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- register uint32_t temp;
+ uint32_t temp;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
@@ -2520,7 +2520,7 @@
*/
__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)
{
- register uint32_t temp;
+ uint32_t temp;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
@@ -3476,7 +3476,7 @@
*/
__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
{
- register uint32_t tmp;
+ uint32_t tmp;
UNUSED(RTCx);
@@ -3502,7 +3502,7 @@
*/
__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
{
- register uint32_t tmp;
+ uint32_t tmp;
UNUSED(RTCx);
diff --git a/Inc/stm32l5xx_ll_sdmmc.h b/Inc/stm32l5xx_ll_sdmmc.h
index 67fbdfb..f2b50bf 100644
--- a/Inc/stm32l5xx_ll_sdmmc.h
+++ b/Inc/stm32l5xx_ll_sdmmc.h
@@ -63,8 +63,8 @@
This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */
#if (USE_SD_TRANSCEIVER != 0U)
- uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Tranceiver/Switcher.
- This parameter can be a value of @ref SDMMC_LL_TRANCEIVER_PRESENT */
+ uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher.
+ This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */
#endif /* USE_SD_TRANSCEIVER */
}SDMMC_InitTypeDef;
@@ -370,11 +370,11 @@
#define SDMMC_SPEED_MODE_ULTRA ((uint32_t)0x00000003U)
#define SDMMC_SPEED_MODE_DDR ((uint32_t)0x00000004U)
-#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
- ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
- ((MODE) == SDMMC_SPEED_MODE_HIGH) || \
- ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
- ((MODE) == SDMMC_SPEED_MODE_DDR))
+#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \
+ ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \
+ ((MODE) == SDMMC_SPEED_MODE_HIGH) || \
+ ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \
+ ((MODE) == SDMMC_SPEED_MODE_DDR))
/**
* @}
@@ -401,7 +401,7 @@
* @}
*/
-/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Tranceiver Present
+/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Transceiver Present
* @{
*/
#define SDMMC_TRANSCEIVER_UNKNOWN ((uint32_t)0x00000000U)
@@ -485,7 +485,7 @@
* @}
*/
-/** @defgroup SDMMC_LL_Data_Length Data Lenght
+/** @defgroup SDMMC_LL_Data_Length Data Length
* @{
*/
#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
@@ -1040,8 +1040,14 @@
/* SDMMC Cards mode management functions */
HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
+/**
+ * @}
+ */
-/* SDMMC Commands management functions */
+/* SDMMC Commands management functions ******************************************/
+/** @addtogroup HAL_SDMMC_LL_Group4
+ * @{
+ */
uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
@@ -1063,17 +1069,31 @@
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA);
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
-
/**
* @}
*/
+/* SDMMC Responses management functions *****************************************/
+/** @addtogroup HAL_SDMMC_LL_Group5
+ * @{
+ */
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
+/**
+ * @}
+ */
+
+
/**
* @}
*/
diff --git a/Inc/stm32l5xx_ll_spi.h b/Inc/stm32l5xx_ll_spi.h
index d88cc88..6105110 100644
--- a/Inc/stm32l5xx_ll_spi.h
+++ b/Inc/stm32l5xx_ll_spi.h
@@ -266,8 +266,8 @@
/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
* @{
*/
-#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */
-#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */
+#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
+#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */
/**
* @}
*/
@@ -848,8 +848,8 @@
*/
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
{
- register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
- register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
+ uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
+ uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
return (Ssm | Ssoe);
}
@@ -1314,7 +1314,7 @@
*/
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
{
- return (uint32_t) & (SPIx->DR);
+ return (uint32_t) &(SPIx->DR);
}
/**
diff --git a/Inc/stm32l5xx_ll_system.h b/Inc/stm32l5xx_ll_system.h
index eac23eb..0cfec05 100644
--- a/Inc/stm32l5xx_ll_system.h
+++ b/Inc/stm32l5xx_ll_system.h
@@ -59,13 +59,13 @@
* @{
*/
/**
- * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
+ * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
*/
#define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x0BFA0579UL)) /*!< Address of VREFBUF trimming value for VRS=0,
VREF_SC0 in STM32L5 datasheet */
#define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x0BFA0530UL)) /*!< Address of VREFBUF trimming value for VRS=1,
VREF_SC1 in STM32L5 datasheet */
-
+
/**
* @brief Power-down in Run mode Flash key
*/
@@ -861,26 +861,6 @@
}
/**
- * @brief Enable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode
- * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
- * @retval None
- */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
* @brief Enable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
* @retval None
@@ -921,6 +901,36 @@
}
/**
+ * @brief Enable the clock for Trace port
+ * @rmtoll DBGMCU_CR TRACE_EN LL_DBGMCU_EnableTraceClock
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void)
+{
+ SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_EN);
+}
+
+/**
+ * @brief Disable the clock for Trace port
+ * @rmtoll DBGMCU_CR TRACE_EN LL_DBGMCU_DisableTraceClock
+ * @retval None
+ */
+__STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void)
+{
+ CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_EN);
+}
+
+/**
+ * @brief Indicate if the clock for Trace port is enabled
+ * @rmtoll DBGMCU_CR TRACE_EN LL_DBGMCU_IsEnabledTraceClock
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void)
+{
+ return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_EN) == (DBGMCU_CR_TRACE_EN)) ? 1UL : 0UL);
+}
+
+/**
* @brief Set Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
diff --git a/Inc/stm32l5xx_ll_tim.h b/Inc/stm32l5xx_ll_tim.h
index 02cd8b3..d6b3466 100644
--- a/Inc/stm32l5xx_ll_tim.h
+++ b/Inc/stm32l5xx_ll_tim.h
@@ -612,8 +612,8 @@
*/
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
/**
* @}
@@ -2000,8 +2000,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
@@ -2045,8 +2045,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
@@ -2084,8 +2084,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
@@ -2118,7 +2118,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2150,7 +2150,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
@@ -2187,7 +2187,7 @@
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
@@ -2219,7 +2219,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
@@ -2244,8 +2244,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2270,8 +2270,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2296,9 +2296,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2322,8 +2322,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2347,8 +2347,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2372,9 +2372,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2401,8 +2401,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2428,8 +2428,8 @@
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
@@ -2457,9 +2457,9 @@
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
- register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
@@ -2728,8 +2728,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
@@ -2756,8 +2756,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2780,8 +2780,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2806,8 +2806,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2831,8 +2831,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2869,8 +2869,8 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
@@ -2906,8 +2906,8 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
- register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
@@ -2935,7 +2935,7 @@
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
@@ -2963,7 +2963,7 @@
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
- register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+ uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
@@ -3696,7 +3696,7 @@
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
SET_BIT(*pReg, Source);
}
@@ -3725,7 +3725,7 @@
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
@@ -3755,7 +3755,7 @@
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
- register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
+ __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput));
MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
/**
diff --git a/Inc/stm32l5xx_ll_ucpd.h b/Inc/stm32l5xx_ll_ucpd.h
index d20a37e..adb8692 100644
--- a/Inc/stm32l5xx_ll_ucpd.h
+++ b/Inc/stm32l5xx_ll_ucpd.h
@@ -126,8 +126,7 @@
#define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
#define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */
#define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */
-#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGEND /*!< Enable Rx message received */
-#define LL_UCPD_IMR_RXERR UCPD_IMR_RXMSGENDIE /*!< Enable Rx error */
+#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE /*!< Enable Rx message received */
#define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */
#define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */
#define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE /*!< Enable fast Role Swap detection event */
diff --git a/Inc/stm32l5xx_ll_usart.h b/Inc/stm32l5xx_ll_usart.h
index ec8b26f..4c48509 100644
--- a/Inc/stm32l5xx_ll_usart.h
+++ b/Inc/stm32l5xx_ll_usart.h
@@ -88,41 +88,49 @@
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref USART_LL_EC_PRESCALER.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetPrescaler().*/
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_LL_EC_STOPBITS.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_LL_EC_PARITY.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_DIRECTION.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetHWFlowCtrl().*/
uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
- This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+ This feature can be modified afterwards using unitary
+ function @ref LL_USART_SetOverSampling().*/
} LL_USART_InitTypeDef;
@@ -141,20 +149,23 @@
uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_LL_EC_POLARITY.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPolarity().
For more details, refer to description of this function. */
uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_LL_EC_PHASE.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetClockPhase().
For more details, refer to description of this function. */
uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
- USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+ USART HW configuration can be modified afterwards using unitary
+ functions @ref LL_USART_SetLastClkPulseOutput().
For more details, refer to description of this function. */
} LL_USART_ClockInitTypeDef;
@@ -357,18 +368,18 @@
/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
-#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */
-#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */
-#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */
-#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */
-#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */
-#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */
-#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */
-#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */
-#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */
-#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */
-#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */
-#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */
+#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
+#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
+#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
+#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
+#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
+#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
@@ -563,8 +574,9 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
- + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
@@ -586,8 +598,9 @@
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
- + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+ ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @}
@@ -645,7 +658,7 @@
/**
* @brief FIFO Mode Enable
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_EnableFIFO
* @param USARTx USART Instance
@@ -658,7 +671,7 @@
/**
* @brief FIFO Mode Disable
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_DisableFIFO
* @param USARTx USART Instance
@@ -671,7 +684,7 @@
/**
* @brief Indicate if FIFO Mode is enabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO
* @param USARTx USART Instance
@@ -684,7 +697,7 @@
/**
* @brief Configure TX FIFO Threshold
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
* @param USARTx USART Instance
@@ -704,7 +717,7 @@
/**
* @brief Return TX FIFO Threshold Configuration
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
* @param USARTx USART Instance
@@ -723,7 +736,7 @@
/**
* @brief Configure RX FIFO Threshold
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
* @param USARTx USART Instance
@@ -743,7 +756,7 @@
/**
* @brief Return RX FIFO Threshold Configuration
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
* @param USARTx USART Instance
@@ -762,7 +775,7 @@
/**
* @brief Configure TX and RX FIFOs Threshold
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n
* CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
@@ -785,14 +798,15 @@
*/
__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
- MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));
+ MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+ (RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
* @brief USART enabled in STOP Mode.
* @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
* USART clock selection is HSI or LSE in RCC.
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_EnableInStopMode
* @param USARTx USART Instance
@@ -806,7 +820,7 @@
/**
* @brief USART disabled in STOP Mode.
* @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_DisableInStopMode
* @param USARTx USART Instance
@@ -819,7 +833,7 @@
/**
* @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
* @param USARTx USART Instance
@@ -1062,7 +1076,7 @@
/**
* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
* @param USARTx USART Instance
@@ -1079,7 +1093,7 @@
/**
* @brief Retrieve Clock pulse of the last data bit output configuration
* (Last bit Clock pulse output to the SCLK pin or not)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
* @param USARTx USART Instance
@@ -1094,7 +1108,7 @@
/**
* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_SetClockPhase
* @param USARTx USART Instance
@@ -1110,7 +1124,7 @@
/**
* @brief Return phase of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_GetClockPhase
* @param USARTx USART Instance
@@ -1125,7 +1139,7 @@
/**
* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
* @param USARTx USART Instance
@@ -1141,7 +1155,7 @@
/**
* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
* @param USARTx USART Instance
@@ -1156,7 +1170,7 @@
/**
* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
@@ -1184,7 +1198,7 @@
/**
* @brief Configure Clock source prescaler for baudrate generator and oversampling
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_SetPrescaler
* @param USARTx USART Instance
@@ -1210,7 +1224,7 @@
/**
* @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_GetPrescaler
* @param USARTx USART Instance
@@ -1235,7 +1249,7 @@
/**
* @brief Enable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
* @param USARTx USART Instance
@@ -1248,7 +1262,7 @@
/**
* @brief Disable Clock output on SCLK pin
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
* @param USARTx USART Instance
@@ -1261,7 +1275,7 @@
/**
* @brief Indicate if Clock output on SCLK pin is enabled
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
* @param USARTx USART Instance
@@ -1480,7 +1494,7 @@
/**
* @brief Enable Auto Baud-Rate Detection
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
* @param USARTx USART Instance
@@ -1493,7 +1507,7 @@
/**
* @brief Disable Auto Baud-Rate Detection
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
* @param USARTx USART Instance
@@ -1506,7 +1520,7 @@
/**
* @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
* @param USARTx USART Instance
@@ -1519,7 +1533,7 @@
/**
* @brief Set Auto Baud-Rate mode bits
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
* @param USARTx USART Instance
@@ -1537,7 +1551,7 @@
/**
* @brief Return Auto Baud-Rate mode
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
* @param USARTx USART Instance
@@ -1644,7 +1658,7 @@
/**
* @brief Enable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1657,7 +1671,7 @@
/**
* @brief Disable RTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1670,7 +1684,7 @@
/**
* @brief Enable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1683,7 +1697,7 @@
/**
* @brief Disable CTS HW Flow Control
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
* @param USARTx USART Instance
@@ -1696,7 +1710,7 @@
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
* CR3 CTSE LL_USART_SetHWFlowCtrl
@@ -1715,7 +1729,7 @@
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
* CR3 CTSE LL_USART_GetHWFlowCtrl
@@ -1799,7 +1813,7 @@
/**
* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_SetWKUPType
* @param USARTx USART Instance
@@ -1816,7 +1830,7 @@
/**
* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_GetWKUPType
* @param USARTx USART Instance
@@ -1864,12 +1878,16 @@
uint32_t BaudRate)
{
uint32_t usartdiv;
- register uint32_t brrtemp;
+ uint32_t brrtemp;
if (PrescalerValue > LL_USART_PRESCALER_DIV256)
{
/* Do not overstep the size of USART_PRESCALER_TAB */
}
+ else if (BaudRate == 0U)
+ {
+ /* Can Not divide per 0 */
+ }
else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
@@ -1912,9 +1930,9 @@
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling)
{
- register uint32_t usartdiv;
- register uint32_t brrresult = 0x0U;
- register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+ uint32_t usartdiv;
+ uint32_t brrresult = 0x0U;
+ uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
usartdiv = USARTx->BRR;
@@ -1996,7 +2014,7 @@
/**
* @brief Enable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_EnableIrda
* @param USARTx USART Instance
@@ -2009,7 +2027,7 @@
/**
* @brief Disable IrDA mode
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_DisableIrda
* @param USARTx USART Instance
@@ -2022,7 +2040,7 @@
/**
* @brief Indicate if IrDA mode is enabled
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
* @param USARTx USART Instance
@@ -2035,7 +2053,7 @@
/**
* @brief Configure IrDA Power Mode (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
* @param USARTx USART Instance
@@ -2051,7 +2069,7 @@
/**
* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
* @param USARTx USART Instance
@@ -2067,7 +2085,7 @@
/**
* @brief Set Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
* @param USARTx USART Instance
@@ -2082,7 +2100,7 @@
/**
* @brief Return Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
* @param USARTx USART Instance
@@ -2103,7 +2121,7 @@
/**
* @brief Enable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
* @param USARTx USART Instance
@@ -2116,7 +2134,7 @@
/**
* @brief Disable Smartcard NACK transmission
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
* @param USARTx USART Instance
@@ -2129,7 +2147,7 @@
/**
* @brief Indicate if Smartcard NACK transmission is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
* @param USARTx USART Instance
@@ -2142,7 +2160,7 @@
/**
* @brief Enable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
* @param USARTx USART Instance
@@ -2155,7 +2173,7 @@
/**
* @brief Disable Smartcard mode
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
* @param USARTx USART Instance
@@ -2168,7 +2186,7 @@
/**
* @brief Indicate if Smartcard mode is enabled
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
* @param USARTx USART Instance
@@ -2181,7 +2199,7 @@
/**
* @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
* In transmission mode, it specifies the number of automatic retransmission retries, before
@@ -2200,7 +2218,7 @@
/**
* @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
* @param USARTx USART Instance
@@ -2214,7 +2232,7 @@
/**
* @brief Set Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
* @param USARTx USART Instance
@@ -2229,7 +2247,7 @@
/**
* @brief Return Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
* @param USARTx USART Instance
@@ -2243,7 +2261,7 @@
/**
* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
* @param USARTx USART Instance
@@ -2258,7 +2276,7 @@
/**
* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
* @param USARTx USART Instance
@@ -2279,7 +2297,7 @@
/**
* @brief Enable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
* @param USARTx USART Instance
@@ -2292,7 +2310,7 @@
/**
* @brief Disable Single Wire Half-Duplex mode
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
* @param USARTx USART Instance
@@ -2305,7 +2323,7 @@
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
* @param USARTx USART Instance
@@ -2325,7 +2343,7 @@
*/
/**
* @brief Enable SPI Synchronous Slave mode
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_EnableSPISlave
* @param USARTx USART Instance
@@ -2338,7 +2356,7 @@
/**
* @brief Disable SPI Synchronous Slave mode
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_DisableSPISlave
* @param USARTx USART Instance
@@ -2351,7 +2369,7 @@
/**
* @brief Indicate if SPI Synchronous Slave mode is enabled
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave
* @param USARTx USART Instance
@@ -2364,7 +2382,7 @@
/**
* @brief Enable SPI Slave Selection using NSS input pin
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave Selection depends on NSS input pin
* (The slave is selected when NSS is low and deselected when NSS is high).
@@ -2379,7 +2397,7 @@
/**
* @brief Disable SPI Slave Selection using NSS input pin
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave will be always selected and NSS input pin will be ignored.
* @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
@@ -2393,7 +2411,7 @@
/**
* @brief Indicate if SPI Slave Selection depends on NSS input pin
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
* @param USARTx USART Instance
@@ -2414,7 +2432,7 @@
/**
* @brief Set LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -2430,7 +2448,7 @@
/**
* @brief Return LIN Break Detection Length
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
* @param USARTx USART Instance
@@ -2445,7 +2463,7 @@
/**
* @brief Enable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_EnableLIN
* @param USARTx USART Instance
@@ -2458,7 +2476,7 @@
/**
* @brief Disable LIN mode
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_DisableLIN
* @param USARTx USART Instance
@@ -2471,7 +2489,7 @@
/**
* @brief Indicate if LIN mode is enabled
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
* @param USARTx USART Instance
@@ -2492,7 +2510,7 @@
/**
* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
* @param USARTx USART Instance
@@ -2506,7 +2524,7 @@
/**
* @brief Return DEDT (Driver Enable De-Assertion Time)
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
* @param USARTx USART Instance
@@ -2519,7 +2537,7 @@
/**
* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
* @param USARTx USART Instance
@@ -2533,7 +2551,7 @@
/**
* @brief Return DEAT (Driver Enable Assertion Time)
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
* @param USARTx USART Instance
@@ -2546,7 +2564,7 @@
/**
* @brief Enable Driver Enable (DE) Mode
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_EnableDEMode
* @param USARTx USART Instance
@@ -2559,7 +2577,7 @@
/**
* @brief Disable Driver Enable (DE) Mode
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_DisableDEMode
* @param USARTx USART Instance
@@ -2572,7 +2590,7 @@
/**
* @brief Indicate if Driver Enable (DE) Mode is enabled
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
* @param USARTx USART Instance
@@ -2585,7 +2603,7 @@
/**
* @brief Select Driver Enable Polarity
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
* @param USARTx USART Instance
@@ -2601,7 +2619,7 @@
/**
* @brief Return Driver Enable Polarity
- * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
* @param USARTx USART Instance
@@ -2665,7 +2683,7 @@
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the USART in Synchronous mode.
- * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2704,7 +2722,7 @@
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also set the UART/USART in LIN mode.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
@@ -2745,7 +2763,7 @@
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* This function also sets the UART/USART in Half Duplex mode.
- * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2785,7 +2803,7 @@
* This function also configures Stop bits to 1.5 bits and
* sets the USART in Smartcard mode (SCEN bit).
* Clock Output is also enabled (CLKEN).
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2828,7 +2846,7 @@
* - SCEN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the UART/USART in IRDA mode (IREN bit).
- * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
@@ -2966,7 +2984,7 @@
/**
* @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
* @param USARTx USART Instance
@@ -2993,7 +3011,7 @@
/**
* @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
* @param USARTx USART Instance
@@ -3006,7 +3024,7 @@
/**
* @brief Check if the USART LIN Break Detection Flag is set or not
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
* @param USARTx USART Instance
@@ -3019,7 +3037,7 @@
/**
* @brief Check if the USART CTS interrupt Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
* @param USARTx USART Instance
@@ -3032,7 +3050,7 @@
/**
* @brief Check if the USART CTS Flag is set or not
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
* @param USARTx USART Instance
@@ -3056,7 +3074,7 @@
/**
* @brief Check if the USART End Of Block Flag is set or not
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
* @param USARTx USART Instance
@@ -3069,7 +3087,7 @@
/**
* @brief Check if the SPI Slave Underrun error flag is set or not
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR
* @param USARTx USART Instance
@@ -3082,7 +3100,7 @@
/**
* @brief Check if the USART Auto-Baud Rate Error Flag is set or not
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
* @param USARTx USART Instance
@@ -3095,7 +3113,7 @@
/**
* @brief Check if the USART Auto-Baud Rate Flag is set or not
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
* @param USARTx USART Instance
@@ -3152,7 +3170,7 @@
/**
* @brief Check if the USART Wake Up from stop mode Flag is set or not
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
* @param USARTx USART Instance
@@ -3187,7 +3205,7 @@
/**
* @brief Check if the USART TX FIFO Empty Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE
* @param USARTx USART Instance
@@ -3200,7 +3218,7 @@
/**
* @brief Check if the USART RX FIFO Full Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF
* @param USARTx USART Instance
@@ -3224,7 +3242,7 @@
/**
* @brief Check if the USART TX FIFO Threshold Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT
* @param USARTx USART Instance
@@ -3237,7 +3255,7 @@
/**
* @brief Check if the USART RX FIFO Threshold Flag is set or not
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT
* @param USARTx USART Instance
@@ -3305,7 +3323,7 @@
/**
* @brief Clear TX FIFO Empty Flag
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE
* @param USARTx USART Instance
@@ -3340,7 +3358,7 @@
/**
* @brief Clear LIN Break Detection Flag
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
* @param USARTx USART Instance
@@ -3353,7 +3371,7 @@
/**
* @brief Clear CTS Interrupt Flag
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
* @param USARTx USART Instance
@@ -3377,7 +3395,7 @@
/**
* @brief Clear End Of Block Flag
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
* @param USARTx USART Instance
@@ -3390,7 +3408,7 @@
/**
* @brief Clear SPI Slave Underrun Flag
- * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR
* @param USARTx USART Instance
@@ -3414,7 +3432,7 @@
/**
* @brief Clear Wake Up from stop mode Flag
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
* @param USARTx USART Instance
@@ -3449,7 +3467,7 @@
/**
* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
* @param USARTx USART Instance
@@ -3476,7 +3494,7 @@
/**
* @brief Enable TX Empty and TX FIFO Not Full Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
* @param USARTx USART Instance
@@ -3522,7 +3540,7 @@
/**
* @brief Enable End Of Block Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
* @param USARTx USART Instance
@@ -3535,7 +3553,7 @@
/**
* @brief Enable TX FIFO Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE
* @param USARTx USART Instance
@@ -3559,7 +3577,7 @@
/**
* @brief Enable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
* @param USARTx USART Instance
@@ -3587,7 +3605,7 @@
/**
* @brief Enable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
* @param USARTx USART Instance
@@ -3600,7 +3618,7 @@
/**
* @brief Enable Wake Up from Stop Mode Interrupt
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
* @param USARTx USART Instance
@@ -3613,7 +3631,7 @@
/**
* @brief Enable TX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT
* @param USARTx USART Instance
@@ -3626,7 +3644,7 @@
/**
* @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
* @param USARTx USART Instance
@@ -3639,7 +3657,7 @@
/**
* @brief Enable RX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT
* @param USARTx USART Instance
@@ -3666,7 +3684,7 @@
/**
* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
* @param USARTx USART Instance
@@ -3693,7 +3711,7 @@
/**
* @brief Disable TX Empty and TX FIFO Not Full Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
* @param USARTx USART Instance
@@ -3739,7 +3757,7 @@
/**
* @brief Disable End Of Block Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
* @param USARTx USART Instance
@@ -3752,7 +3770,7 @@
/**
* @brief Disable TX FIFO Empty Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE
* @param USARTx USART Instance
@@ -3765,7 +3783,7 @@
/**
* @brief Disable RX FIFO Full Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF
* @param USARTx USART Instance
@@ -3778,7 +3796,7 @@
/**
* @brief Disable LIN Break Detection Interrupt
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
* @param USARTx USART Instance
@@ -3806,7 +3824,7 @@
/**
* @brief Disable CTS Interrupt
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
* @param USARTx USART Instance
@@ -3819,7 +3837,7 @@
/**
* @brief Disable Wake Up from Stop Mode Interrupt
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
* @param USARTx USART Instance
@@ -3832,7 +3850,7 @@
/**
* @brief Disable TX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT
* @param USARTx USART Instance
@@ -3845,7 +3863,7 @@
/**
* @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
* @param USARTx USART Instance
@@ -3858,7 +3876,7 @@
/**
* @brief Disable RX FIFO Threshold Interrupt
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT
* @param USARTx USART Instance
@@ -3885,7 +3903,7 @@
/**
* @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
* @param USARTx USART Instance
@@ -3912,7 +3930,7 @@
/**
* @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
* @param USARTx USART Instance
@@ -3958,7 +3976,7 @@
/**
* @brief Check if the USART End Of Block Interrupt is enabled or disabled.
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
* @param USARTx USART Instance
@@ -3971,7 +3989,7 @@
/**
* @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
* @param USARTx USART Instance
@@ -3984,7 +4002,7 @@
/**
* @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
* @param USARTx USART Instance
@@ -3997,7 +4015,7 @@
/**
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
* @param USARTx USART Instance
@@ -4021,7 +4039,7 @@
/**
* @brief Check if the USART CTS Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
* @param USARTx USART Instance
@@ -4034,7 +4052,7 @@
/**
* @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
- * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
* @param USARTx USART Instance
@@ -4047,7 +4065,7 @@
/**
* @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
* @param USARTx USART Instance
@@ -4060,7 +4078,7 @@
/**
* @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
- * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
* @param USARTx USART Instance
@@ -4073,7 +4091,7 @@
/**
* @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
* @param USARTx USART Instance
@@ -4203,7 +4221,7 @@
*/
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{
- register uint32_t data_reg_addr;
+ uint32_t data_reg_addr;
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
@@ -4283,7 +4301,7 @@
/**
* @brief Request an Automatic Baud Rate measurement on next received data frame
- * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
* @param USARTx USART Instance
@@ -4318,7 +4336,7 @@
/**
* @brief Request a Receive Data and FIFO flush
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @note Allows to discard the received data without reading them, and avoid an overrun
* condition.
@@ -4333,7 +4351,7 @@
/**
* @brief Request a Transmit data and FIFO flush
- * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+ * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
* @param USARTx USART Instance
diff --git a/Inc/stm32l5xx_ll_usb.h b/Inc/stm32l5xx_ll_usb.h
index c89e991..208ec14 100644
--- a/Inc/stm32l5xx_ll_usb.h
+++ b/Inc/stm32l5xx_ll_usb.h
@@ -118,6 +118,10 @@
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+ uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
+
+ uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
+
} USB_EPTypeDef;
@@ -131,10 +135,10 @@
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
-#define DEP0CTL_MPS_64 0U
-#define DEP0CTL_MPS_32 1U
-#define DEP0CTL_MPS_16 2U
-#define DEP0CTL_MPS_8 3U
+#define EP_MPS_64 0U
+#define EP_MPS_32 1U
+#define EP_MPS_16 2U
+#define EP_MPS_8 3U
/**
* @}
*/
@@ -159,10 +163,10 @@
* @}
*/
-#define BTABLE_ADDRESS 0x000U
+#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 1U
-#define EP_ADDR_MSK 0x7U
+#define EP_ADDR_MSK 0x7U
/**
* @}
*/
diff --git a/License.md b/License.md
index 37e1863..c19f468 100644
--- a/License.md
+++ b/License.md
@@ -1,3 +1,3 @@
# Copyright (c) 2019 STMicroelectronics
-This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
+This software component is licensed by STMicroelectronics under the **BSD-3-Clause** license. You may not use this software except in compliance with this license. You may obtain a copy of the license [here](https://opensource.org/licenses/BSD-3-Clause).
\ No newline at end of file
diff --git a/README.md b/README.md
index 93dbe12..f74c7c8 100644
--- a/README.md
+++ b/README.md
@@ -26,6 +26,10 @@
This software component is licensed by STMicroelectronics under BSD-3-Clause license. You may not use this software except in compliance with the License.
You may obtain a copy of the License [here](https://opensource.org/licenses/BSD-3-Clause).
+## Release note
+
+Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32l5xx_hal_driver/blob/master/Release_Notes.html).
+
## Compatibility information
In this table, you can find the successive versions of this HAL-LL Driver component, in line with the corresponding versions of the full MCU package:
@@ -36,6 +40,7 @@
------------- | --------------- | ---------- | -------------------------------------
Tag v1.0.0 | Tag v1.0.0 | Tag v5.4.0_cm33 | Tag v1.1.0 (and following, if any, till next tag)
Tag v1.0.2 | Tag v1.0.2 | Tag v5.4.0_cm33 | Tag v1.2.0 (and following, if any, till next tag)
+Tag v1.0.3 | Tag v1.0.3 | Tag v5.6.0_cm33 | Tag v1.3.0 (and following, if any, till next tag)
The full **STM32CubeL5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL5).
@@ -43,4 +48,4 @@
If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32l5xx_hal_driver/issues/new/choose).
-For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
+For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus).
\ No newline at end of file
diff --git a/Release_Notes.html b/Release_Notes.html
index cce207a..0feee71 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -46,15 +46,142 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.0.2 / 12-February-2020</strong></label>
+<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.0.3 / 26-June-2020</strong></label>
<div>
<h2 id="main-changes">Main Changes</h2>
-<p><strong>Third release</strong></p>
+<p><strong>Fourth release</strong></p>
<h2 id="contents">Contents</h2>
-<p>Third official release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
+<p>Fourth release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
<p>Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)</p>
<h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
<ul>
+<li>Global removal of ‘register’ storage class qualifier deprecated since C++ 11</li>
+<li><strong>HAL</strong> generic driver
+<ul>
+<li>Remove non-applicable HAL_DBGMCU_EnableDBGSleepMode() and HAL_DBGMCU_DisableDBGSleepMode() APIs</li>
+</ul></li>
+<li><strong>HAL CRYP</strong> driver
+<ul>
+<li>AES GSM: Support data encrypt/decrypt with length not multiple of 16 bytes</li>
+<li>AES GSM: Handling of AAD with size not multiple of 4 bytes in HAL_CRYPEx_AESGCM_GenerateAuthTAG()</li>
+</ul></li>
+<li><strong>HAL DAC</strong> driver
+<ul>
+<li>Fix timeout management for sample & hold channel 2</li>
+</ul></li>
+<li><strong>HAL FLASH</strong> driver
+<ul>
+<li>Add FLASH_NB_PAGE definition in stm32l5xx_hal_flash.h</li>
+</ul></li>
+<li><strong>HAL GPIO</strong> driver
+<ul>
+<li>Fix HAL_GPIO_TogglePin() to manage several pins</li>
+</ul></li>
+<li><strong>HAL HASH</strong> driver
+<ul>
+<li>Add comments to describe case of message made of several parts, not all with length multiple of 4 bytes.</li>
+</ul></li>
+<li><strong>HAL ICACHE</strong> driver
+<ul>
+<li>HAL_ICACHE_Enable() updated to enable the instruction cache whatever any ongoing operation.</li>
+<li>HAL_ICACHE_Disable() updated to not wait for end of invalidation procedure.</li>
+<li>Add HAL_ICACHE_WaitForInvalidateComplete() API</li>
+</ul></li>
+<li><strong>HAL IWDG</strong> driver
+<ul>
+<li>HAL_IWDG_DEFAULT_TIMEOUT updated based on LSI_VALUE</li>
+</ul></li>
+<li><strong>HAL MMC</strong> driver
+<ul>
+<li>Add MMC_LOW_VOLTAGE_RANGE and eMMC_LOW_VOLTAGE_RANGE modes</li>
+<li>Add HAL_MMC_GetCardExtCSD() API</li>
+<li>Fix in HAL_MMC_ConfigWideBusOperation() to manage power class before bus width speed</li>
+</ul></li>
+<li><strong>HAL NOR</strong> driver
+<ul>
+<li>Apply adequate commands according to the command set field value (command set 1 for Micron JS28F512P33, command set 2 for Micron M29W128G and Cypress S29GL128P)</li>
+</ul></li>
+<li><strong>HAL PCD</strong> driver
+<ul>
+<li>Fix double buffer bulk out transaction</li>
+</ul></li>
+<li><strong>HAL RNG</strong> driver
+<ul>
+<li>Apply in HAL_RNG_Init() the recommended value after NIST SP 800-90B entropy validation</li>
+<li>New API HAL_RNGEx_RecoverSeedError()</li>
+<li>Add check on seed error with internal seed recovery procedure in HAL_RNG_GenerateRandomNumber()</li>
+</ul></li>
+<li><strong>HAL RCC</strong> driver
+<ul>
+<li>Fix __HAL_RCC_APB1_FORCE_RESET() and __HAL_RCC_APB1_RELEASE_RESET() macros to manage both APB1RSTR1 and APB1RSTR2 registers</li>
+</ul></li>
+<li><strong>HAL SMARTCARD</strong> driver
+<ul>
+<li>Fix NACK management</li>
+</ul></li>
+<li><strong>HAL SPI</strong> driver
+<ul>
+<li>Fix in 3-wires communication (disable and enable SPI)</li>
+<li>Fix timeout management inside SPI DMA xfer complete handler</li>
+<li>Fix to not assert on BaudRatePrescaler in Slave Motorola mode</li>
+</ul></li>
+<li><strong>HAL TIM</strong> driver
+<ul>
+<li>Fix DMA management when DMA requests are used for several channels of the same timer</li>
+<li>Fix HAL_TIM_IC_Stop_DMA() to stop DMA prior to disabling the channel</li>
+</ul></li>
+<li><strong>HAL UART</strong> driver
+<ul>
+<li>Add new reception services APIs, allowing user to handle reception of unknown/variable lengths and to get notified about received data upon events at reception buffer filling or IDLE event on Rx line:
+<ul>
+<li>HAL_UARTEx_ReceiveToIdle(): allow user to receive data until a given number of data are received or until IDLE event occurs on Rx Line. In case of IDLE event detected during reception, function returns HAL_OK and provides number of received data (available data stored in reception buffer)</li>
+<li>HAL_UARTEx_ReceiveToIdle_IT(): allow user to receive data in interrupt mode until a given number of data are received or until IDLE event occurs on Rx Line. When any of these 2 events occurs, a user callback HAL_UARTEx_RxEventCallback() is executed and reception is stopped. Callback provides number of received data (available data stored in reception buffer)</li>
+<li>HAL_UARTEx_ReceiveToIdle_DMA(): allow user to receive data in DMA mode until DMA buffer filling Half Transfer and Transfer Complete events occur or until IDLE event occurs on Rx Line. When any of these 3 events occurs, a user callback HAL_UARTEx_RxEventCallback() is executed and provides number of received data (available data stored in reception buffer). In DMA Normal mode, reception ends after either DMA Transfer Complete or IDLE event occurs. In DMA Circular mode, reception goes on after all occurrences of HAL_UARTEx_RxEventCallback() calls.</li>
+<li>User version of HAL_UARTEx_RxEventCallback() is to be implemented in user code (weak empty function defined in HAL code).</li>
+</ul></li>
+<li>Rework BRR register value computation in HAL_UART_Init() for ROM size gain</li>
+</ul></li>
+</ul>
+<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<ul>
+<li>Global removal of ‘register’ storage class qualifier deprecated since C++ 11</li>
+<li><strong>LL GPIO</strong> driver
+<ul>
+<li>Fix LL_GPIO_TogglePin() to manage several pins</li>
+</ul></li>
+<li><strong>LL PWR</strong> driver
+<ul>
+<li>Fix LL_PWR_IsEnabledUCPDDeadBattery() returned value</li>
+</ul></li>
+<li><strong>LL SYSTEM</strong> driver
+<ul>
+<li>Add LL_DBGMCU_EnableTraceClock(), LL_DBGMCU_DisableTraceClock() and LL_DBGMCU_IsEnabledTraceClock() APIs</li>
+<li>Remove non-applicable LL_DBGMCU_EnableDBGSleepMode() and LL_DBGMCU_DisableDBGSleepMode() APIs</li>
+</ul></li>
+<li><strong>LL TIM</strong> driver
+<ul>
+<li>Fix inverted LL_TIM_COUNTERMODE_CENTER_UP and LL_TIM_COUNTERMODE_CENTER_DOWN definitions</li>
+</ul></li>
+<li><strong>LL UCPD</strong> driver
+<ul>
+<li>Change default CFGR1 register values in LL_UCPD_StructInit()</li>
+</ul></li>
+</ul>
+<h2 id="notes">Notes</h2>
+<p>For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.</p>
+<p>For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.0.2 / 12-February-2020</strong></label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<p><strong>Third release</strong></p>
+<h2 id="contents-1">Contents</h2>
+<p>Third official release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
+<p>Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)</p>
+<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<ul>
<li><strong>HAL FLASH</strong> driver
<ul>
<li>Fix non-secure Flash access from secure Flash service to not update SAU status</li>
@@ -76,7 +203,7 @@
<li>Fix HAL_SPI_Receive_DMA() and HAL_SPI_TransmitReceive_DMA() to only disable TX DMA interrupt at end of DMA reception in Master RX 2 lines mode</li>
</ul></li>
</ul>
-<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL UTILS</strong> driver
<ul>
@@ -86,7 +213,7 @@
</ul></li>
</ul></li>
</ul>
-<h2 id="notes">Notes</h2>
+<h2 id="notes-1">Notes</h2>
<p>For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.</p>
<p>For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.</p>
<h2 id="known-limitations">Known Limitations</h2>
@@ -99,14 +226,14 @@
</div>
</div>
<div class="collapse">
-<input type="checkbox" id="collapse-section2" unchecked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 22-January-2020</strong></label>
+<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.0.1 / 22-January-2020</strong></label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<p><strong>Second release</strong></p>
-<h2 id="contents-1">Contents</h2>
+<h2 id="contents-2">Contents</h2>
<p>Second official release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
<p>Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)</p>
-<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL FLASH</strong> driver
<ul>
@@ -126,8 +253,7 @@
<ul>
<li>Fix sequential transfer of MAX_NBYTE_SIZE in:
<ul>
-<li>HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Receive_IT() and HAL_I2C_Master_Seq_Receive_DMA(),<br />
-</li>
+<li>HAL_I2C_Master_Seq_Transmit_IT(), HAL_I2C_Master_Seq_Transmit_DMA(), HAL_I2C_Master_Seq_Receive_IT() and HAL_I2C_Master_Seq_Receive_DMA(),</li>
</ul></li>
</ul></li>
<li><strong>HAL SMBUS</strong> driver
@@ -151,7 +277,7 @@
<li>Add receiver timeout interrupt management with new HAL_USART_ERROR_RTO error code in HAL_USART_IRQHandler()</li>
</ul></li>
</ul>
-<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL GPIO</strong> driver
<ul>
@@ -166,17 +292,17 @@
<li>Add LL_SetFlashLatency() API</li>
</ul></li>
</ul>
-<h2 id="notes-1">Notes</h2>
+<h2 id="notes-2">Notes</h2>
<p>For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.</p>
<p>For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.</p>
</div>
</div>
<div class="collapse">
-<input type="checkbox" id="collapse-section1" unchecked aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 13-December-2019</strong></label>
+<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 13-December-2019</strong></label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<p><strong>First release</strong></p>
-<h2 id="contents-2">Contents</h2>
+<h2 id="contents-3">Contents</h2>
<p>First official release of <strong>HAL and Low Layer drivers</strong> for <strong>STM32L552xx/STM32L562xx</strong> devices</p>
<p>Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)</p>
<h3 id="hal-drivers">HAL Drivers</h3>
@@ -188,7 +314,7 @@
<ul>
<li>ADC, BUS, COMP, CORTEX, CRC, CRS, CRYP, DAC, DMA, DMAMUX, EXTI, GPIO, I2C, IWDG, LPTIM, LPUART, OPAMP, PKA, PWR, RCC, RNG, RTC, SDMMC, SPI, SYSTEM, TIM, UCPD, USART, UTILS, WWDG</li>
</ul>
-<h2 id="notes-2">Notes</h2>
+<h2 id="notes-3">Notes</h2>
<p>For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.</p>
<p>For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.</p>
</div>
diff --git a/Src/stm32l5xx_hal.c b/Src/stm32l5xx_hal.c
index 5f65e01..605fdaf 100644
--- a/Src/stm32l5xx_hal.c
+++ b/Src/stm32l5xx_hal.c
@@ -53,7 +53,7 @@
*/
#define STM32L5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define STM32L5XX_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
-#define STM32L5XX_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
+#define STM32L5XX_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define STM32L5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define STM32L5XX_HAL_VERSION ((STM32L5XX_HAL_VERSION_MAIN << 24U)\
|(STM32L5XX_HAL_VERSION_SUB1 << 16U)\
@@ -77,7 +77,7 @@
*/
__IO uint32_t uwTick;
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */
-uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
@@ -145,7 +145,7 @@
/* Insure time base clock coherency */
SystemCoreClockUpdate();
-
+
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
@@ -162,7 +162,7 @@
}
/**
- * @brief De-initialize common part of the HAL and stop the source of time base.
+ * @brief DeInitialize common part of the HAL and stop the source of time base.
* @note This function is optional.
* @retval HAL status
*/
@@ -233,10 +233,11 @@
{
HAL_StatusTypeDef status = HAL_OK;
- if (uwTickFreq != 0U)
+ /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
+ if ((uint32_t)uwTickFreq != 0U)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
@@ -298,7 +299,7 @@
*/
__weak void HAL_IncTick(void)
{
- uwTick += uwTickFreq;
+ uwTick += (uint32_t)uwTickFreq;
}
/**
@@ -326,18 +327,25 @@
* @param Freq tick frequency
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
- assert_param(IS_TICKFREQ(Freq));
+ HAL_TickFreqTypeDef prevTickFreq;
if (uwTickFreq != Freq)
{
+ /* Back up uwTickFreq frequency */
+ prevTickFreq = uwTickFreq;
+
+ /* Update uwTickFreq global variable used by HAL_InitTick() */
+ uwTickFreq = Freq;
+
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
- if (status == HAL_OK)
+ if (status != HAL_OK)
{
- uwTickFreq = Freq;
+ /* Restore previous tick frequency */
+ uwTickFreq = prevTickFreq;
}
}
@@ -348,7 +356,7 @@
* @brief Return tick frequency.
* @retval tick period in Hz
*/
-uint32_t HAL_GetTickFreq(void)
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
@@ -372,10 +380,10 @@
/* Add a period to guaranty minimum wait */
if (wait < HAL_MAX_DELAY)
{
- wait += (uint32_t)(uwTickFreq);
+ wait += (uint32_t)uwTickFreq;
}
- while((HAL_GetTick() - tickstart) < wait)
+ while ((HAL_GetTick() - tickstart) < wait)
{
}
}
@@ -418,7 +426,7 @@
*/
uint32_t HAL_GetHalVersion(void)
{
- return STM32L5XX_HAL_VERSION;
+ return STM32L5XX_HAL_VERSION;
}
/**
@@ -427,7 +435,7 @@
*/
uint32_t HAL_GetREVID(void)
{
- return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+ return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
}
/**
@@ -436,7 +444,7 @@
*/
uint32_t HAL_GetDEVID(void)
{
- return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
+ return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
}
/**
@@ -445,7 +453,7 @@
*/
uint32_t HAL_GetUIDw0(void)
{
- return(READ_REG(*((uint32_t *)UID_BASE)));
+ return(READ_REG(*((uint32_t *)UID_BASE)));
}
/**
@@ -454,7 +462,7 @@
*/
uint32_t HAL_GetUIDw1(void)
{
- return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+ return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
@@ -478,7 +486,6 @@
##### HAL Debug functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
(+) Enable/Disable Debug module during STANDBY mode
@@ -487,24 +494,6 @@
*/
/**
- * @brief Enable the Debug Module during SLEEP mode.
- * @retval None
- */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
- SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
- * @brief Disable the Debug Module during SLEEP mode.
- * @retval None
- */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
- CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
* @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes.
* @retval None
*/
diff --git a/Src/stm32l5xx_hal_adc.c b/Src/stm32l5xx_hal_adc.c
index 2192b42..4519941 100644
--- a/Src/stm32l5xx_hal_adc.c
+++ b/Src/stm32l5xx_hal_adc.c
@@ -3,7 +3,7 @@
* @file stm32l5xx_hal_adc.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Initialization and de-initialization functions
* ++ Initialization and Configuration of ADC
@@ -323,8 +323,7 @@
#define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\
ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
- ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
- when no regular conversion is on-going */
+ ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
/* Timeout values for ADC operations (enable settling time, */
/* disable settling time, ...). */
@@ -877,10 +876,10 @@
hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
}
- /* DeInit the low level hardware: RCC clock, NVIC */
+ /* DeInit the low level hardware */
hadc->MspDeInitCallback(hadc);
#else
- /* DeInit the low level hardware: RCC clock, NVIC */
+ /* DeInit the low level hardware */
HAL_ADC_MspDeInit(hadc);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
@@ -957,7 +956,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+ pADC_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -2142,7 +2142,7 @@
/* Disable ADC peripheral if conversions are effectively stopped */
if (tmp_hal_status == HAL_OK)
{
- /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
+ /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
/* Disable the DMA channel (in case of DMA in circular mode or stop */
@@ -2345,7 +2345,7 @@
/* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
/* to determine if conversion has been triggered from EOC or EOS, */
/* possibility to use: */
- /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
+ /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
@@ -2445,8 +2445,8 @@
/* Injected Conversion complete callback */
/* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
- if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+ if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
interruption has been triggered by end of conversion or end of
sequence. */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
@@ -2701,7 +2701,7 @@
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
- __IO uint32_t wait_loop_index = 0;
+ __IO uint32_t wait_loop_index = 0UL;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
@@ -2785,19 +2785,23 @@
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
@@ -2829,7 +2833,7 @@
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
- if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
{
/* Configuration of common ADC parameters */
@@ -2841,7 +2845,8 @@
{
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
- if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
{
@@ -2920,7 +2925,7 @@
* The setting of these parameters is conditioned to ADC state.
* For parameters constraints, see comments of structure
* "ADC_AnalogWDGConfTypeDef".
- * @note On this STM32 serie, analog watchdog thresholds cannot be modified
+ * @note On this STM32 series, analog watchdog thresholds cannot be modified
* while ADC conversion is on going.
* @param hadc ADC handle
* @param AnalogWDGConfig Structure of ADC analog watchdog configuration
@@ -3024,7 +3029,8 @@
tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
- LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
+ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
+ tmpAWDLowThresholdShifted);
/* Update state, clear previous result related to AWD1 */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
@@ -3082,7 +3088,8 @@
tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
/* Set ADC analog watchdog thresholds value of both thresholds high and low */
- LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted);
+ LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
+ tmpAWDLowThresholdShifted);
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
{
@@ -3343,8 +3350,6 @@
return HAL_OK;
}
-
-
/**
* @brief Enable the selected ADC.
* @note Prerequisite condition to use this function: ADC must be disabled
@@ -3363,7 +3368,8 @@
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Check if conditions to enable the ADC are fulfilled */
- if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+ if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+ | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
diff --git a/Src/stm32l5xx_hal_adc_ex.c b/Src/stm32l5xx_hal_adc_ex.c
index 4c9773b..f0aefc1 100644
--- a/Src/stm32l5xx_hal_adc_ex.c
+++ b/Src/stm32l5xx_hal_adc_ex.c
@@ -3,7 +3,7 @@
* @file stm32l5xx_hal_adc_ex.c
* @author MCD Application Team
* @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC)
+ * functionalities of the Analog to Digital Converter (ADC)
* peripheral:
* + Operation functions
* ++ Start, stop, get result of conversions of ADC group injected,
@@ -62,8 +62,7 @@
#define ADC_JSQR_FIELDS ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
ADC_JSQR_JSQ1 | ADC_JSQR_JSQ2 |\
- ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime
- once the ADC is enabled */
+ ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 )) /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */
/* Fixed timeout value for ADC calibration. */
/* Values defined to be higher than worst cases: maximum ratio between ADC */
@@ -220,7 +219,8 @@
* @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
* @retval HAL state
*/
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+ uint32_t CalibrationFactor)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_adc_is_conversion_on_going_regular;
@@ -1944,19 +1944,23 @@
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
}
- if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+ == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
}
@@ -1978,7 +1982,9 @@
if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
{
/* Set sampling time of the selected ADC channel */
- LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
+ LL_ADC_SetChannelSamplingTime(hadc->Instance,
+ (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel)
+ + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
}
/* Management of internal measurement channels: Vbat/VrefInt/TempSensor */
@@ -1987,7 +1993,7 @@
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
- if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
+ if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
{
/* Configuration of common ADC parameters (continuation) */
/* Software is allowed to change common parameters only when all ADCs */
diff --git a/Src/stm32l5xx_hal_comp.c b/Src/stm32l5xx_hal_comp.c
index 3d6f884..e3f3efa 100644
--- a/Src/stm32l5xx_hal_comp.c
+++ b/Src/stm32l5xx_hal_comp.c
@@ -91,11 +91,11 @@
The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_COMP_RegisterCallback()
+ Use Functions HAL_COMP_RegisterCallback()
to register an interrupt callback.
[..]
- Function @ref HAL_COMP_RegisterCallback() allows to register following callbacks:
+ Function HAL_COMP_RegisterCallback() allows to register following callbacks:
(+) TriggerCallback : callback for COMP trigger.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
@@ -103,11 +103,11 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_COMP_UnRegisterCallback to reset a callback to the default
+ Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
weak function.
[..]
- @ref HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TriggerCallback : callback for COMP trigger.
@@ -115,27 +115,27 @@
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
- By default, after the @ref HAL_COMP_Init() and when the state is @ref HAL_COMP_STATE_RESET
+ By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
all callbacks are set to the corresponding weak functions:
- example @ref HAL_COMP_TriggerCallback().
+ example HAL_COMP_TriggerCallback().
Exception done for MspInit and MspDeInit functions that are
- reset to the legacy weak functions in the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit() only when
+ reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
these callbacks are null (not registered beforehand).
[..]
- If MspInit or MspDeInit are not null, the @ref HAL_COMP_Init()/ @ref HAL_COMP_DeInit()
+ If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
- Callbacks can be registered/unregistered in @ref HAL_COMP_STATE_READY state only.
+ Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
- in @ref HAL_COMP_STATE_READY or @ref HAL_COMP_STATE_RESET state,
+ in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
[..]
Then, the user first registers the MspInit/MspDeInit user callbacks
- using @ref HAL_COMP_RegisterCallback() before calling @ref HAL_COMP_DeInit()
- or @ref HAL_COMP_Init() function.
+ using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
+ or HAL_COMP_Init() function.
[..]
When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
diff --git a/Src/stm32l5xx_hal_cortex.c b/Src/stm32l5xx_hal_cortex.c
index 7211b4e..9fc53eb 100644
--- a/Src/stm32l5xx_hal_cortex.c
+++ b/Src/stm32l5xx_hal_cortex.c
@@ -18,7 +18,7 @@
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
- The Cortex-M4 exceptions are managed by CMSIS functions.
+ The Cortex-M33 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
diff --git a/Src/stm32l5xx_hal_crc_ex.c b/Src/stm32l5xx_hal_crc_ex.c
index 699f182..d0502ee 100644
--- a/Src/stm32l5xx_hal_crc_ex.c
+++ b/Src/stm32l5xx_hal_crc_ex.c
@@ -11,7 +11,7 @@
##### How to use this driver #####
================================================================================
[..]
- (+) Set user-defined generating polynomial thru HAL_CRCEx_Polynomial_Set()
+ (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set()
(+) Configure Input or Output data inversion
@endverbatim
diff --git a/Src/stm32l5xx_hal_cryp.c b/Src/stm32l5xx_hal_cryp.c
index c463855..a41da89 100644
--- a/Src/stm32l5xx_hal_cryp.c
+++ b/Src/stm32l5xx_hal_cryp.c
@@ -2743,7 +2743,8 @@
static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
@@ -2780,19 +2781,17 @@
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i= 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
}
/**
@@ -2805,24 +2804,23 @@
*/
static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
{
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
+ uint32_t i;
if (hcryp->State == HAL_CRYP_STATE_BUSY)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i= 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
if (hcryp->CrypOutCount == (hcryp->Size / 4U))
{
/* Disable Computation Complete flag and errors interrupts */
@@ -2959,7 +2957,7 @@
uint32_t tickstart;
uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ;
uint32_t npblb;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t index;
uint32_t lastwordsize;
uint32_t incount; /* Temporary CrypInCount Value */
@@ -3138,9 +3136,11 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
hcryp->CrypOutCount++;
}
}
@@ -3487,7 +3487,7 @@
uint32_t index;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -3667,9 +3667,11 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
@@ -3700,7 +3702,7 @@
uint32_t loopcounter;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4] ; /* Temporary CrypOutBuff */
uint32_t incount; /* Temporary CrypInCount Value */
uint32_t outcount; /* Temporary CrypOutCount Value */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
@@ -3872,9 +3874,11 @@
for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[loopcounter] = hcryp->Instance->DOUTR;
+ }
+ for (loopcounter = 0U; loopcounter<lastwordsize; loopcounter++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[loopcounter];
hcryp->CrypOutCount++;
}
}
@@ -4197,7 +4201,7 @@
uint32_t index;
uint32_t npblb;
uint32_t lastwordsize;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
@@ -4376,9 +4380,11 @@
for (index = 0U; index < 4U; index++)
{
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
- temp = hcryp->Instance->DOUTR;
-
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+ temp[index] = hcryp->Instance->DOUTR;
+ }
+ for (index = 0U; index < lastwordsize; index++)
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
hcryp->CrypOutCount++;
}
@@ -4402,29 +4408,28 @@
static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
{
uint32_t loopcounter;
- uint32_t temp; /* Temporary CrypOutBuff */
+ uint32_t temp[4]; /* Temporary CrypOutBuff */
uint32_t lastwordsize;
uint32_t npblb;
uint32_t mode;
uint16_t incount; /* Temporary CrypInCount Value */
uint16_t outcount; /* Temporary CrypOutCount Value */
+ uint32_t i;
/***************************** Payload phase *******************************/
/* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
- hcryp->CrypOutCount++;
- temp = hcryp->Instance->DOUTR;
- *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
- hcryp->CrypOutCount++;
-
+ for (i = 0U; i < 4U; i++)
+ {
+ temp[i] = hcryp->Instance->DOUTR;
+ }
+ i= 0U;
+ while((hcryp->CrypOutCount < ((hcryp->Size + 3U)/4U)) && (i<4U))
+ {
+ *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+ hcryp->CrypOutCount++;
+ i++;
+ }
incount = hcryp->CrypInCount;
outcount = hcryp->CrypOutCount;
if ((outcount >= (hcryp->Size / 4U)) && ((incount * 4U) >= hcryp->Size))
@@ -4550,10 +4555,21 @@
static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
{
uint32_t loopcounter;
+ uint32_t size_in_bytes;
+ uint32_t tmp;
+ uint32_t mask[4] = {0x0U, 0x0FFU, 0x0FFFFU, 0x0FFFFFFU};
/***************************** Header phase for GCM/GMAC or CCM *********************************/
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
+ {
+ size_in_bytes = hcryp->Init.HeaderSize * 4U;
+ }
+ else
+ {
+ size_in_bytes = hcryp->Init.HeaderSize;
+ }
- if ((hcryp->Init.HeaderSize != 0U))
+ if ((size_in_bytes != 0U))
{
/* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
@@ -4561,10 +4577,11 @@
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
- if ((hcryp->Init.HeaderSize % 4U) == 0U)
+ /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
+ if ((size_in_bytes % 16U) == 0U)
{
- /* HeaderSize %4, no padding */
- for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
+ /* No padding */
+ for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
{
/* Write the input block in the data input register */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -4595,8 +4612,8 @@
}
else
{
- /*Write header block in the IN FIFO without last block */
- for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
+ /* Write header block in the IN FIFO without last block */
+ for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
{
/* Write the input block in the data input register */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
@@ -4624,17 +4641,35 @@
/* Clear CCF flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
}
- /* Last block optionally pad the data with zeros*/
- for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
+ /* Write last complete words */
+ for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
hcryp->CrypHeaderCount++ ;
}
- while (loopcounter < 4U)
+ /* If the header size is a multiple of words */
+ if ((size_in_bytes % 4U) == 0U)
{
- /*Pad the data with zeros to have a complete block */
- hcryp->Instance->DINR = 0x0U;
- loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
+ }
+ else
+ {
+ /* Enter last bytes, padded with zeroes */
+ tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
+ tmp &= mask[size_in_bytes % 4U];
+ hcryp->Instance->DINR = tmp;
+ loopcounter++;
+ /* Pad the data with zeros to have a complete block */
+ while (loopcounter < 4U)
+ {
+ hcryp->Instance->DINR = 0x0U;
+ loopcounter++;
+ }
}
if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
diff --git a/Src/stm32l5xx_hal_cryp_ex.c b/Src/stm32l5xx_hal_cryp_ex.c
index dbeafcc..30d96b9 100644
--- a/Src/stm32l5xx_hal_cryp_ex.c
+++ b/Src/stm32l5xx_hal_cryp_ex.c
@@ -99,10 +99,17 @@
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout)
{
uint32_t tickstart;
+ /* Assume first Init.HeaderSize is in words */
uint64_t headerlength = (uint64_t)hcryp->Init.HeaderSize * 32U; /* Header length in bits */
- uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
+ uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */
uint32_t tagaddr = (uint32_t)AuthTag;
+ /* Correct headerlength if Init.HeaderSize is actually in bytes */
+ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE)
+ {
+ headerlength /= 4U;
+ }
+
if (hcryp->State == HAL_CRYP_STATE_READY)
{
/* Process locked */
diff --git a/Src/stm32l5xx_hal_dac.c b/Src/stm32l5xx_hal_dac.c
index c3e40ae..200c86b 100644
--- a/Src/stm32l5xx_hal_dac.c
+++ b/Src/stm32l5xx_hal_dac.c
@@ -740,8 +740,6 @@
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
- HAL_StatusTypeDef status;
-
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
@@ -757,7 +755,7 @@
if (Channel == DAC_CHANNEL_1)
{
/* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle1);
+ (void)HAL_DMA_Abort(hdac->DMA_Handle1);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
@@ -765,26 +763,17 @@
else /* Channel2 is used for */
{
/* Disable the DMA channel */
- status = HAL_DMA_Abort(hdac->DMA_Handle2);
+ (void)HAL_DMA_Abort(hdac->DMA_Handle2);
/* Disable the DAC DMA underrun interrupt */
__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
}
- /* Check if DMA Channel effectively disabled */
- if (status != HAL_OK)
- {
- /* Update DAC state machine to error */
- hdac->State = HAL_DAC_STATE_ERROR;
- }
- else
- {
- /* Change DAC state */
- hdac->State = HAL_DAC_STATE_READY;
- }
+ /* Change DAC state */
+ hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -1021,7 +1010,7 @@
{
uint32_t tmpreg1;
uint32_t tmpreg2;
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
uint32_t hclkfreq;
/* Check the DAC parameters */
@@ -1049,15 +1038,14 @@
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
+ /* Sample and hold configuration */
if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
- /* Sample on old configuration */
{
- /* SampleTime */
+ /* Get timeout */
+ tickstart = HAL_GetTick();
+
if (Channel == DAC_CHANNEL_1)
{
- /* Get timeout */
- tickstart = HAL_GetTick();
-
/* SHSR1 can be written when BWST1 is cleared */
while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
{
@@ -1079,7 +1067,6 @@
else /* Channel 2 */
{
/* SHSR2 can be written when BWST2 is cleared */
-
while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
{
/* Check for the Timeout */
@@ -1099,9 +1086,11 @@
}
/* HoldTime */
- MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
/* RefreshTime */
- MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
+ MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
+ (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
}
if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
@@ -1359,7 +1348,7 @@
* @param hdac DAC handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
- * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID
+ * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
diff --git a/Src/stm32l5xx_hal_dma.c b/Src/stm32l5xx_hal_dma.c
index 23b53c2..2b7993f 100644
--- a/Src/stm32l5xx_hal_dma.c
+++ b/Src/stm32l5xx_hal_dma.c
@@ -712,6 +712,9 @@
/* Clear the transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
+ /* Process unlocked */
+ __HAL_UNLOCK(hdma);
+
/* The selected Channelx EN bit is cleared (DMA is disabled and
all transfers are complete) */
hdma->State = HAL_DMA_STATE_READY;
@@ -722,9 +725,6 @@
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
}
- /* Process unlocked */
- __HAL_UNLOCK(hdma);
-
return HAL_OK;
}
@@ -876,7 +876,7 @@
* @brief Register callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param CallbackID User Callback identifer
+ * @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @param pCallback pointer to private callbacsk function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
@@ -937,7 +937,7 @@
* @brief UnRegister callbacks
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
- * @param CallbackID User Callback identifer
+ * @param CallbackID User Callback identifier
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
diff --git a/Src/stm32l5xx_hal_exti.c b/Src/stm32l5xx_hal_exti.c
index 0ade687..77902b8 100644
--- a/Src/stm32l5xx_hal_exti.c
+++ b/Src/stm32l5xx_hal_exti.c
@@ -32,7 +32,7 @@
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
- be selected throught multiplexer.
+ be selected through multiplexer.
##### How to use this driver #####
==============================================================================
diff --git a/Src/stm32l5xx_hal_fdcan.c b/Src/stm32l5xx_hal_fdcan.c
index 9bff6df..48d1eb0 100644
--- a/Src/stm32l5xx_hal_fdcan.c
+++ b/Src/stm32l5xx_hal_fdcan.c
@@ -223,13 +223,17 @@
#define SRAMCAN_TEF_SIZE ( 2U * 4U) /* TX Event FIFO Elements Size in bytes */
#define SRAMCAN_TFQ_SIZE (18U * 4U) /* TX FIFO/Queue Elements Size in bytes */
-#define SRAMCAN_FLSSA ((uint32_t)0) /* Filter List Standard Start Address */
-#define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start Address */
-#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
-#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
-#define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start Address */
-#define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start Address */
-#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */
+#define SRAMCAN_FLSSA ((uint32_t)0) /* Filter List Standard Start
+ Address */
+#define SRAMCAN_FLESA ((uint32_t)(SRAMCAN_FLSSA + (SRAMCAN_FLS_NBR * SRAMCAN_FLS_SIZE))) /* Filter List Extended Start
+ Address */
+#define SRAMCAN_RF0SA ((uint32_t)(SRAMCAN_FLESA + (SRAMCAN_FLE_NBR * SRAMCAN_FLE_SIZE))) /* Rx FIFO 0 Start Address */
+#define SRAMCAN_RF1SA ((uint32_t)(SRAMCAN_RF0SA + (SRAMCAN_RF0_NBR * SRAMCAN_RF0_SIZE))) /* Rx FIFO 1 Start Address */
+#define SRAMCAN_TEFSA ((uint32_t)(SRAMCAN_RF1SA + (SRAMCAN_RF1_NBR * SRAMCAN_RF1_SIZE))) /* Tx Event FIFO Start
+ Address */
+#define SRAMCAN_TFQSA ((uint32_t)(SRAMCAN_TEFSA + (SRAMCAN_TEF_NBR * SRAMCAN_TEF_SIZE))) /* Tx FIFO/Queue Start
+ Address */
+#define SRAMCAN_SIZE ((uint32_t)(SRAMCAN_TFQSA + (SRAMCAN_TFQ_NBR * SRAMCAN_TFQ_SIZE))) /* Message RAM size */
/**
* @}
@@ -244,7 +248,8 @@
* @{
*/
static void FDCAN_CalcultateRamBlockAddresses(FDCAN_HandleTypeDef *hfdcan);
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
+ uint32_t BufferIndex);
/**
* @}
*/
@@ -255,8 +260,8 @@
*/
/** @defgroup FDCAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
@@ -320,17 +325,22 @@
hfdcan->Lock = HAL_UNLOCKED;
/* Reset callbacks to legacy functions */
- hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
- hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
- hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
- hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
- hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak TxBufferCompleteCallback */
- hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak TxBufferAbortCallback */
- hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak HighPriorityMessageCallback */
- hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak TimestampWraparoundCallback */
- hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak TimeoutOccurredCallback */
- hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */
- hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
+ hfdcan->TxEventFifoCallback = HAL_FDCAN_TxEventFifoCallback; /* Legacy weak TxEventFifoCallback */
+ hfdcan->RxFifo0Callback = HAL_FDCAN_RxFifo0Callback; /* Legacy weak RxFifo0Callback */
+ hfdcan->RxFifo1Callback = HAL_FDCAN_RxFifo1Callback; /* Legacy weak RxFifo1Callback */
+ hfdcan->TxFifoEmptyCallback = HAL_FDCAN_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hfdcan->TxBufferCompleteCallback = HAL_FDCAN_TxBufferCompleteCallback; /* Legacy weak
+ TxBufferCompleteCallback */
+ hfdcan->TxBufferAbortCallback = HAL_FDCAN_TxBufferAbortCallback; /* Legacy weak
+ TxBufferAbortCallback */
+ hfdcan->HighPriorityMessageCallback = HAL_FDCAN_HighPriorityMessageCallback; /* Legacy weak
+ HighPriorityMessageCallback */
+ hfdcan->TimestampWraparoundCallback = HAL_FDCAN_TimestampWraparoundCallback; /* Legacy weak
+ TimestampWraparoundCallback */
+ hfdcan->TimeoutOccurredCallback = HAL_FDCAN_TimeoutOccurredCallback; /* Legacy weak
+ TimeoutOccurredCallback */
+ hfdcan->ErrorCallback = HAL_FDCAN_ErrorCallback; /* Legacy weak ErrorCallback */
+ hfdcan->ErrorStatusCallback = HAL_FDCAN_ErrorStatusCallback; /* Legacy weak ErrorStatusCallback */
if (hfdcan->MspInitCallback == NULL)
{
@@ -677,7 +687,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID,
+ void (* pCallback)(FDCAN_HandleTypeDef *_hFDCAN))
{
HAL_StatusTypeDef status = HAL_OK;
@@ -864,7 +875,8 @@
* @param pCallback pointer to the Tx Event Fifo Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxEventFifoCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -924,7 +936,8 @@
* @param pCallback pointer to the Rx Fifo 0 Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_RxFifo0CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -984,7 +997,8 @@
* @param pCallback pointer to the Rx Fifo 1 Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_RxFifo1CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -1044,7 +1058,8 @@
* @param pCallback pointer to the Tx Buffer Complete Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferCompleteCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -1073,7 +1088,8 @@
/**
* @brief UnRegister the Tx Buffer Complete FDCAN Callback
- * Tx Buffer Complete FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
+ * Tx Buffer Complete FDCAN Callback is redirected to
+ * the weak HAL_FDCAN_TxBufferCompleteCallback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
@@ -1104,7 +1120,8 @@
* @param pCallback pointer to the Tx Buffer Abort Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_TxBufferAbortCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -1133,7 +1150,8 @@
/**
* @brief UnRegister the Tx Buffer Abort FDCAN Callback
- * Tx Buffer Abort FDCAN Callback is redirected to the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
+ * Tx Buffer Abort FDCAN Callback is redirected to
+ * the weak HAL_FDCAN_TxBufferAbortCallback() predefined callback
* @param hfdcan FDCAN handle
* @retval HAL status
*/
@@ -1164,7 +1182,8 @@
* @param pCallback pointer to the Error Status Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan,
+ pFDCAN_ErrorStatusCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -1224,8 +1243,8 @@
*/
/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions
- * @brief FDCAN Configuration functions.
- *
+ * @brief FDCAN Configuration functions.
+ *
@verbatim
==============================================================================
##### Configuration functions #####
@@ -1370,10 +1389,10 @@
FDCAN_RXGFC_ANFE |
FDCAN_RXGFC_RRFS |
FDCAN_RXGFC_RRFE),
- ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) |
- (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) |
- (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) |
- (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos)));
+ ((NonMatchingStd << FDCAN_RXGFC_ANFS_Pos) |
+ (NonMatchingExt << FDCAN_RXGFC_ANFE_Pos) |
+ (RejectRemoteStd << FDCAN_RXGFC_RRFS_Pos) |
+ (RejectRemoteExt << FDCAN_RXGFC_RRFE_Pos)));
/* Return function status */
return HAL_OK;
@@ -1624,7 +1643,8 @@
* This parameter must be a number between 0x0000 and 0xFFFF
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod)
+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation,
+ uint32_t TimeoutPeriod)
{
/* Check function parameters */
assert_param(IS_FDCAN_TIMEOUT(TimeoutOperation));
@@ -1633,7 +1653,8 @@
if (hfdcan->State == HAL_FDCAN_STATE_READY)
{
/* Select timeout operation and configure period */
- MODIFY_REG(hfdcan->Instance->TOCC, (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
+ MODIFY_REG(hfdcan->Instance->TOCC,
+ (FDCAN_TOCC_TOS | FDCAN_TOCC_TOP), (TimeoutOperation | (TimeoutPeriod << FDCAN_TOCC_TOP_Pos)));
/* Return function status */
return HAL_OK;
@@ -1744,7 +1765,8 @@
* This parameter must be a number between 0x00 and 0x7F.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter)
+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset,
+ uint32_t TdcFilter)
{
/* Check function parameters */
assert_param(IS_FDCAN_MAX_VALUE(TdcOffset, 0x7FU));
@@ -1926,8 +1948,8 @@
*/
/** @defgroup FDCAN_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
+ * @brief Control functions
+ *
@verbatim
==============================================================================
##### Control functions #####
@@ -1935,15 +1957,18 @@
[..] This section provides functions allowing to:
(+) HAL_FDCAN_Start : Start the FDCAN module
(+) HAL_FDCAN_Stop : Stop the FDCAN module and enable access to configuration registers
- (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding transmission request
+ (+) HAL_FDCAN_AddMessageToTxFifoQ : Add a message to the Tx FIFO/Queue and activate the corresponding
+ transmission request
(+) HAL_FDCAN_GetLatestTxFifoQRequestBuffer : Get Tx buffer index of latest Tx FIFO/Queue request
(+) HAL_FDCAN_AbortTxRequest : Abort transmission request
(+) HAL_FDCAN_GetRxMessage : Get an FDCAN frame from the Rx FIFO zone into the message RAM
- (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone into the message RAM
+ (+) HAL_FDCAN_GetTxEvent : Get an FDCAN Tx event from the Tx Event FIFO zone
+ into the message RAM
(+) HAL_FDCAN_GetHighPriorityMessageStatus : Get high priority message status
(+) HAL_FDCAN_GetProtocolStatus : Get protocol status
(+) HAL_FDCAN_GetErrorCounters : Get error counter values
- (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending on the selected Tx buffer
+ (+) HAL_FDCAN_IsTxBufferMessagePending : Check if a transmission request is pending
+ on the selected Tx buffer
(+) HAL_FDCAN_GetRxFifoFillLevel : Return Rx FIFO fill level
(+) HAL_FDCAN_GetTxFifoFreeLevel : Return Tx FIFO free level
(+) HAL_FDCAN_IsRestrictedOperationMode : Check if the FDCAN peripheral entered Restricted Operation Mode
@@ -2072,7 +2097,8 @@
* @param pTxData pointer to a buffer containing the payload of the Tx frame.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData)
+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader,
+ uint8_t *pTxData)
{
uint32_t PutIndex;
@@ -2185,7 +2211,8 @@
* @param pRxData pointer to a buffer where the payload of the Rx frame will be stored.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation,
+ FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData)
{
uint32_t *RxAddress;
uint8_t *pData;
@@ -2396,7 +2423,8 @@
* @param HpMsgStatus pointer to an FDCAN_HpMsgStatusTypeDef structure.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan,
+ FDCAN_HpMsgStatusTypeDef *HpMsgStatus)
{
HpMsgStatus->FilterList = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FLST) >> FDCAN_HPMS_FLST_Pos);
HpMsgStatus->FilterIndex = ((hfdcan->Instance->HPMS & FDCAN_HPMS_FIDX) >> FDCAN_HPMS_FIDX_Pos);
@@ -2477,7 +2505,7 @@
/* Check function parameters */
assert_param(IS_FDCAN_TX_LOCATION_LIST(TxBufferIndex));
- /* Check pending transmittion request on the selected buffer */
+ /* Check pending transmission request on the selected buffer */
if ((hfdcan->Instance->TXBRP & TxBufferIndex) == 0U)
{
return 0;
@@ -2582,8 +2610,8 @@
*/
/** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management
- * @brief Interrupts management
- *
+ * @brief Interrupts management
+ *
@verbatim
==============================================================================
##### Interrupts management #####
@@ -2653,7 +2681,8 @@
* - FDCAN_IT_TX_ABORT_COMPLETE
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes)
+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs,
+ uint32_t BufferIndexes)
{
HAL_FDCAN_StateTypeDef state = hfdcan->State;
uint32_t ITs_lines_selection;
@@ -2671,24 +2700,38 @@
ITs_lines_selection = hfdcan->Instance->ILS;
/* Enable Interrupt lines */
- if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
+ if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
{
/* Enable Interrupt line 0 */
SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE0);
}
- if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
- (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
+ if ((((ActiveITs & FDCAN_IT_LIST_RX_FIFO0) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_RX_FIFO1) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_SMSG) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_MISC) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
+ (((ActiveITs & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
{
/* Enable Interrupt line 1 */
SET_BIT(hfdcan->Instance->ILE, FDCAN_INTERRUPT_LINE1);
@@ -2697,14 +2740,14 @@
if ((ActiveITs & FDCAN_IT_TX_COMPLETE) != 0U)
{
/* Enable Tx Buffer Transmission Interrupt to set TC flag in IR register,
- but interrupt will only occure if TC is enabled in IE register */
+ but interrupt will only occur if TC is enabled in IE register */
SET_BIT(hfdcan->Instance->TXBTIE, BufferIndexes);
}
if ((ActiveITs & FDCAN_IT_TX_ABORT_COMPLETE) != 0U)
{
/* Enable Tx Buffer Cancellation Finished Interrupt to set TCF flag in IR register,
- but interrupt will only occure if TCF is enabled in IE register */
+ but interrupt will only occur if TCF is enabled in IE register */
SET_BIT(hfdcan->Instance->TXBCIE, BufferIndexes);
}
@@ -2762,13 +2805,20 @@
ITs_lines_selection = hfdcan->Instance->ILS;
/* Check if some interrupts are still enabled on interrupt line 0 */
- if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
+ if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) == 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) == 0U)))
{
/* Do nothing */
}
@@ -2779,13 +2829,20 @@
}
/* Check if some interrupts are still enabled on interrupt line 1 */
- if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
- (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U) && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
+ if ((((ITs_enabled & FDCAN_IT_LIST_RX_FIFO0) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO0) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_RX_FIFO1) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_RX_FIFO1) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_SMSG) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_SMSG) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_TX_FIFO_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_TX_FIFO_ERROR) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_MISC) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_MISC) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_BIT_LINE_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_BIT_LINE_ERROR) != 0U)) || \
+ (((ITs_enabled & FDCAN_IT_LIST_PROTOCOL_ERROR) != 0U)
+ && (((ITs_lines_selection) & FDCAN_IT_GROUP_PROTOCOL_ERROR) != 0U)))
{
/* Do nothing */
}
@@ -3015,11 +3072,11 @@
__HAL_FDCAN_CLEAR_FLAG(hfdcan, ErrorStatusITs);
#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
- /* Call registered callback*/
- hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
+ /* Call registered callback*/
+ hfdcan->ErrorStatusCallback(hfdcan, ErrorStatusITs);
#else
- /* Error Status Callback */
- HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
+ /* Error Status Callback */
+ HAL_FDCAN_ErrorStatusCallback(hfdcan, ErrorStatusITs);
#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
}
@@ -3050,8 +3107,8 @@
*/
/** @defgroup FDCAN_Exported_Functions_Group5 Callback functions
- * @brief FDCAN Callback functions
- *
+ * @brief FDCAN Callback functions
+ *
@verbatim
==============================================================================
##### Callback functions #####
@@ -3273,8 +3330,8 @@
*/
/** @defgroup FDCAN_Exported_Functions_Group6 Peripheral State functions
- * @brief FDCAN Peripheral State functions
- *
+ * @brief FDCAN Peripheral State functions
+ *
@verbatim
==============================================================================
##### Peripheral State functions #####
@@ -3374,7 +3431,8 @@
* @param BufferIndex index of the buffer to be configured.
* @retval none
*/
-static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex)
+static void FDCAN_CopyMessageToRAM(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData,
+ uint32_t BufferIndex)
{
uint32_t TxElementW1;
uint32_t TxElementW2;
diff --git a/Src/stm32l5xx_hal_flash.c b/Src/stm32l5xx_hal_flash.c
index e42473c..38ce12c 100644
--- a/Src/stm32l5xx_hal_flash.c
+++ b/Src/stm32l5xx_hal_flash.c
@@ -11,7 +11,7 @@
*
@verbatim
==============================================================================
- ##### FLASH peripheral features #####
+ ##### Flash peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB C-Bus accesses
@@ -131,12 +131,12 @@
* @{
*/
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
- * @brief Programming operation functions
+/** @defgroup FLASH_Exported_Functions_Group1 Programming Operation functions
+ * @brief Programming Operation functions
*
@verbatim
===============================================================================
- ##### Programming operation functions #####
+ ##### Programming Operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
@@ -356,11 +356,11 @@
/**
* @brief FLASH end of operation interrupt callback.
- * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * Mass Erase: Bank number which has been requested to erase
- * Page Erase: Page which has been erased
- * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
- * Program: Address which was selected for data program
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure :
+ * @arg Mass Erase: Bank number which has been requested to erase
+ * @arg Page Erase: Page which has been erased
+ * (if 0xFFFFFFFF, it means that all the selected pages have been erased)
+ * @arg Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
@@ -375,10 +375,10 @@
/**
* @brief FLASH operation error interrupt callback.
- * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
- * Mass Erase: Bank number which has been requested to erase
- * Page Erase: Page number which returned an error
- * Program: Address which was selected for data program
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure :
+ * @arg Mass Erase: Bank number which has been requested to erase
+ * @arg Page Erase: Page number which returned an error
+ * @arg Program: Address which was selected for data program
* @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
diff --git a/Src/stm32l5xx_hal_flash_ex.c b/Src/stm32l5xx_hal_flash_ex.c
index 96570a2..e5f6de3 100644
--- a/Src/stm32l5xx_hal_flash_ex.c
+++ b/Src/stm32l5xx_hal_flash_ex.c
@@ -100,7 +100,7 @@
*/
/** @defgroup FLASHEx FLASHEx
- * @brief FALSH Extended HAL module driver
+ * @brief FLASH Extended HAL module driver
* @{
*/
@@ -140,12 +140,12 @@
* @{
*/
-/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
- * @brief Extended IO operation functions
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended Programming Operation functions
+ * @brief Extended Programming Operation functions
*
@verbatim
===============================================================================
- ##### Extended programming operation functions #####
+ ##### Extended Programming Operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the Extended FLASH
@@ -154,6 +154,7 @@
@endverbatim
* @{
*/
+
/**
* @brief Perform a mass erase or erase the specified FLASH memory pages.
* @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
@@ -552,6 +553,25 @@
#endif
/**
+ * @}
+ */
+
+/** @defgroup FLASHEx_Exported_Functions_Group2 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended Peripheral Control functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the FLASH
+ memory operations.
+
+@endverbatim
+ * @{
+ */
+
+/**
* @brief Configuration of the privilege attribute.
*
* @param PrivMode indicate privilege mode configuration
diff --git a/Src/stm32l5xx_hal_flash_ramfunc.c b/Src/stm32l5xx_hal_flash_ramfunc.c
index 7465d59..5c78d17 100644
--- a/Src/stm32l5xx_hal_flash_ramfunc.c
+++ b/Src/stm32l5xx_hal_flash_ramfunc.c
@@ -53,7 +53,7 @@
* @{
*/
-/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
+/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
* @brief FLASH functions executed from RAM
* @{
*/
@@ -71,12 +71,12 @@
* @{
*/
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
- * @brief Data transfers functions
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 RAM Execution functions
+ * @brief RAM Execution functions
*
@verbatim
===============================================================================
- ##### ramfunc functions #####
+ ##### RAM Execution functions #####
===============================================================================
[..]
This subsection provides a set of functions that should be executed from RAM.
@@ -130,7 +130,7 @@
*/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig)
{
- register uint32_t count, reg;
+ uint32_t count, reg;
HAL_StatusTypeDef status = HAL_ERROR;
/* Process Locked */
diff --git a/Src/stm32l5xx_hal_gpio.c b/Src/stm32l5xx_hal_gpio.c
index 66a0467..b4a9197 100644
--- a/Src/stm32l5xx_hal_gpio.c
+++ b/Src/stm32l5xx_hal_gpio.c
@@ -426,17 +426,16 @@
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
+ uint32_t odr;
+
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
- if ((GPIOx->ODR & GPIO_Pin) != 0U)
- {
- GPIOx->BRR = (uint32_t)GPIO_Pin;
- }
- else
- {
- GPIOx->BSRR = (uint32_t)GPIO_Pin;
- }
+ /* get current Output Data Register value */
+ odr = GPIOx->ODR;
+
+ /* Set selected pins that were at low level, and reset ones that were high */
+ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
}
/**
diff --git a/Src/stm32l5xx_hal_hash.c b/Src/stm32l5xx_hal_hash.c
index 46d2078..d5629a6 100644
--- a/Src/stm32l5xx_hal_hash.c
+++ b/Src/stm32l5xx_hal_hash.c
@@ -28,13 +28,13 @@
(##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA())
(+++) Enable the DMAx interface clock using
__DMAx_CLK_ENABLE()
- (+++) Configure and enable one DMA stream to manage data transfer from
- memory to peripheral (input stream). Managing data transfer from
+ (+++) Configure and enable one DMA channel to manage data transfer from
+ memory to peripheral (input channel). Managing data transfer from
peripheral to memory can be performed only using CPU.
(+++) Associate the initialized DMA handle to the HASH DMA handle
using __HAL_LINKDMA()
(+++) Configure the priority and enable the NVIC for the transfer complete
- interrupt on the DMA Stream: use
+ interrupt on the DMA channel: use
HAL_NVIC_SetPriority() and
HAL_NVIC_EnableIRQ()
@@ -71,10 +71,10 @@
well the computed digest.
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
- (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the Peripheral thru HAL_HASH_xxx_Start_DMA() API.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
- macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ macro then wrap-up the HASH processing in feeding the last input buffer through the
same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASH_xxx_Finish().
(+++) HMAC processing (requires to resort to extended functions):
@@ -105,6 +105,40 @@
(#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral.
+ *** Remarks on message length ***
+ ===================================
+ [..]
+ (#) HAL in interruption mode (interruptions driven)
+
+ (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes.
+ This is why, for driver implementation simplicity’s sake, user is requested to enter a message the
+ length of which is a multiple of 4 bytes.
+
+ (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR
+ to specify which bits to discard at the end of the complete message to process only the message bits
+ and not extra bits.
+
+ (##) If user needs to perform a hash computation of a large input buffer that is spread around various places
+ in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it
+ becomes necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral.
+ It is advised to the user to
+ (+++) achieve the first formatting operation by software then enter the data
+ (+++) while the Peripheral is processing the first input set, carry out the second formatting operation by software, to be ready when DINIS occurs.
+ (+++) repeat step 2 until the whole message is processed.
+
+ [..]
+ (#) HAL in DMA mode
+
+ (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis.
+ The same field described above in HASH_STR is used to specify which bits to discard at the end of the DMA transfer
+ to process only the message bits and not extra bits. Due to hardware implementation, this is possible only at the
+ end of the complete message. When several DMA transfers are needed to enter the message, this is not applicable at
+ the end of the intermediary transfers.
+
+ (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive chunks of data
+ by software while the DMA transfer and processing is on-going for the first parts of the message. Due to the 32-bit alignment
+ required for the DMA transfer, it is underlined that the software formatting operation is more complex than in the IT mode.
+
*** Callback registration ***
===================================
[..]
@@ -157,7 +191,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -175,7 +209,7 @@
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
-#if defined (HASH)
+
/** @defgroup HASH HASH
* @brief HASH HAL module driver.
@@ -449,7 +483,7 @@
* @brief Input data transfer complete call back.
* @note HAL_HASH_InCpltCallback() is called when the complete input message
* has been fed to the Peripheral. This API is invoked only when input data are
- * entered under interruption or thru DMA.
+ * entered under interruption or through DMA.
* @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set),
* HAL_HASH_InCpltCallback() is called at the end of each buffer feeding
* to the Peripheral.
@@ -1460,6 +1494,7 @@
/* Make sure there is enough time to suspend the processing */
tmp_remaining_DMATransferSize_inWords = ((DMA_Channel_TypeDef *)hhash->hdmain->Instance)->CNDTR;
+
if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT)
{
/* No suspension attempted since almost to the end of the transferred data. */
@@ -1467,7 +1502,7 @@
return HAL_ERROR;
}
- /* Wait for DMAS to be reset */
+ /* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
@@ -1478,19 +1513,26 @@
return HAL_ERROR;
}
- /* Wait for DMAS to be set */
+ /* Wait for BUSY flag to be set */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
}
/* Disable DMA channel */
- /* No need to check the returned value of HAL_DMA_Abort. */
- /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for HASH. */
- (void) HAL_DMA_Abort(hhash->hdmain);
+ /* Note that the Abort function will
+ - Clear the transfer error flags
+ - Unlock
+ - Set the State
+ */
+ if (HAL_DMA_Abort(hhash->hdmain) !=HAL_OK)
+ {
+ return HAL_ERROR;
+ }
/* Clear DMAE bit */
CLEAR_BIT(HASH->CR,HASH_CR_DMAE);
+ /* Wait for BUSY flag to be reset */
if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK)
{
return HAL_TIMEOUT;
@@ -1687,11 +1729,11 @@
/* Configure the Number of valid bits in last word of the message */
__HAL_HASH_SET_NBVALIDBITS(buffersize);
- /* Set the HASH DMA transfert completion call back */
+ /* Set the HASH DMA transfer completion call back */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
- /* Enable the DMA In DMA Stream */
- status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize%4U)!=0U) ? ((buffersize+3U)/4U):(buffersize/4U)));
+ /* Enable the DMA In DMA channel */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((buffersize %4U)!=0U) ? ((buffersize+(4U-(buffersize %4U)))/4U):(buffersize/4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
@@ -1766,56 +1808,47 @@
inputaddr+=4U;
/* If the suspension flag has been raised and if the processing is not about
- to end, suspend processing */
- if ((HASH_NBW_PUSHED() == 0U) /* If Peripheral FIFO is empty (condition for DINIS to raise) */ \
- && (buffercounter != 0U) /* and if at least one word has been written */ \
- && ((buffercounter+4U) < Size) /* and if the processing is not about to end */ \
- && (hhash->SuspendRequest == HAL_HASH_SUSPEND) ) /* and if suspension is requested */
+ to end, suspend processing */
+ if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4U) < Size))
{
- /* Wait first for BUSY flag to be cleared */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) == HAL_OK)
+ /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
+ in the input buffer */
+ if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))
{
- /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free
- in the input buffer.
- No error management is done if DINIS doesn't raise before time out:
- input block data feeding is carried on */
- if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DINIS, RESET, HASH_TIMEOUTVALUE) == HAL_OK)
+ /* Reset SuspendRequest */
+ hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+
+ /* Depending whether the key or the input data were fed to the Peripheral, the feeding point
+ reached at suspension time is not saved in the same handle fields */
+ if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
{
- /* Reset SuspendRequest */
- hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE;
+ /* Save current reading and writing locations of Input and Output buffers */
+ hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hhash->HashInCount = Size - (buffercounter + 4U);
+ }
+ else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
+ {
+ /* Save current reading and writing locations of Input and Output buffers */
+ hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
+ /* Save the number of bytes that remain to be processed at this point */
+ hhash->HashKeyCount = Size - (buffercounter + 4U);
+ }
+ else
+ {
+ /* Unexpected phase: unlock process and report error */
+ hhash->State = HAL_HASH_STATE_READY;
+ __HAL_UNLOCK(hhash);
+ return HAL_ERROR;
+ }
- /* Depending whether the key or the input data were fed to the Peripheral, the feeding point
- reached at suspension time is not saved in the same handle fields */
- if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2))
- {
- /* Save current reading and writing locations of Input and Output buffers */
- hhash->pHashInBuffPtr = (uint8_t *)inputaddr;
- /* Save the number of bytes that remain to be processed at this point */
- hhash->HashInCount = Size - (buffercounter + 4U);
- }
- else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
- {
- /* Save current reading and writing locations of Input and Output buffers */
- hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr;
- /* Save the number of bytes that remain to be processed at this point */
- hhash->HashKeyCount = Size - (buffercounter + 4U);
- }
- else
- {
- /* Unexpected phase: unlock process and report error */
- hhash->State = HAL_HASH_STATE_READY;
- __HAL_UNLOCK(hhash);
- return HAL_ERROR;
- }
+ /* Set the HASH state to Suspended and exit to stop entering data */
+ hhash->State = HAL_HASH_STATE_SUSPENDED;
- /* Set the HASH state to Suspended and exit to stop entering data */
- hhash->State = HAL_HASH_STATE_SUSPENDED;
-
- return HAL_OK;
- } /* if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DINIS, RESET, HASH_TIMEOUTVALUE) == HAL_OK) */
- } /* if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) == HAL_OK) */
- }
- } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
+ return HAL_OK;
+ } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) */
+ } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */
+ } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */
/* At this point, all the data have been entered to the Peripheral: exit */
return HAL_OK;
@@ -2033,7 +2066,7 @@
return HAL_OK;
}
- /* Enter input data in the Peripheral thru HASH_Write_Block_Data() call and
+ /* Enter input data in the Peripheral through HASH_Write_Block_Data() call and
check whether the digest calculation has been triggered */
if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED)
{
@@ -2898,11 +2931,11 @@
HAL_StatusTypeDef status ;
HAL_HASH_StateTypeDef State_tmp = hhash->State;
-#if defined (HASH_CR_MDMAT)
+
/* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set
(case of multi-buffer HASH processing) */
assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size));
-#endif /* MDMA defined*/
+
/* If State is ready or suspended, start or resume polling-based HASH processing */
if((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED))
{
@@ -2965,7 +2998,7 @@
}
- /* Set the HASH DMA transfert complete callback */
+ /* Set the HASH DMA transfer complete callback */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Set the DMA error callback */
hhash->hdmain->XferErrorCallback = HASH_DMAError;
@@ -2973,8 +3006,8 @@
/* Store number of words already pushed to manage proper DMA processing suspension */
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
- /* Enable the DMA In DMA Stream */
- status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize%4U)!=0U) ? ((inputSize+3U)/4U):(inputSize/4U)));
+ /* Enable the DMA In DMA channel */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
@@ -3354,7 +3387,7 @@
}
- /* Set the HASH DMA transfert complete callback */
+ /* Set the HASH DMA transfer complete callback */
hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt;
/* Set the DMA error callback */
hhash->hdmain->XferErrorCallback = HASH_DMAError;
@@ -3362,8 +3395,8 @@
/* Store number of words already pushed to manage proper DMA processing suspension */
hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED();
- /* Enable the DMA In DMA Stream */
- status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+3U)/4U):(inputSize/4U)));
+ /* Enable the DMA In DMA channel */
+ status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, (((inputSize %4U)!=0U) ? ((inputSize+(4U-(inputSize %4U)))/4U):(inputSize/4U)));
/* Enable DMA requests */
SET_BIT(HASH->CR, HASH_CR_DMAE);
@@ -3394,7 +3427,7 @@
/**
* @}
*/
-#endif /* HASH*/
+
/**
* @}
*/
diff --git a/Src/stm32l5xx_hal_hash_ex.c b/Src/stm32l5xx_hal_hash_ex.c
index ec65ba5..e3e0d0d 100644
--- a/Src/stm32l5xx_hal_hash_ex.c
+++ b/Src/stm32l5xx_hal_hash_ex.c
@@ -5,7 +5,7 @@
* @brief Extended HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral for SHA-224 and SHA-256
- * alogrithms:
+ * algorithms:
* + HASH or HMAC processing in polling mode
* + HASH or HMAC processing in interrupt mode
* + HASH or HMAC processing in DMA mode
@@ -46,10 +46,10 @@
(##) In DMA mode, multi-buffer HASH and HMAC processing are possible.
- (+++) HASH processing: once initialization is done, MDMAT bit must be set thru __HAL_HASH_SET_MDMAT() macro.
- From that point, each buffer can be fed to the Peripheral thru HAL_HASHEx_xxx_Start_DMA() API.
+ (+++) HASH processing: once initialization is done, MDMAT bit must be set through __HAL_HASH_SET_MDMAT() macro.
+ From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API.
Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT()
- macro then wrap-up the HASH processing in feeding the last input buffer thru the
+ macro then wrap-up the HASH processing in feeding the last input buffer through the
same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to
API HAL_HASHEx_xxx_Finish().
@@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© Copyright (c) 2018 STMicroelectronics.
+ * <h2><center>© Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
@@ -90,7 +90,7 @@
/** @addtogroup STM32L5xx_HAL_Driver
* @{
*/
-#if defined (HASH)
+
/** @defgroup HASHEx HASHEx
* @brief HASH HAL extended module driver.
@@ -100,7 +100,7 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
-#if defined (HASH_CR_MDMAT)
+
/** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions
* @{
@@ -388,7 +388,7 @@
*
@verbatim
===============================================================================
- ##### DMA mode HASH extended processing functionss #####
+ ##### DMA mode HASH extended processing functions #####
===============================================================================
[..] This section provides functions allowing to calculate in DMA mode
the hash value using one of the following algorithms:
@@ -1011,7 +1011,7 @@
* @}
*/
-#endif /* MDMA defined*/
+
/**
* @}
*/
@@ -1020,7 +1020,7 @@
/**
* @}
*/
-#endif /* HASH*/
+
/**
* @}
*/
diff --git a/Src/stm32l5xx_hal_i2c.c b/Src/stm32l5xx_hal_i2c.c
index a648e00..267f5af 100644
--- a/Src/stm32l5xx_hal_i2c.c
+++ b/Src/stm32l5xx_hal_i2c.c
@@ -93,7 +93,7 @@
[..]
(+) A specific option field manage the different steps of a sequential transfer
(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
- (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
+ (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
@@ -112,7 +112,7 @@
or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
- Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
interface.
@@ -122,7 +122,7 @@
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
- (+) Differents sequential I2C interfaces are listed below:
+ (+) Different sequential I2C interfaces are listed below:
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
@@ -390,8 +390,10 @@
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
/* Private functions for I2C transfer IRQ handler */
static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
@@ -400,7 +402,8 @@
static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
@@ -417,7 +420,8 @@
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
/* Private function to handle start, restart or stop a transfer */
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request);
/* Private function to Convert Specific options */
static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);
@@ -432,8 +436,8 @@
*/
/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -672,7 +676,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
+ pI2C_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -977,8 +982,8 @@
*/
/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -1060,7 +1065,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1174,7 +1180,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1550,7 +1557,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
{
uint32_t xfermode;
@@ -1786,7 +1794,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
@@ -1929,7 +1938,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size)
{
uint32_t xfermode;
HAL_StatusTypeDef dmaxferstatus;
@@ -2280,7 +2290,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -2372,8 +2383,7 @@
}
}
- }
- while (hi2c->XferCount > 0U);
+ } while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
@@ -2415,7 +2425,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
@@ -2507,8 +2518,7 @@
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
- }
- while (hi2c->XferCount > 0U);
+ } while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
@@ -2548,7 +2558,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
@@ -2639,7 +2650,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
@@ -2729,7 +2741,8 @@
* @param Size Amount of data to be sent
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
@@ -2873,7 +2886,8 @@
* @param Size Amount of data to be read
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
{
uint32_t tickstart;
uint32_t xfermode;
@@ -3124,8 +3138,7 @@
/* Increment Trials */
I2C_Trials++;
- }
- while (I2C_Trials < Trials);
+ } while (I2C_Trials < Trials);
/* Update I2C state */
hi2c->State = HAL_I2C_STATE_READY;
@@ -3156,7 +3169,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
@@ -3240,7 +3254,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
@@ -3402,7 +3417,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_READ;
@@ -3486,7 +3502,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t xfermode;
uint32_t xferrequest = I2C_GENERATE_START_READ;
@@ -3646,7 +3663,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -3741,7 +3759,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
HAL_StatusTypeDef dmaxferstatus;
@@ -3920,7 +3939,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -4015,7 +4035,8 @@
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
HAL_StatusTypeDef dmaxferstatus;
@@ -4300,8 +4321,8 @@
*/
/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/**
* @brief This function handles I2C event interrupt request.
@@ -4539,8 +4560,8 @@
*/
/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
- * @brief Peripheral State, Mode and Error functions
- *
+ * @brief Peripheral State, Mode and Error functions
+ *
@verbatim
===============================================================================
##### Peripheral State, Mode and Error functions #####
@@ -4577,11 +4598,11 @@
}
/**
-* @brief Return the I2C error code.
+ * @brief Return the I2C error code.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
-* @retval I2C Error Code
-*/
+ * @retval I2C Error Code
+ */
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
{
return hi2c->ErrorCode;
@@ -4767,7 +4788,8 @@
/* So clear Flag NACKF only */
if (hi2c->XferCount == 0U)
{
- if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, tmpITFlags);
@@ -4827,7 +4849,8 @@
I2C_ITSlaveSeqCplt(hi2c);
}
}
- else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
+ else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \
+ (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET))
{
I2C_ITAddrCplt(hi2c, tmpITFlags);
}
@@ -4835,7 +4858,7 @@
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
- /* Check if all Datas have already been sent */
+ /* Check if all data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
if (hi2c->XferCount > 0U)
{
@@ -5063,7 +5086,8 @@
if (treatdmanack == 1U)
{
- if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
@@ -5151,7 +5175,8 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
@@ -5204,7 +5229,8 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
+ uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
@@ -5719,7 +5745,7 @@
}
else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
- /* Call the Sequential Complete callback, to inform upper layer of the end of Tranfer */
+ /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */
I2C_ITSlaveSeqCplt(hi2c);
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
@@ -5856,7 +5882,7 @@
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
- /* If state is an abort treatment on goind, don't change state */
+ /* If state is an abort treatment on going, don't change state */
/* This change will be do later */
if (hi2c->State != HAL_I2C_STATE_ABORT)
{
@@ -5868,7 +5894,8 @@
/* Abort DMA TX transfer if any */
tmppreviousstate = hi2c->PreviousState;
- if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
+ if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
+ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
@@ -5897,7 +5924,8 @@
}
}
/* Abort DMA RX transfer if any */
- else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
+ else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \
+ (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX)))
{
if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
@@ -6189,7 +6217,8 @@
* @param Tickstart Tick start value
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout, uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
@@ -6421,7 +6450,8 @@
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
@@ -6429,8 +6459,11 @@
assert_param(IS_TRANSFER_REQUEST(Request));
/* update CR2 register */
- MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+ MODIFY_REG(hi2c->Instance->CR2,
+ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) |
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
@@ -6570,7 +6603,7 @@
}
/**
- * @brief Convert I2Cx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.
* @param hi2c I2C handle.
* @retval None
*/
diff --git a/Src/stm32l5xx_hal_i2c_ex.c b/Src/stm32l5xx_hal_i2c_ex.c
index b3ba207..de0bd47 100644
--- a/Src/stm32l5xx_hal_i2c_ex.c
+++ b/Src/stm32l5xx_hal_i2c_ex.c
@@ -73,7 +73,7 @@
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
- *
+ *
@verbatim
===============================================================================
##### Extended features functions #####
diff --git a/Src/stm32l5xx_hal_icache.c b/Src/stm32l5xx_hal_icache.c
index 1d7d8cd..469018d 100644
--- a/Src/stm32l5xx_hal_icache.c
+++ b/Src/stm32l5xx_hal_icache.c
@@ -10,12 +10,50 @@
* + Monitoring management
* + Memory address remap management
@verbatim
- ===============================================================================
+ ==============================================================================
+ ##### ICACHE main features #####
+ ==============================================================================
+ [..]
+ The Instruction Cache (ICACHE) is introduced on C-AHB code bus of
+ Cortex-M33 processor to improve performance when fetching instruction
+ and data from both internal and external memories. It allows close to
+ zero wait states performance.
+
+ (+) The ICACHE provides two performance counters (Hit and Miss),
+ cache invalidate maintenance operation, error management and TrustZone
+ security support.
+
+ (+) The ICACHE provides additionnaly the possibility to remap input address
+ falling into up to four memory regions (used to remap aliased code in
+ external memories to the internal Code region, for execution)
+
+ ===============================================================================
##### How to use this driver #####
- ===============================================================================
+ ===============================================================================
[..]
The ICACHE HAL driver can be used as follows:
+ (#) Enable and disable the Instruction Cache with respectively
+ @ref HAL_ICACHE_Enable() and @ref HAL_ICACHE_Disable()
+
+ (#) Configure the Instruction Cache mode with @ref HAL_ICACHE_ConfigAssociativityMode()
+
+ (#) Initiate the cache maintenance invalidation procedure with either
+ @ref HAL_ICACHE_Invalidate() (blocking mode) or @ref HAL_ICACHE_Invalidate_IT()
+ (interrupt mode). When interrupt mode is used, the callback function
+ @ref HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate
+ procedure is complete. The function @ref HAL_ICACHE_WaitForInvalidateComplete()
+ may be called to wait for the end of the invalidate procedure automatically
+ initiated when disabling the Instruction Cache with @ref HAL_ICACHE_Disable()
+
+ (#) Use the performance monitoring counters for Hit and Miss with the following
+ functions: @ref HAL_ICACHE_Monitor_Start(), @ref HAL_ICACHE_Monitor_Stop(),
+ @ref HAL_ICACHE_Monitor_Reset(), @ref HAL_ICACHE_Monitor_GetHitValue() and
+ @ref HAL_ICACHE_Monitor_GetMissValue()
+
+ (#) Enable and disable up to four regions to remap input address from external
+ memories to the internal Code region for execution with
+ @ref HAL_ICACHE_EnableRemapRegion() and @ref HAL_ICACHE_DisableRemapRegion()
@endverbatim
******************************************************************************
@@ -46,7 +84,6 @@
#ifdef HAL_ICACHE_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants
* @{
@@ -68,13 +105,27 @@
* @{
*/
+/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions
+ * @brief Initialization and control functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Initialization and control functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to initialize and control the
+ Instruction Cache (mode, invalidate procedure, performance counters).
+ @endverbatim
+ * @{
+ */
+
/**
* @brief Configure the Instruction Cache cache associativity mode selection.
* @param AssociativityMode Associativity mode selection
* This parameter can be one of the following values:
* @arg ICACHE_1WAY 1-way cache (direct mapped cache)
* @arg ICACHE_2WAYS 2-ways set associative cache (default)
- * @retval HAL status
+ * @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode)
{
@@ -97,13 +148,15 @@
}
/**
- * @brief DeInitialize the Instruction cache.
- * @retval HAL status
+ * @brief DeInitialize the Instruction Cache.
+ * @retval HAL status (HAL_OK/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_DeInit(void)
{
+ HAL_StatusTypeDef status;
+
/* Disable cache with reset value for 2-ways set associative mode */
- WRITE_REG(ICACHE->CR, 4U);
+ WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);
/* Stop monitor and reset monitor values */
(void)HAL_ICACHE_Monitor_Stop(ICACHE_MONITOR_HIT_MISS);
@@ -115,46 +168,51 @@
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_2);
(void)HAL_ICACHE_DisableRemapRegion(ICACHE_REGION_3);
- return HAL_OK;
-}
+ /* Wait for end of invalidate cache procedure */
+ status = HAL_ICACHE_WaitForInvalidateComplete();
-/**
- * @brief Enable the Instruction cache.
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ICACHE_Enable(void)
-{
- HAL_StatusTypeDef status = HAL_OK;
-
- /* Check no ongoing operation */
- if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
- {
- status = HAL_ERROR;
- }
- else
- {
- SET_BIT(ICACHE->CR, ICACHE_CR_EN);
- }
+ /* Clear any pending flags */
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);
return status;
}
/**
- * @brief Disable the Instruction cache.
- * @retval HAL status
+ * @brief Enable the Instruction Cache.
+ * @note This function always returns HAL_OK even if there is any ongoing
+ * cache operation. The Instruction Cache is bypassed until the
+ * cache operation completes.
+ * @retval HAL status (HAL_OK)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Enable(void)
+{
+ SET_BIT(ICACHE->CR, ICACHE_CR_EN);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable the Instruction Cache.
+ * @note This function waits for the cache being disabled but
+ * not for the end of the automatic cache invalidation procedure.
+ * @retval HAL status (HAL_OK/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_Disable(void)
{
HAL_StatusTypeDef status = HAL_OK;
uint32_t tickstart;
- /* Get timeout */
- tickstart = HAL_GetTick();
+ /* Reset BSYENDF before to disable the instruction cache */
+ /* that starts a cache invalidation procedure */
+ CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
- /* Wait for end of instruction cache disabling */
- while (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 1U)
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for instruction cache being disabled */
+ while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)
{
if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE)
{
@@ -167,14 +225,14 @@
}
/**
- * @brief Invalidate the Instruction cache.
- * @note This function waits for end of cache invalidation
- * @retval HAL status
+ * @brief Invalidate the Instruction Cache.
+ * @note This function waits for the end of cache invalidation procedure
+ * and clears the associated BSYENDF flag.
+ * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT)
*/
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void)
{
- HAL_StatusTypeDef status = HAL_OK;
- uint32_t tickstart;
+ HAL_StatusTypeDef status;
/* Check no ongoing operation */
if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
@@ -183,35 +241,25 @@
}
else
{
- /* Make sure BSYENDF is reset */
- CLEAR_BIT(ICACHE->SR, ICACHE_SR_BSYENDF);
-
- /* Get timeout */
- tickstart = HAL_GetTick();
+ /* Make sure BSYENDF is reset before to start cache invalidation */
+ CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Launch cache invalidation */
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
- /* Wait for end of cache invalidation */
- while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
- {
- if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE)
- {
- status = HAL_TIMEOUT;
- break;
- }
- }
+ status = HAL_ICACHE_WaitForInvalidateComplete();
}
return status;
}
/**
- * @brief Invalidate the Instruction cache with interrupt.
+ * @brief Invalidate the Instruction Cache with interrupt.
* @note This function launches cache invalidation and returns.
* User application shall resort to interrupt generation to check
- * the end of the cache invalidation with the BSYENDF flag.
- * @retval HAL status
+ * the end of the cache invalidation with the BSYENDF flag and the
+ * HAL_ICACHE_InvalidateCompleteCallback() callback.
+ * @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void)
{
@@ -225,7 +273,7 @@
else
{
/* Make sure BSYENDF is reset */
- CLEAR_BIT(ICACHE->SR, ICACHE_SR_BSYENDF);
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
/* Enable end of cache invalidation interrupt */
SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
@@ -238,8 +286,142 @@
}
/**
+ * @brief Wait for the end of the Instruction Cache invalidate procedure.
+ * @note This function checks and clears the BSYENDF flag when set.
+ * @retval HAL status (HAL_OK/HAL_TIMEOUT)
+ */
+HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ uint32_t tickstart;
+
+ /* Check if ongoing invalidation operation */
+ if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)
+ {
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for end of cache invalidation */
+ while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)
+ {
+ if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE)
+ {
+ status = HAL_TIMEOUT;
+ break;
+ }
+ }
+ }
+
+ /* Clear BSYENDF */
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+ return status;
+}
+
+
+/**
+ * @brief Start the Instruction Cache performance monitoring.
+ * @param MonitorType Monitoring type
+ * This parameter can be one of the following values:
+ * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
+ * @arg ICACHE_MONITOR_HIT Hit monitoring
+ * @arg ICACHE_MONITOR_MISS Miss monitoring
+ * @retval HAL status (HAL_OK)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType)
+{
+ /* Check the parameters */
+ assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
+
+ SET_BIT(ICACHE->CR, MonitorType);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Stop the Instruction Cache performance monitoring.
+ * @note Stopping the monitoring does not reset the values.
+ * @param MonitorType Monitoring type
+ * This parameter can be one of the following values:
+ * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
+ * @arg ICACHE_MONITOR_HIT Hit monitoring
+ * @arg ICACHE_MONITOR_MISS Miss monitoring
+ * @retval HAL status (HAL_OK)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType)
+{
+ /* Check the parameters */
+ assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
+
+ CLEAR_BIT(ICACHE->CR, MonitorType);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Reset the Instruction Cache performance monitoring values.
+ * @param MonitorType Monitoring type
+ * This parameter can be one of the following values:
+ * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
+ * @arg ICACHE_MONITOR_HIT Hit monitoring
+ * @arg ICACHE_MONITOR_MISS Miss monitoring
+ * @retval HAL status (HAL_OK)
+ */
+HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType)
+{
+ /* Check the parameters */
+ assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
+
+ /* Force/Release reset */
+ SET_BIT(ICACHE->CR, (MonitorType << 2U));
+ CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Get the Instruction Cache performance Hit monitoring value.
+ * @note Upon reaching the 32-bit maximum value, monitor does not wrap.
+ * @retval Hit monitoring value
+ */
+uint32_t HAL_ICACHE_Monitor_GetHitValue(void)
+{
+ return (ICACHE->HMONR);
+}
+
+/**
+ * @brief Get the Instruction Cache performance Miss monitoring value.
+ * @note Upon reaching the 32-bit maximum value, monitor does not wrap.
+ * @retval Miss monitoring value
+ */
+uint32_t HAL_ICACHE_Monitor_GetMissValue(void)
+{
+ return (ICACHE->MMONR);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions
+ * @brief IRQ and callback functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### IRQ and callback functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to handle ICACHE global interrupt
+ and the associated callback functions.
+ @endverbatim
+ * @{
+ */
+
+/**
* @brief Handle the Instruction Cache interrupt request.
- * @note This API should be called under the ICACHE_IRQHandler().
+ * @note This function should be called under the ICACHE_IRQHandler().
+ * @note This function respectively disables the interrupt and clears the
+ * flag of any pending flag before calling the associated user callback.
* @retval None
*/
void HAL_ICACHE_IRQHandler(void)
@@ -251,21 +433,27 @@
/* Check Instruction cache Error interrupt flag */
if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U)
{
- /* Instruction cache error interrupt user callback */
- HAL_ICACHE_ErrorCallback();
+ /* Disable error interrupt */
+ CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
/* Clear ICACHE error pending flag */
- WRITE_REG(ICACHE->FCR, ICACHE_FLAG_ERROR);
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
+
+ /* Instruction cache error interrupt user callback */
+ HAL_ICACHE_ErrorCallback();
}
/* Check Instruction cache BusyEnd interrupt flag */
if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U)
{
- /* Instruction cache busyend interrupt user callback */
- HAL_ICACHE_InvalidateCompleteCallback();
+ /* Disable end of cache invalidation interrupt */
+ CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
/* Clear ICACHE busyend pending flag */
- WRITE_REG(ICACHE->FCR, ICACHE_FLAG_BUSYEND);
+ WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
+
+ /* Instruction cache busyend interrupt user callback */
+ HAL_ICACHE_InvalidateCompleteCallback();
}
}
@@ -289,93 +477,31 @@
*/
}
-
/**
- * @brief Start the Instruction Cache performance monitoring.
- * @param MonitorType Monitoring type
- * This parameter can be one of the following values:
- * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
- * @arg ICACHE_MONITOR_HIT Hit monitoring
- * @arg ICACHE_MONITOR_MISS Miss monitoring
- * @retval HAL status
+ * @}
*/
-HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType)
-{
- /* Check the parameters */
- assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
- SET_BIT(ICACHE->CR, MonitorType);
-
- return HAL_OK;
-}
-
-/**
- * @brief Stop the Instruction Cache performance monitoring.
- * @note Stopping the monitoring does not reset the values.
- * @param MonitorType Monitoring type
- * This parameter can be one of the following values:
- * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
- * @arg ICACHE_MONITOR_HIT Hit monitoring
- * @arg ICACHE_MONITOR_MISS Miss monitoring
- * @retval HAL status
+/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions
+ * @brief Memory remapped regions functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### Memory remapped regions functions #####
+ ==============================================================================
+ [..]
+ This section provides functions allowing to manage the remapping of
+ external memories to internal Code for execution.
+ @endverbatim
+ * @{
*/
-HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType)
-{
- /* Check the parameters */
- assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
-
- CLEAR_BIT(ICACHE->CR, MonitorType);
-
- return HAL_OK;
-}
-
-/**
- * @brief Reset the Instruction Cache performance monitoring values.
- * @param MonitorType Monitoring type
- * This parameter can be one of the following values:
- * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring
- * @arg ICACHE_MONITOR_HIT Hit monitoring
- * @arg ICACHE_MONITOR_MISS Miss monitoring
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType)
-{
- /* Check the parameters */
- assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType));
-
- /* Force/Release reset */
- SET_BIT(ICACHE->CR, (MonitorType << 2U));
- CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));
-
- return HAL_OK;
-}
-
-/**
- * @brief Get the Instruction Cache performance Hit monitoring value.
- * @note Upon reaching the maximum value, monitor does not wrap.
- * @retval Hit monitoring value
- */
-uint32_t HAL_ICACHE_Monitor_GetHitValue(void)
-{
- return (ICACHE->HMONR);
-}
-
-/**
- * @brief Get the Instruction Cache performance Miss monitoring value.
- * @note Upon reaching the maximum value, monitor does not wrap.
- * @retval Miss monitoring value
- */
-uint32_t HAL_ICACHE_Monitor_GetMissValue(void)
-{
- return (ICACHE->MMONR);
-}
/**
* @brief Configure and enable a region for memory remapping.
+ * @note The Instruction Cache and the region must be disabled.
* @param Region Region number
This parameter can be a value of @arg @ref ICACHE_Region
* @param sRegionConfig Structure of ICACHE region configuration parameters
- * @retval HAL status
+ * @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, ICACHE_RegionConfigTypeDef *sRegionConfig)
{
@@ -432,7 +558,7 @@
* @brief Disable the memory remapping for a predefined region.
* @param Region Region number
This parameter can be a value of @arg @ref ICACHE_Region
- * @retval HAL status
+ * @retval HAL status (HAL_OK/HAL_ERROR)
*/
HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region)
{
@@ -463,6 +589,10 @@
* @}
*/
+/**
+ * @}
+ */
+
#endif /* HAL_ICACHE_MODULE_ENABLED */
/**
diff --git a/Src/stm32l5xx_hal_irda.c b/Src/stm32l5xx_hal_irda.c
index 5e0012a..6b3ac43 100644
--- a/Src/stm32l5xx_hal_irda.c
+++ b/Src/stm32l5xx_hal_irda.c
@@ -40,7 +40,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter),
the normal or low power mode and the clock prescaler in the hirda handle Init structure.
@@ -771,13 +772,16 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_IRDA_ErrorCallback() user callback is executed. Transfer is kept ongoing on IRDA side.
+ to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+ in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+ to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on IRDA side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed.
+ Error code is set to allow user to identify error type, and
+ HAL_IRDA_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -815,7 +819,7 @@
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->gState = HAL_IRDA_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->TxXferSize = Size;
@@ -905,7 +909,7 @@
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
hirda->RxState = HAL_IRDA_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
hirda->RxXferSize = Size;
@@ -1280,7 +1284,7 @@
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_IRDA_CLEAR_OREFLAG(hirda);
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE);
SET_BIT(hirda->Instance->CR3, USART_CR3_EIE);
@@ -1380,7 +1384,8 @@
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda)
{
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* Disable the IRDA DMA Tx request if enabled */
@@ -1578,7 +1583,8 @@
uint32_t abortcplt = 1U;
/* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+ CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | \
+ USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
/* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised
@@ -2322,7 +2328,7 @@
/* Initialize the IRDA ErrorCode */
hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
@@ -2377,7 +2383,8 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE);
diff --git a/Src/stm32l5xx_hal_iwdg.c b/Src/stm32l5xx_hal_iwdg.c
index bc876e1..2897c5a 100644
--- a/Src/stm32l5xx_hal_iwdg.c
+++ b/Src/stm32l5xx_hal_iwdg.c
@@ -16,33 +16,43 @@
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
- (+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
- if the main clock fails.
+ (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays
+ active even if the main clock fails.
- (+) Once the IWDG is started, the LSI is forced ON and both can not be
+ (+) Once the IWDG is started, the LSI is forced ON and both cannot be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
- the IWDG_RLR value is reloaded in the counter and the watchdog reset is
- prevented.
+ the IWDG_RLR value is reloaded into the counter and the watchdog reset
+ is prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
- (+) Debug mode : When the microcontroller enters debug mode (core halted),
+ (+) Debug mode: When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32L5xx
- devices provide the capability to measure the LSI frequency (LSI clock
- connected internally to TIM16 CH1 input capture). The measured value
- can be used to have an IWDG timeout with an acceptable accuracy.
+ The IWDG timeout may vary due to LSI clock frequency dispersion.
+ STM32L5xx devices provide the capability to measure the LSI clock
+ frequency (LSI clock is internally connected to TIM16 CH1 input capture).
+ The measured value can be used to have an IWDG timeout with an
+ acceptable accuracy.
+
+ [..] Default timeout value (necessary for IWDG_SR status register update):
+ Constant LSI_VALUE is defined based on the nominal LSI clock frequency.
+ This frequency being subject to variations as mentioned above, the
+ default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT
+ below) may become too short or too long.
+ In such cases, this default timeout value can be tuned by redefining
+ the constant LSI_VALUE at user-application level (based, for instance,
+ on the measured LSI clock frequency as explained above).
##### How to use this driver #####
==============================================================================
@@ -108,10 +118,14 @@
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
-/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
- higher prescaler (256), and according to LSI variation, we need to wait at
- least 6 cycles so 48 ms. */
-#define HAL_IWDG_DEFAULT_TIMEOUT 48u
+/* Status register needs up to 5 LSI clock periods divided by the clock
+ prescaler to be updated. The number of LSI clock periods is upper-rounded to
+ 6 for the timeout value calculation.
+ The timeout value is also calculated using the highest prescaler (256) and
+ the LSI_VALUE constant. The value of this constant can be changed by the user
+ to take into account possible LSI clock period variations.
+ The timeout value is multiplied by 1000 to be converted in milliseconds. */
+#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE)
/**
* @}
*/
diff --git a/Src/stm32l5xx_hal_lptim.c b/Src/stm32l5xx_hal_lptim.c
index dd18b61..2bb1654 100644
--- a/Src/stm32l5xx_hal_lptim.c
+++ b/Src/stm32l5xx_hal_lptim.c
@@ -2022,9 +2022,9 @@
/* Repetition counter underflowed (or contains zero) and the LPTIM counter
overflowed */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UPDATE) != RESET)
{
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UPDATE) != RESET)
{
/* Clear update event flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UPDATE);
@@ -2039,9 +2039,9 @@
}
/* Successful APB bus write to repetition counter register */
- if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
+ if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_REPOK) != RESET)
{
- if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
+ if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_REPOK) != RESET)
{
/* Clear successful APB bus write to repetition counter flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_REPOK);
@@ -2497,17 +2497,17 @@
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
- do
+ do
+ {
+ count--;
+ if (count == 0UL)
{
- count--;
- if (count == 0UL)
- {
- result = HAL_TIMEOUT;
- }
+ result = HAL_TIMEOUT;
}
- while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
+ }
+ while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
- return result;
+ return result;
}
/**
@@ -2535,17 +2535,17 @@
/* Save LPTIM source clock */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
- break;
- case LPTIM2_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
- break;
- case LPTIM3_BASE:
- tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
+ break;
+ case LPTIM2_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM2_SOURCE();
+ break;
+ case LPTIM3_BASE:
+ tmpclksource = __HAL_RCC_GET_LPTIM3_SOURCE();
+ break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -2559,20 +2559,20 @@
/*********** Reset LPTIM ***********/
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_FORCE_RESET();
- __HAL_RCC_LPTIM1_RELEASE_RESET();
- break;
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_FORCE_RESET();
- __HAL_RCC_LPTIM2_RELEASE_RESET();
- break;
- case LPTIM3_BASE:
- __HAL_RCC_LPTIM3_FORCE_RESET();
- __HAL_RCC_LPTIM3_RELEASE_RESET();
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_FORCE_RESET();
+ __HAL_RCC_LPTIM1_RELEASE_RESET();
+ break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_FORCE_RESET();
+ __HAL_RCC_LPTIM2_RELEASE_RESET();
+ break;
+ case LPTIM3_BASE:
+ __HAL_RCC_LPTIM3_FORCE_RESET();
+ __HAL_RCC_LPTIM3_RELEASE_RESET();
+ break;
+ default:
+ break;
}
/*********** Restore LPTIM Config ***********/
@@ -2581,17 +2581,17 @@
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
- break;
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1);
- break;
- case LPTIM3_BASE:
- __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_PCLK1);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
+ break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_CONFIG(RCC_LPTIM2CLKSOURCE_PCLK1);
+ break;
+ case LPTIM3_BASE:
+ __HAL_RCC_LPTIM3_CONFIG(RCC_LPTIM3CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -2640,17 +2640,17 @@
/* Restore LPTIM source kernel clock */
switch ((uint32_t)hlptim->Instance)
{
- case LPTIM1_BASE:
- __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
- break;
- case LPTIM2_BASE:
- __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
- break;
- case LPTIM3_BASE:
- __HAL_RCC_LPTIM3_CONFIG(tmpclksource);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
+ break;
+ case LPTIM2_BASE:
+ __HAL_RCC_LPTIM2_CONFIG(tmpclksource);
+ break;
+ case LPTIM3_BASE:
+ __HAL_RCC_LPTIM3_CONFIG(tmpclksource);
+ break;
+ default:
+ break;
}
}
diff --git a/Src/stm32l5xx_hal_mmc.c b/Src/stm32l5xx_hal_mmc.c
index b3eadc0..9128570 100644
--- a/Src/stm32l5xx_hal_mmc.c
+++ b/Src/stm32l5xx_hal_mmc.c
@@ -260,7 +260,27 @@
/** @addtogroup MMC_Private_Defines
* @{
*/
+#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U)
+#define MMC_VOLTAGE_RANGE MMC_LOW_VOLTAGE_RANGE
+#define MMC_EXT_CSD_PWR_CL_26_INDEX 201
+#define MMC_EXT_CSD_PWR_CL_52_INDEX 200
+#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238
+
+#define MMC_EXT_CSD_PWR_CL_26_POS 8
+#define MMC_EXT_CSD_PWR_CL_52_POS 0
+#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16
+#else
+#define MMC_VOLTAGE_RANGE MMC_HIGH_VOLTAGE_RANGE
+
+#define MMC_EXT_CSD_PWR_CL_26_INDEX 203
+#define MMC_EXT_CSD_PWR_CL_52_INDEX 202
+#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239
+
+#define MMC_EXT_CSD_PWR_CL_26_POS 24
+#define MMC_EXT_CSD_PWR_CL_52_POS 16
+#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24
+#endif
/**
* @}
*/
@@ -280,8 +300,8 @@
static void MMC_Read_IT(MMC_HandleTypeDef *hmmc);
static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state);
static uint32_t MMC_DDR_Mode(MMC_HandleTypeDef *hmmc, FunctionalState state);
-HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout);
-
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout);
+static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed);
/**
* @}
@@ -373,6 +393,15 @@
/* Initialize the MMC state */
hmmc->State = HAL_MMC_STATE_READY;
+ /* Configure bus width */
+ if (hmmc->Init.BusWide != SDMMC_BUS_WIDE_1B)
+ {
+ if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ }
+
return HAL_OK;
}
@@ -387,13 +416,23 @@
{
uint32_t errorstate;
MMC_InitTypeDef Init;
+ uint32_t sdmmc_clk;
/* Default SDMMC peripheral configuration for MMC card initialization */
Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING;
Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
Init.BusWide = SDMMC_BUS_WIDE_1B;
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDMMC_INIT_CLK_DIV;
+
+ /* Init Clock should be less or equal to 400Khz*/
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+ if (sdmmc_clk == 0U)
+ {
+ hmmc->State = HAL_MMC_STATE_READY;
+ hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+ return HAL_ERROR;
+ }
+ Init.ClockDiv = sdmmc_clk/(2U*400000U);
/* Initialize SDMMC peripheral interface with default configuration */
(void)SDMMC_Init(hmmc->Instance, Init);
@@ -401,6 +440,11 @@
/* Set Power State to ON */
(void)SDMMC_PowerState_ON(hmmc->Instance);
+ /* wait 74 Cycles: required power up waiting time before starting
+ the MMC initialization sequence */
+ sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv);
+ HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
+
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -2065,6 +2109,125 @@
}
/**
+ * @brief Returns information the information of the card which are stored on
+ * the Extended CSD register.
+ * @param hmmc Pointer to MMC handle
+ * @param pExtCSD Pointer to a memory area (512 bytes) that contains all
+ * Extended CSD register parameters
+ * @param Timeout Specify timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout)
+{
+ SDMMC_DataInitTypeDef config;
+ uint32_t errorstate;
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t count;
+ uint32_t *tmp_buf;
+
+ if(NULL == pExtCSD)
+ {
+ hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM;
+ return HAL_ERROR;
+ }
+
+ if(hmmc->State == HAL_MMC_STATE_READY)
+ {
+ hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
+
+ hmmc->State = HAL_MMC_STATE_BUSY;
+
+ /* Initialize data control register */
+ hmmc->Instance->DCTRL = 0;
+
+ /* Initiaize the destination pointer */
+ tmp_buf = pExtCSD;
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
+ config.DataTimeOut = SDMMC_DATATIMEOUT;
+ config.DataLength = 512;
+ config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
+ config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC;
+ config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
+ config.DPSM = SDMMC_DPSM_DISABLE;
+ (void)SDMMC_ConfigData(hmmc->Instance, &config);
+ __SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
+
+ /* Send ExtCSD Read command to Card */
+ errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0);
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= errorstate;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+
+ /* Poll on SDMMC flags */
+ while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND))
+ {
+ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF))
+ {
+ /* Read data from SDMMC Rx FIFO */
+ for(count = 0U; count < 8U; count++)
+ {
+ *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance);
+ tmp_buf++;
+ }
+ }
+
+ if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT;
+ hmmc->State= HAL_MMC_STATE_READY;
+ return HAL_TIMEOUT;
+ }
+ }
+
+ __SDMMC_CMDTRANS_DISABLE( hmmc->Instance);
+
+ /* Get error state */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS);
+ hmmc->State = HAL_MMC_STATE_READY;
+ }
+
+ return HAL_OK;
+}
+
+/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
* @param hmmc: Pointer to MMC handle
@@ -2085,71 +2248,88 @@
/* Check the parameters */
assert_param(IS_SDMMC_BUS_WIDE(WideMode));
- /* Chnage Satte */
+ /* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
- if(WideMode == SDMMC_BUS_WIDE_8B)
+ /* Check and update the power class if needed */
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U)
{
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
- }
- else if(WideMode == SDMMC_BUS_WIDE_4B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
- }
- else if(WideMode == SDMMC_BUS_WIDE_1B)
- {
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
- }
- else
- {
- /* WideMode is not a valid argument*/
- errorstate = HAL_MMC_ERROR_PARAM;
- }
-
- /* Check for switch error and violation of the trial number of sending CMD 13 */
- if(errorstate == HAL_MMC_ERROR_NONE)
- {
- /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
- count = SDMMC_MAX_TRIAL;
- do
+ if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) != 0U)
{
- errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- break;
- }
-
- /* Get command response */
- response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
- count--;
- }while(((response & 0x100U) == 0U) && (count != 0U));
-
- /* Check the status after the switch command execution */
- if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
- {
- /* Check the bit SWITCH_ERROR of the device status */
- if ((response & 0x80U) != 0U)
- {
- errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
- }
- else
- {
- /* Configure the SDMMC peripheral */
- Init.ClockEdge = hmmc->Init.ClockEdge;
- Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
- Init.BusWide = WideMode;
- Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
- Init.ClockDiv = hmmc->Init.ClockDiv;
- (void)SDMMC_Init(hmmc->Instance, Init);
- }
- }
- else if (count == 0U)
- {
- errorstate = SDMMC_ERROR_TIMEOUT;
+ errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DDR);
}
else
{
- /* Nothing to do */
+ errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_HIGH);
+ }
+ }
+ else
+ {
+ errorstate = MMC_PwrClassUpdate(hmmc, WideMode, SDMMC_SPEED_MODE_DEFAULT);
+ }
+
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if(WideMode == SDMMC_BUS_WIDE_8B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ }
+ else if(WideMode == SDMMC_BUS_WIDE_4B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ }
+ else if(WideMode == SDMMC_BUS_WIDE_1B)
+ {
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U);
+ }
+ else
+ {
+ /* WideMode is not a valid argument*/
+ errorstate = HAL_MMC_ERROR_PARAM;
+ }
+
+ /* Check for switch error and violation of the trial number of sending CMD 13 */
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ else
+ {
+ /* Configure the SDMMC peripheral */
+ Init = hmmc->Init;
+ Init.BusWide = WideMode;
+ (void)SDMMC_Init(hmmc->Instance, Init);
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
}
}
@@ -2188,14 +2368,13 @@
/* Check the parameters */
assert_param(IS_SDMMC_SPEED_MODE(SpeedMode));
+
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
- if(MMC_ReadExtCSD(hmmc, &device_type, 196, 0x0FFFFFFFU) != HAL_OK) /* Field DEVICE_TYPE [196] */
- {
- return HAL_ERROR;
- }
-
+ /* Field DEVICE_TYPE [196 = 49*4] of Extended CSD register */
+ device_type = (hmmc->Ext_CSD[49] & 0x000000FFU);
+
switch (SpeedMode)
{
case SDMMC_SPEED_MODE_AUTO:
@@ -2255,7 +2434,7 @@
{
/* High Speed DDR mode not allowed */
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
break;
}
@@ -2274,7 +2453,7 @@
{
/* High Speed mode not allowed */
hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
- status = HAL_ERROR;
+ status = HAL_ERROR;
}
break;
}
@@ -2771,40 +2950,19 @@
*/
HAL_StatusTypeDef HAL_MMC_GetSupportedSecRemovalType(MMC_HandleTypeDef *hmmc, uint32_t *SupportedSRT)
{
- uint32_t srt;
- uint32_t errorstate = SDMMC_ERROR_NONE;
-
/* Check the state of the driver */
if(hmmc->State == HAL_MMC_STATE_READY)
{
/* Change State */
hmmc->State = HAL_MMC_STATE_BUSY;
- /* Read the Extended CSD register and get expected value */
- if(MMC_ReadExtCSD(hmmc, &srt, 16, 0x0FFFFFFFU) == HAL_OK) /* Field SECURE_REMOVAL_TYPE [16] */
- {
- *SupportedSRT = (srt & 0x0000000FU); /* Bits [3:0] of field 16 */
- }
- else
- {
- errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
- }
+ /* Read field SECURE_REMOVAL_TYPE [16 = 4*4] of the Extended CSD register */
+ *SupportedSRT = (hmmc->Ext_CSD[4] & 0x0000000FU); /* Bits [3:0] of field 16 */
/* Change State */
hmmc->State = HAL_MMC_STATE_READY;
- /* Manage errors */
- if(errorstate != HAL_MMC_ERROR_NONE)
- {
- /* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
- hmmc->ErrorCode |= errorstate;
- return HAL_ERROR;
- }
- else
- {
- return HAL_OK;
- }
+ return HAL_OK;
}
else
{
@@ -2835,7 +2993,7 @@
{
HAL_MMC_CardCSDTypeDef CSD;
uint32_t errorstate;
- uint16_t mmc_rca = 1U;
+ uint16_t mmc_rca = 2U;
MMC_InitTypeDef Init;
/* Check the power State */
@@ -2860,9 +3018,9 @@
hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4);
}
- /* Send CMD3 SET_REL_ADDR with argument 0 */
+ /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */
/* MMC Card publishes its RCA. */
- errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca);
+ errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca);
if(errorstate != HAL_MMC_ERROR_NONE)
{
return errorstate;
@@ -2909,12 +3067,23 @@
hmmc->ErrorCode |= errorstate;
}
+
+ /* Get Extended CSD parameters */
+ if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK)
+ {
+ return hmmc->ErrorCode;
+ }
+
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ hmmc->ErrorCode |= errorstate;
+ }
+
/* Configure the SDMMC peripheral */
- Init.ClockEdge = hmmc->Init.ClockEdge;
- Init.ClockPowerSave = hmmc->Init.ClockPowerSave;
- Init.BusWide = SDMMC_BUS_WIDE_1B;
- Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl;
- Init.ClockDiv = hmmc->Init.ClockDiv;
+ Init = hmmc->Init;
+ Init.BusWide = SDMMC_BUS_WIDE_1B;
(void)SDMMC_Init(hmmc->Instance, Init);
/* All cards are initialized */
@@ -2948,8 +3117,8 @@
return HAL_MMC_ERROR_INVALID_VOLTRANGE;
}
- /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */
- errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE);
+ /* SEND CMD1 APP_CMD with voltage range as argument */
+ errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE);
if(errorstate != HAL_MMC_ERROR_NONE)
{
return HAL_MMC_ERROR_UNSUPPORTED_FEATURE;
@@ -3023,7 +3192,7 @@
* @param Timeout: Specify timeout value
* @retval HAL status
*/
-HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
+static HAL_StatusTypeDef MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout)
{
SDMMC_DataInitTypeDef config;
uint32_t errorstate;
@@ -3086,6 +3255,36 @@
}
}
+ /* Get error state */
+ if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR))
+ {
+ /* Clear all the static flags */
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS);
+ hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN;
+ hmmc->State = HAL_MMC_STATE_READY;
+ return HAL_ERROR;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+
/* While card is not ready for data and trial number for sending CMD13 is not exceeded */
errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16));
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -3183,14 +3382,22 @@
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE))
{
- /* Index : 185 - Value : 0 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
+ errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_DEFAULT);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 185 - Value : 0 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90000U);
+ }
}
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) == 0U) && (state != DISABLE))
{
- /* Index : 185 - Value : 1 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
+ errorstate = MMC_PwrClassUpdate(hmmc, (hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS), SDMMC_SPEED_MODE_HIGH);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 185 - Value : 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B90100U);
+ }
}
if(errorstate == HAL_MMC_ERROR_NONE)
@@ -3270,27 +3477,43 @@
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
- /* Index : 183 - Value : 1 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_HIGH);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 1 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U);
+ }
}
else
{
- /* Index : 183 - Value : 2 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_HIGH);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 2 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U);
+ }
}
}
-
+
if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_DDR) == 0U) && (state != DISABLE))
{
if ((hmmc->Instance->CLKCR & SDMMC_CLKCR_WIDBUS_0) != 0U)
{
- /* Index : 183 - Value : 5 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_4B, SDMMC_SPEED_MODE_DDR);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 5 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70500U);
+ }
}
else
{
- /* Index : 183 - Value : 6 */
- errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
+ errorstate = MMC_PwrClassUpdate(hmmc, SDMMC_BUS_WIDE_8B, SDMMC_SPEED_MODE_DDR);
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* Index : 183 - Value : 6 */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70600U);
+ }
}
}
@@ -3322,16 +3545,13 @@
else
{
/* Configure DDR mode */
- if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ if (state == DISABLE)
{
- if (state == DISABLE)
- {
- CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
- }
- else
- {
- SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
- }
+ CLEAR_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
+ }
+ else
+ {
+ SET_BIT(hmmc->Instance->CLKCR, SDMMC_CLKCR_DDR);
}
}
}
@@ -3349,6 +3569,106 @@
}
/**
+ * @brief Update the power class of the device.
+ * @param hmmc MMC handle
+ * @param Wide Wide of MMC bus
+ * @param Speed Speed of the MMC bus
+ * @retval MMC Card error state
+ */
+static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint32_t Speed)
+{
+ uint32_t count;
+ uint32_t response = 0U;
+ uint32_t errorstate = HAL_MMC_ERROR_NONE;
+ uint32_t power_class, supported_pwr_class;
+
+ if((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B))
+ {
+ power_class = 0U; /* Default value after power-on or software reset */
+
+ /* Read the PowerClass field of the Extended CSD register */
+ if(MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */
+ {
+ errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR;
+ }
+ else
+ {
+ power_class = ((power_class >> 24U) & 0x000000FFU);
+ }
+
+ /* Get the supported PowerClass field of the Extended CSD register */
+ if (Speed == SDMMC_SPEED_MODE_DDR)
+ {
+ /* Field PWR_CL_DDR_52_xxx [238 or 239] */
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_DDR_52_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_DDR_52_POS) & 0x000000FFU);
+ }
+ else if (Speed == SDMMC_SPEED_MODE_HIGH)
+ {
+ /* Field PWR_CL_52_xxx [200 or 202] */
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_52_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_52_POS) & 0x000000FFU);
+ }
+ else
+ {
+ /* Field PWR_CL_26_xxx [201 or 203] */
+ supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & 0x000000FFU);
+ }
+
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ if(Wide == SDMMC_BUS_WIDE_8B)
+ {
+ /* Bit [7:4] : power class for 8-bits bus configuration - Bit [3:0] : power class for 4-bits bus configuration */
+ supported_pwr_class = (supported_pwr_class >> 4U);
+ }
+
+ if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU))
+ {
+ /* Need to change current power class */
+ errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U)));
+
+ if(errorstate == HAL_MMC_ERROR_NONE)
+ {
+ /* While card is not ready for data and trial number for sending CMD13 is not exceeded */
+ count = SDMMC_MAX_TRIAL;
+ do
+ {
+ errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U));
+ if(errorstate != HAL_MMC_ERROR_NONE)
+ {
+ break;
+ }
+
+ /* Get command response */
+ response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1);
+ count--;
+ }while(((response & 0x100U) == 0U) && (count != 0U));
+
+ /* Check the status after the switch command execution */
+ if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE))
+ {
+ /* Check the bit SWITCH_ERROR of the device status */
+ if ((response & 0x80U) != 0U)
+ {
+ errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE;
+ }
+ }
+ else if (count == 0U)
+ {
+ errorstate = SDMMC_ERROR_TIMEOUT;
+ }
+ else
+ {
+ /* Nothing to do */
+ }
+ }
+ }
+ }
+ }
+
+ return errorstate;
+}
+
+/**
* @brief Read DMA Buffer 0 Transfer completed callbacks
* @param hmmc: MMC handle
* @retval None
diff --git a/Src/stm32l5xx_hal_mmc_ex.c b/Src/stm32l5xx_hal_mmc_ex.c
index d83a742..b8fd8f2 100644
--- a/Src/stm32l5xx_hal_mmc_ex.c
+++ b/Src/stm32l5xx_hal_mmc_ex.c
@@ -3,10 +3,10 @@
* @file stm32l5xx_hal_mmc_ex.c
* @author MCD Application Team
* @brief MMC card Extended HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
* + Extended features functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -16,7 +16,7 @@
(+) Configure Buffer0 and Buffer1 start address and Buffer size using HAL_MMCEx_ConfigDMAMultiBuffer() function.
(+) Start Read and Write for multibuffer mode using HAL_MMCEx_ReadBlocksDMAMultiBuffer() and HAL_MMCEx_WriteBlocksDMAMultiBuffer() functions.
-
+
@endverbatim
******************************************************************************
* @attention
@@ -30,7 +30,7 @@
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32l5xx_hal.h"
@@ -57,17 +57,19 @@
* @{
*/
+
+
/** @addtogroup MMCEx_Exported_Functions_Group1
- * @brief Multibuffer functions
+ * @brief Multibuffer functions
*
-@verbatim
+@verbatim
==============================================================================
##### Multibuffer functions #####
==============================================================================
- [..]
- This section provides functions allowing to configure the multibuffer mode and start read and write
+ [..]
+ This section provides functions allowing to configure the multibuffer mode and start read and write
multibuffer mode for MMC HAL driver.
-
+
@endverbatim
* @{
*/
@@ -75,8 +77,8 @@
/**
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
* @param hmmc: MMC handle
- * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
- * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
+ * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transferred data
+ * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transferred data
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
@@ -87,7 +89,7 @@
hmmc->Instance->IDMABASE0= (uint32_t) pDataBuffer0 ;
hmmc->Instance->IDMABASE1= (uint32_t) pDataBuffer1 ;
hmmc->Instance->IDMABSIZE= (uint32_t) (MMC_BLOCKSIZE * BufferSize);
-
+
return HAL_OK;
}
else
@@ -95,12 +97,12 @@
return HAL_BUSY;
}
}
-
+
/**
* @brief Reads block(s) from a specified address in a card. The received Data will be stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
* @param hmmc: MMC handle
- * @param BlockAdd: Block Address from where data is to be read
+ * @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
@@ -110,7 +112,7 @@
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t errorstate;
uint32_t add = BlockAdd;
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
@@ -118,18 +120,19 @@
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
+
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
-
+
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
hmmc->State = HAL_MMC_STATE_BUSY;
@@ -137,8 +140,8 @@
{
add *= 512U;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
@@ -146,16 +149,16 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
-
+
hmmc->Instance->DCTRL |= SDMMC_DCTRL_FIFORST;
-
+
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
-
- hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
+ hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
/* Read Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
+
/* Read Multi Block command */
errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -164,7 +167,7 @@
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
-
+
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
@@ -173,14 +176,14 @@
{
return HAL_BUSY;
}
-
+
}
/**
- * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
+ * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_MMCEx_ConfigDMAMultiBuffer before call this function.
* @param hmmc: MMC handle
- * @param BlockAdd: Block Address from where data is to be read
+ * @param BlockAdd: Block Address from where data is to be read
* @param NumberOfBlocks: Total number of blocks to read
* @retval HAL status
*/
@@ -190,7 +193,7 @@
uint32_t errorstate;
uint32_t DmaBase0_reg, DmaBase1_reg;
uint32_t add = BlockAdd;
-
+
if(hmmc->State == HAL_MMC_STATE_READY)
{
if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr))
@@ -198,28 +201,29 @@
hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
DmaBase0_reg = hmmc->Instance->IDMABASE0;
DmaBase1_reg = hmmc->Instance->IDMABASE1;
+
if ((hmmc->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hmmc->ErrorCode = HAL_MMC_ERROR_ADDR_OUT_OF_RANGE;
return HAL_ERROR;
}
-
+
/* Initialize data control register */
hmmc->Instance->DCTRL = 0;
-
+
hmmc->ErrorCode = HAL_MMC_ERROR_NONE;
-
+
hmmc->State = HAL_MMC_STATE_BUSY;
if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD)
{
add *= 512U;
}
-
- /* Configure the MMC DPSM (Data Path State Machine) */
+
+ /* Configure the MMC DPSM (Data Path State Machine) */
config.DataTimeOut = SDMMC_DATATIMEOUT;
config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks;
config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B;
@@ -227,14 +231,14 @@
config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK;
config.DPSM = SDMMC_DPSM_DISABLE;
(void)SDMMC_ConfigData(hmmc->Instance, &config);
-
+
__SDMMC_CMDTRANS_ENABLE( hmmc->Instance);
-
- hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
-
+
+ hmmc->Instance->IDMACTRL = SDMMC_ENABLE_IDMA_DOUBLE_BUFF0;
+
/* Write Blocks in DMA mode */
hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA);
-
+
/* Write Multi Block command */
errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -243,7 +247,7 @@
hmmc->ErrorCode |= errorstate;
return HAL_ERROR;
}
-
+
__HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC));
return HAL_OK;
@@ -251,18 +255,18 @@
else
{
return HAL_BUSY;
- }
+ }
}
-
+
/**
* @brief Change the DMA Buffer0 or Buffer1 address on the fly.
* @param hmmc: pointer to a MMC_HandleTypeDef structure.
- * @param Buffer: the buffer to be changed, This parameter can be one of
+ * @param Buffer: the buffer to be changed, This parameter can be one of
* the following values: MMC_DMA_BUFFER0 or MMC_DMA_BUFFER1
* @param pDataBuffer: The new address
* @note The BUFFER0 address can be changed only when the current transfer use
- * BUFFER1 and the BUFFER1 address can be changed only when the current
+ * BUFFER1 and the BUFFER1 address can be changed only when the current
* transfer use BUFFER0.
* @retval HAL status
*/
@@ -278,7 +282,7 @@
/* change the memory1 address */
hmmc->Instance->IDMABASE1 = (uint32_t)pDataBuffer;
}
-
+
return HAL_OK;
}
diff --git a/Src/stm32l5xx_hal_nand.c b/Src/stm32l5xx_hal_nand.c
index fdbad30..19a5fb8 100644
--- a/Src/stm32l5xx_hal_nand.c
+++ b/Src/stm32l5xx_hal_nand.c
@@ -155,7 +155,8 @@
* @param AttSpace_Timing pointer to Attribute space timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
+ FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
{
/* Check the NAND handle state */
if (hnand == NULL)
@@ -169,7 +170,7 @@
hnand->Lock = HAL_UNLOCKED;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- if(hnand->MspInitCallback == NULL)
+ if (hnand->MspInitCallback == NULL)
{
hnand->MspInitCallback = HAL_NAND_MspInit;
}
@@ -194,7 +195,7 @@
/* Enable the NAND device */
__FMC_NAND_ENABLE(hnand->Instance);
-
+
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@@ -210,7 +211,7 @@
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
{
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
- if(hnand->MspDeInitCallback == NULL)
+ if (hnand->MspDeInitCallback == NULL)
{
hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
}
@@ -272,7 +273,7 @@
* @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
-*/
+ */
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
{
/* Check NAND interrupt Rising edge flag */
@@ -513,12 +514,13 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead;
- uint8_t * buff = pBuffer;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -667,12 +669,13 @@
* @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead;
- uint16_t * buff = pBuffer;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -820,12 +823,13 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
- uint8_t * buff = pBuffer;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -969,12 +973,13 @@
* @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
+ uint32_t NumPageToWrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
- uint16_t * buff = pBuffer;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1117,13 +1122,14 @@
* @param pBuffer pointer to source buffer to write
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
+ */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
+ uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
- uint8_t * buff = pBuffer;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1277,13 +1283,14 @@
* @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
* @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
-*/
-HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
+ */
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
- uint16_t * buff = pBuffer;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1438,12 +1445,13 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
- uint8_t * buff = pBuffer;
+ uint8_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1596,12 +1604,13 @@
* @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
+ uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
uint32_t index;
uint32_t tickstart;
uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
- uint16_t * buff = pBuffer;
+ uint16_t *buff = pBuffer;
/* Check the NAND controller state */
if (hnand->State == HAL_NAND_STATE_BUSY)
@@ -1849,11 +1858,12 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
+ pNAND_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -1861,39 +1871,39 @@
/* Process locked */
__HAL_LOCK(hnand);
- if(hnand->State == HAL_NAND_STATE_READY)
+ if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = pCallback;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = pCallback;
- break;
- case HAL_NAND_IT_CB_ID :
- hnand->ItCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hnand->State == HAL_NAND_STATE_RESET)
+ else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = pCallback;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = pCallback;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1918,46 +1928,46 @@
* @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hnand);
- if(hnand->State == HAL_NAND_STATE_READY)
+ if (hnand->State == HAL_NAND_STATE_READY)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = HAL_NAND_MspInit;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
- break;
- case HAL_NAND_IT_CB_ID :
- hnand->ItCallback = HAL_NAND_ITCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ case HAL_NAND_IT_CB_ID :
+ hnand->ItCallback = HAL_NAND_ITCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(hnand->State == HAL_NAND_STATE_RESET)
+ else if (hnand->State == HAL_NAND_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_NAND_MSP_INIT_CB_ID :
- hnand->MspInitCallback = HAL_NAND_MspInit;
- break;
- case HAL_NAND_MSP_DEINIT_CB_ID :
- hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NAND_MSP_INIT_CB_ID :
+ hnand->MspInitCallback = HAL_NAND_MspInit;
+ break;
+ case HAL_NAND_MSP_DEINIT_CB_ID :
+ hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1977,8 +1987,8 @@
*/
/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### NAND Control functions #####
@@ -2098,8 +2108,8 @@
/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### NAND State functions #####
@@ -2136,7 +2146,7 @@
UNUSED(hnand);
/* Identify the device address */
- DeviceAddress = NAND_DEVICE;
+ DeviceAddress = NAND_DEVICE;
/* Send Read status operation command */
*(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
diff --git a/Src/stm32l5xx_hal_nor.c b/Src/stm32l5xx_hal_nor.c
index 240ab4d..9bcbfd5 100644
--- a/Src/stm32l5xx_hal_nor.c
+++ b/Src/stm32l5xx_hal_nor.c
@@ -150,9 +150,35 @@
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29
#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30
+#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF
+#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040
+#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8
+#define NOR_CMD_CONFIRM (uint16_t)0x00D0
+#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020
+#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060
+#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070
+#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050
+
/* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010
#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020
#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040
+#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080
+
+/* Address of the primary command set */
+#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013
+
+/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
+#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */
+#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */
+#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */
+#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */
+#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */
+#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */
+#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */
+#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */
/**
* @}
@@ -199,8 +225,11 @@
* @param ExtTiming pointer to NOR extended mode timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
+ uint32_t deviceaddress;
+
/* Check the NOR handle parameter */
if (hnor == NULL)
{
@@ -213,7 +242,7 @@
hnor->Lock = HAL_UNLOCKED;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- if(hnor->MspInitCallback == NULL)
+ if (hnor->MspInitCallback == NULL)
{
hnor->MspInitCallback = HAL_NOR_MspInit;
}
@@ -251,7 +280,29 @@
/* Initialize the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
- return HAL_OK;
+ /* Select the NOR device address */
+ if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS1;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS2;
+ }
+ else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
+ {
+ deviceaddress = NOR_MEMORY_ADRESS3;
+ }
+ else /* FMC_NORSRAM_BANK4 */
+ {
+ deviceaddress = NOR_MEMORY_ADRESS4;
+ }
+
+ /* Get the value of the command set */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+ hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
+
+ return HAL_NOR_ReturnToReadMode(hnor);
}
/**
@@ -263,7 +314,7 @@
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
{
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
- if(hnor->MspDeInitCallback == NULL)
+ if (hnor->MspDeInitCallback == NULL)
{
hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
}
@@ -366,6 +417,7 @@
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -400,15 +452,30 @@
}
/* Send read ID command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
- /* Read the NOR IDs */
- pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
- pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
- pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
- pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+ if (status != HAL_ERROR)
+ {
+ /* Read the NOR IDs */
+ pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+ pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
+ pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
+ pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
+ }
/* Check the NOR controller state */
hnor->State = state;
@@ -421,7 +488,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -434,6 +501,7 @@
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -467,7 +535,19 @@
deviceaddress = NOR_MEMORY_ADRESS4;
}
- NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
/* Check the NOR controller state */
hnor->State = state;
@@ -480,7 +560,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -495,6 +575,7 @@
{
uint32_t deviceaddress;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -529,12 +610,27 @@
}
/* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
- /* Read the data */
- *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+ if (status != HAL_ERROR)
+ {
+ /* Read the data */
+ *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+ }
/* Check the NOR controller state */
hnor->State = state;
@@ -547,7 +643,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -561,6 +657,7 @@
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@@ -594,12 +691,27 @@
}
/* Send program data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
- /* Write the data */
- NOR_WRITE(pAddress, *pData);
+ if (status != HAL_ERROR)
+ {
+ /* Write the data */
+ NOR_WRITE(pAddress, *pData);
+ }
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -612,7 +724,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -624,11 +736,13 @@
* @param uwBufferSize number of Half word to read.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize)
{
uint32_t deviceaddress, size = uwBufferSize, address = uwAddress;
uint16_t *data = pData;
HAL_NOR_StateTypeDef state;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
state = hnor->State;
@@ -663,17 +777,32 @@
}
/* Send read data command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
-
- /* Read buffer */
- while (size > 0U)
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- *data = *(__IO uint16_t *)address;
- data++;
- address += 2U;
- size--;
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
+
+ if (status != HAL_ERROR)
+ {
+ /* Read buffer */
+ while (size > 0U)
+ {
+ *data = *(__IO uint16_t *)address;
+ data++;
+ address += 2U;
+ size--;
+ }
}
/* Check the NOR controller state */
@@ -687,7 +816,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -699,12 +828,14 @@
* @param uwBufferSize Size of the buffer to write
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+ uint32_t uwBufferSize)
{
uint16_t *p_currentaddress;
const uint16_t *p_endaddress;
uint16_t *data = pData;
- uint32_t lastloadedaddress, deviceaddress;
+ uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@@ -738,31 +869,51 @@
}
/* Initialize variables */
- p_currentaddress = (uint16_t *)(uwAddress);
- p_endaddress = (const uint16_t *)(uwAddress + (uwBufferSize - 1U));
- lastloadedaddress = uwAddress;
+ p_currentaddress = (uint16_t *)(deviceaddress + uwAddress);
+ p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U*(uwBufferSize - 1U)));
- /* Issue unlock command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-
- /* Write Buffer Load Command */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uint16_t)(uwBufferSize - 1U));
-
- /* Load Data into NOR Buffer */
- while (p_currentaddress <= p_endaddress)
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- /* Store last loaded address & data value (for polling) */
- lastloadedaddress = (uint32_t)p_currentaddress;
+ /* Issue unlock command sequence */
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(p_currentaddress, *data);
-
- data++;
- p_currentaddress ++;
+ /* Write Buffer Load Command */
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+ NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ /* Write Buffer Load Command */
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
+ NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
}
- NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+ if (status != HAL_ERROR)
+ {
+ /* Load Data into NOR Buffer */
+ while (p_currentaddress <= p_endaddress)
+ {
+ NOR_WRITE(p_currentaddress, *data);
+
+ data++;
+ p_currentaddress ++;
+ }
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+ }
+ else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
+ {
+ NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
+ }
+ }
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -775,7 +926,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
@@ -790,6 +941,7 @@
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
/* Check the NOR controller state */
if (hnor->State == HAL_NOR_STATE_BUSY)
@@ -823,12 +975,30 @@
}
/* Send block erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
+ NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -841,7 +1011,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
@@ -855,6 +1025,7 @@
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
{
uint32_t deviceaddress;
+ HAL_StatusTypeDef status = HAL_OK;
UNUSED(Address);
/* Check the NOR controller state */
@@ -889,12 +1060,23 @@
}
/* Send NOR chip erase command sequence */
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
- NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+ {
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+ NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+ }
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_ERROR;
+ }
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@@ -907,7 +1089,7 @@
return HAL_ERROR;
}
- return HAL_OK;
+ return status;
}
/**
@@ -989,12 +1171,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+ pNOR_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -1003,20 +1186,20 @@
__HAL_LOCK(hnor);
state = hnor->State;
- if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_NOR_MSP_INIT_CB_ID :
- hnor->MspInitCallback = pCallback;
- break;
- case HAL_NOR_MSP_DEINIT_CB_ID :
- hnor->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = pCallback;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1040,7 +1223,7 @@
* @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_NOR_StateTypeDef state;
@@ -1049,20 +1232,20 @@
__HAL_LOCK(hnor);
state = hnor->State;
- if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+ if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_NOR_MSP_INIT_CB_ID :
- hnor->MspInitCallback = HAL_NOR_MspInit;
- break;
- case HAL_NOR_MSP_DEINIT_CB_ID :
- hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_NOR_MSP_INIT_CB_ID :
+ hnor->MspInitCallback = HAL_NOR_MspInit;
+ break;
+ case HAL_NOR_MSP_DEINIT_CB_ID :
+ hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -1082,8 +1265,8 @@
*/
/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### NOR Control functions #####
@@ -1105,7 +1288,7 @@
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_PROTECTED)
+ if (hnor->State == HAL_NOR_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -1139,7 +1322,7 @@
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
{
/* Check the NOR controller state */
- if(hnor->State == HAL_NOR_STATE_READY)
+ if (hnor->State == HAL_NOR_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hnor);
@@ -1169,8 +1352,8 @@
*/
/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### NOR State functions #####
@@ -1216,45 +1399,84 @@
/* Get tick */
tickstart = HAL_GetTick();
- while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+
+ if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
{
- /* Check for the Timeout */
- if (Timeout != HAL_MAX_DELAY)
+ while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
{
- if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
{
- status = HAL_NOR_STATUS_TIMEOUT;
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ status = HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+
+ /* Read NOR status register (DQ6 and DQ5) */
+ tmpSR1 = *(__IO uint16_t *)Address;
+ tmpSR2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS ;
+ }
+
+ if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ status = HAL_NOR_STATUS_ONGOING;
+ }
+
+ tmpSR1 = *(__IO uint16_t *)Address;
+ tmpSR2 = *(__IO uint16_t *)Address;
+
+ /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
+ if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ {
+ return HAL_NOR_STATUS_SUCCESS;
+ }
+ if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ {
+ return HAL_NOR_STATUS_ERROR;
}
}
-
- /* Read NOR status register (DQ6 and DQ5) */
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ }
+ else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+ {
+ do
{
- return HAL_NOR_STATUS_SUCCESS ;
- }
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ tmpSR2 = *(__IO uint16_t*)(Address);
- if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
- {
- status = HAL_NOR_STATUS_ONGOING;
- }
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ return HAL_NOR_STATUS_TIMEOUT;
+ }
+ }
+ } while ((tmpSR2 & NOR_MASK_STATUS_DQ7) == 0U);
- tmpSR1 = *(__IO uint16_t *)Address;
- tmpSR2 = *(__IO uint16_t *)Address;
-
- /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
- if ((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6))
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ tmpSR1 = *(__IO uint16_t*)(Address);
+ if((tmpSR1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
{
- return HAL_NOR_STATUS_SUCCESS;
+ /* Clear the Status Register */
+ NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+ status = HAL_NOR_STATUS_ERROR;
}
- if ((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+ else
{
- return HAL_NOR_STATUS_ERROR;
+ status = HAL_NOR_STATUS_SUCCESS;
}
}
+ else
+ {
+ /* Primary command set not supported by the driver */
+ status = HAL_NOR_STATUS_ERROR;
+ }
/* Return the operation status */
return status;
diff --git a/Src/stm32l5xx_hal_opamp.c b/Src/stm32l5xx_hal_opamp.c
index f91de6e..7733ee0 100644
--- a/Src/stm32l5xx_hal_opamp.c
+++ b/Src/stm32l5xx_hal_opamp.c
@@ -273,7 +273,7 @@
* parameters in the OPAMP_InitTypeDef and initialize the associated handle.
* @note If the selected opamp is locked, initialization can't be performed.
* To unlock the configuration, perform a system reset.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
@@ -306,15 +306,15 @@
assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));
+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
if(hopamp->State == HAL_OPAMP_STATE_RESET)
{
-#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
if(hopamp->MspInitCallback == NULL)
{
hopamp->MspInitCallback = HAL_OPAMP_MspInit;
}
-#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
}
+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
if ((hopamp->Init.Mode) == OPAMP_STANDALONE_MODE)
{
@@ -437,7 +437,7 @@
* @brief DeInitialize the OPAMP peripheral.
* @note Deinitialization can be performed if the OPAMP configuration is locked.
* (the lock is SW in L5)
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
@@ -487,7 +487,7 @@
/**
* @brief Initialize the OPAMP MSP.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval None
*/
__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
@@ -502,7 +502,7 @@
/**
* @brief DeInitialize OPAMP MSP.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval None
*/
__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
@@ -537,7 +537,7 @@
/**
* @brief Start the OPAMP.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
@@ -580,7 +580,7 @@
/**
* @brief Stop the OPAMP.
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
@@ -668,8 +668,7 @@
assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
- /* Save OPAMP mode as */
- /* the calibration is not working in PGA mode */
+ /* The calibration is not working in PGA mode */
opampmode = READ_BIT(hopamp->Instance->CSR,OPAMP_CSR_OPAMODE);
/* Use of standalone mode */
@@ -862,7 +861,7 @@
* @note On STM32L5, HAL OPAMP lock is software lock only (in
* contrast of hardware lock available on some other STM32
* devices).
- * @param hopamp: OPAMP handle
+ * @param hopamp OPAMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
diff --git a/Src/stm32l5xx_hal_ospi.c b/Src/stm32l5xx_hal_ospi.c
index 06e03cc..8ad6281 100644
--- a/Src/stm32l5xx_hal_ospi.c
+++ b/Src/stm32l5xx_hal_ospi.c
@@ -23,179 +23,195 @@
*** Initialization ***
======================
[..]
- (#) As prerequisite, fill in the HAL_OSPI_MspInit() :
- (++) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE().
- (++) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET().
- (++) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
- (++) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init().
- (++) If interrupt or DMA mode is used, enable and configure OctoSPI global
- interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (++) If DMA mode is used, enable the clocks for the OctoSPI DMA channel
- with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
- link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure
- DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
- (#) Configure the fifo threshold, the dual-quad mode, the memory type, the
- device size, the CS high time, the free running clock, the clock mode,
- the wrap size, the clock prescaler, the sample shifting, the hold delay
- and the CS boundary using the HAL_OSPI_Init() function.
- (#) When using Hyperbus, configure the RW recovery time, the access time,
- the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
- function.
+ As prerequisite, fill in the HAL_OSPI_MspInit() :
+ (+) Enable OctoSPI clock interface with __HAL_RCC_OSPIx_CLK_ENABLE().
+ (+) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET().
+ (+) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
+ (+) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init().
+ (+) If interrupt or DMA mode is used, enable and configure OctoSPI global
+ interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ (+) If DMA mode is used, enable the clocks for the OctoSPI DMA channel
+ with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
+ link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure
+ DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
+ [..]
+ Configure the fifo threshold, the dual-quad mode, the memory type, the
+ device size, the CS high time, the free running clock, the clock mode,
+ the wrap size, the clock prescaler, the sample shifting, the hold delay
+ and the CS boundary using the HAL_OSPI_Init() function.
+ [..]
+ When using Hyperbus, configure the RW recovery time, the access time,
+ the write latency and the latency mode unsing the HAL_OSPI_HyperbusCfg()
+ function.
*** Indirect functional mode ***
================================
[..]
- (#) In regular mode, configure the command sequence using the HAL_OSPI_Command()
- or HAL_OSPI_Command_IT() functions :
- (++) Instruction phase : the mode used and if present the size, the instruction
- opcode and the DTR mode.
- (++) Address phase : the mode used and if present the size, the address
- value and the DTR mode.
- (++) Alternate-bytes phase : the mode used and if present the size, the
- alternate bytes values and the DTR mode.
- (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
- (++) Data phase : the mode used and if present the number of bytes and the DTR mode.
- (++) Data strobe (DQS) mode : the activation (or not) of this mode
- (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
- (++) Flash identifier : in dual-quad mode, indicates which flash is concerned
- (++) Operation type : always common configuration
- (#) In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd()
- function :
- (++) Address space : indicate if the access will be done in register or memory
- (++) Address size
- (++) Number of data
- (++) Data strobe (DQS) mode : the activation (or not) of this mode
- (#) If no data is required for the command (only for regular mode, not for
- Hyperbus mode), it is sent directly to the memory :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete.
- (#) For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or
- HAL_OSPI_Transmit_IT() after the command configuration :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
- is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and
- HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
- (#) For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or
- HAL_OSPI_Receive_IT() after the command configuration :
- (++) In polling mode, the output of the function is done when the transfer is complete.
- (++) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
- is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
- (++) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and
- HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
+ In regular mode, configure the command sequence using the HAL_OSPI_Command()
+ or HAL_OSPI_Command_IT() functions :
+ (+) Instruction phase : the mode used and if present the size, the instruction
+ opcode and the DTR mode.
+ (+) Address phase : the mode used and if present the size, the address
+ value and the DTR mode.
+ (+) Alternate-bytes phase : the mode used and if present the size, the
+ alternate bytes values and the DTR mode.
+ (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
+ (+) Data phase : the mode used and if present the number of bytes and the DTR mode.
+ (+) Data strobe (DQS) mode : the activation (or not) of this mode
+ (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
+ (+) Flash identifier : in dual-quad mode, indicates which flash is concerned
+ (+) Operation type : always common configuration
+ [..]
+ In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd()
+ function :
+ (+) Address space : indicate if the access will be done in register or memory
+ (+) Address size
+ (+) Number of data
+ (+) Data strobe (DQS) mode : the activation (or not) of this mode
+ [..]
+ If no data is required for the command (only for regular mode, not for
+ Hyperbus mode), it is sent directly to the memory :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete.
+ [..]
+ For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or
+ HAL_OSPI_Transmit_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and
+ HAL_OSPI_TxCpltCallback() will be called when the transfer is complete.
+ [..]
+ For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or
+ HAL_OSPI_Receive_IT() after the command configuration :
+ (+) In polling mode, the output of the function is done when the transfer is complete.
+ (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold
+ is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
+ (+) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and
+ HAL_OSPI_RxCpltCallback() will be called when the transfer is complete.
*** Auto-polling functional mode ***
====================================
[..]
- (#) Configure the command sequence by the same way than the indirect mode
- (#) Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling()
- or HAL_OSPI_AutoPolling_IT() functions :
- (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
- the polling interval and the automatic stop activation.
- (#) After the configuration :
- (++) In polling mode, the output of the function is done when the status match is reached. The
- automatic stop is activated to avoid an infinite loop.
- (++) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached.
+ Configure the command sequence by the same way than the indirect mode
+ [..]
+ Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling()
+ or HAL_OSPI_AutoPolling_IT() functions :
+ (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
+ the polling interval and the automatic stop activation.
+ [..]
+ After the configuration :
+ (+) In polling mode, the output of the function is done when the status match is reached. The
+ automatic stop is activated to avoid an infinite loop.
+ (+) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached.
*** Memory-mapped functional mode ***
=====================================
[..]
- (#) Configure the command sequence by the same way than the indirect mode except
- for the operation type in regular mode :
- (++) Operation type equals to read configuration : the command configuration
- applies to read access in memory-mapped mode
- (++) Operation type equals to write configuration : the command configuration
- applies to write access in memory-mapped mode
- (++) Both read and write configuration should be performed before activating
- memory-mapped mode
- (#) Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped()
- functions :
- (++) The timeout activation and the timeout period.
- (#) After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on
- the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires.
+ Configure the command sequence by the same way than the indirect mode except
+ for the operation type in regular mode :
+ (+) Operation type equals to read configuration : the command configuration
+ applies to read access in memory-mapped mode
+ (+) Operation type equals to write configuration : the command configuration
+ applies to write access in memory-mapped mode
+ (+) Both read and write configuration should be performed before activating
+ memory-mapped mode
+ [..]
+ Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped()
+ functions :
+ (+) The timeout activation and the timeout period.
+ [..]
+ After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on
+ the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires.
*** Errors management and abort functionality ***
=================================================
[..]
- (#) HAL_OSPI_GetError() function gives the error raised during the last operation.
- (#) HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and
- flushes the fifo :
- (++) In polling mode, the output of the function is done when the transfer
- complete bit is set and the busy bit cleared.
- (++) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when
- the transfer complete bit is set.
+ HAL_OSPI_GetError() function gives the error raised during the last operation.
+ [..]
+ HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and
+ flushes the fifo :
+ (+) In polling mode, the output of the function is done when the transfer
+ complete bit is set and the busy bit cleared.
+ (+) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when
+ the transfer complete bit is set.
*** Control functions ***
=========================
[..]
- (#) HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver.
- (#) HAL_OSPI_SetTimeout() function configures the timeout value used in the driver.
- (#) HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral.
- (#) HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
-
- *** IO manager configuration functions ***
- ==========================================
+ HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver.
[..]
- (#) HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance.
+ HAL_OSPI_SetTimeout() function configures the timeout value used in the driver.
+ [..]
+ HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral.
+ [..]
+ HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
*** Callback registration ***
=============================================
[..]
- The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1
- allows the user to configure dynamically the driver callbacks.
+ The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
- Use Functions @ref HAL_OSPI_RegisterCallback() to register a user callback,
- it allows to register following callbacks:
- (+) ErrorCallback : callback when error occurs.
- (+) AbortCpltCallback : callback when abort is completed.
- (+) FifoThresholdCallback : callback when the fifo threshold is reached.
- (+) CmdCpltCallback : callback when a command without data is completed.
- (+) RxCpltCallback : callback when a reception transfer is completed.
- (+) TxCpltCallback : callback when a transmission transfer is completed.
- (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
- (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
- (+) StatusMatchCallback : callback when a status match occurs.
- (+) TimeOutCallback : callback when the timeout perioed expires.
- (+) MspInitCallback : OSPI MspInit.
- (+) MspDeInitCallback : OSPI MspDeInit.
- This function takes as parameters the HAL peripheral handle, the Callback ID
- and a pointer to the user callback function.
+ [..]
+ Use function HAL_OSPI_RegisterCallback() to register a user callback,
+ it allows to register following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : OSPI MspInit.
+ (+) MspDeInitCallback : OSPI MspDeInit.
+ [..]
+ This function takes as parameters the HAL peripheral handle, the Callback ID
+ and a pointer to the user callback function.
- Use function @ref HAL_OSPI_UnRegisterCallback() to reset a callback to the default
- weak (surcharged) function. It allows to reset following callbacks:
- (+) ErrorCallback : callback when error occurs.
- (+) AbortCpltCallback : callback when abort is completed.
- (+) FifoThresholdCallback : callback when the fifo threshold is reached.
- (+) CmdCpltCallback : callback when a command without data is completed.
- (+) RxCpltCallback : callback when a reception transfer is completed.
- (+) TxCpltCallback : callback when a transmission transfer is completed.
- (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
- (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
- (+) StatusMatchCallback : callback when a status match occurs.
- (+) TimeOutCallback : callback when the timeout perioed expires.
- (+) MspInitCallback : OSPI MspInit.
- (+) MspDeInitCallback : OSPI MspDeInit.
- This function) takes as parameters the HAL peripheral handle and the Callback ID.
+ [..]
+ Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default
+ weak (surcharged) function. It allows to reset following callbacks:
+ (+) ErrorCallback : callback when error occurs.
+ (+) AbortCpltCallback : callback when abort is completed.
+ (+) FifoThresholdCallback : callback when the fifo threshold is reached.
+ (+) CmdCpltCallback : callback when a command without data is completed.
+ (+) RxCpltCallback : callback when a reception transfer is completed.
+ (+) TxCpltCallback : callback when a transmission transfer is completed.
+ (+) RxHalfCpltCallback : callback when half of the reception transfer is completed.
+ (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed.
+ (+) StatusMatchCallback : callback when a status match occurs.
+ (+) TimeOutCallback : callback when the timeout perioed expires.
+ (+) MspInitCallback : OSPI MspInit.
+ (+) MspDeInitCallback : OSPI MspDeInit.
+ [..]
+ This function) takes as parameters the HAL peripheral handle and the Callback ID.
- By default, after the @ref HAL_OSPI_Init and if the state is HAL_OSPI_STATE_RESET
- all callbacks are reset to the corresponding legacy weak (surcharged) functions.
- Exception done for MspInit and MspDeInit callbacks that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_OSPI_Init
- and @ref HAL_OSPI_DeInit only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_OSPI_Init and @ref HAL_OSPI_DeInit
- keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+ [..]
+ By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET
+ all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+ Exception done for MspInit and MspDeInit callbacks that are respectively
+ reset to the legacy weak (surcharged) functions in the HAL_OSPI_Init()
+ and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit()
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
- Callbacks can be registered/unregistered in READY state only.
- Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
- in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
- during the Init/DeInit.
- In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_OSPI_RegisterCallback before calling @ref HAL_OSPI_DeInit
- or @ref HAL_OSPI_Init function.
+ [..]
+ Callbacks can be registered/unregistered in READY state only.
+ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+ during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using HAL_OSPI_RegisterCallback() before calling HAL_OSPI_DeInit()
+ or HAL_OSPI_Init() function.
- When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
- not defined, the callback registering feature is not available
- and weak (surcharged) callbacks are used.
+ [..]
+ When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registering feature is not available
+ and weak (surcharged) callbacks are used.
@endverbatim
******************************************************************************
diff --git a/Src/stm32l5xx_hal_pcd.c b/Src/stm32l5xx_hal_pcd.c
index ce3055e..6434928 100644
--- a/Src/stm32l5xx_hal_pcd.c
+++ b/Src/stm32l5xx_hal_pcd.c
@@ -88,6 +88,8 @@
*/
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
+static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
+static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal);
/**
* @}
@@ -99,8 +101,8 @@
*/
/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -224,7 +226,10 @@
hpcd->State = HAL_PCD_STATE_BUSY;
/* Stop Device */
- (void)HAL_PCD_Stop(hpcd);
+ if (USB_StopDevice(hpcd->Instance) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
if (hpcd->MspDeInitCallback == NULL)
@@ -538,7 +543,7 @@
}
/**
- * @brief UnRegister the USB PCD Data OUT Stage Callback
+ * @brief Unregister the USB PCD Data OUT Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -611,7 +616,7 @@
}
/**
- * @brief UnRegister the USB PCD Data IN Stage Callback
+ * @brief Unregister the USB PCD Data IN Stage Callback
* USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -684,7 +689,7 @@
}
/**
- * @brief UnRegister the USB PCD Iso OUT incomplete Callback
+ * @brief Unregister the USB PCD Iso OUT incomplete Callback
* USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -757,7 +762,7 @@
}
/**
- * @brief UnRegister the USB PCD Iso IN incomplete Callback
+ * @brief Unregister the USB PCD Iso IN incomplete Callback
* USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -830,7 +835,7 @@
}
/**
- * @brief UnRegister the USB PCD BCD Callback
+ * @brief Unregister the USB PCD BCD Callback
* USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -903,7 +908,7 @@
}
/**
- * @brief UnRegister the USB PCD LPM Callback
+ * @brief Unregister the USB PCD LPM Callback
* USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback
* @param hpcd PCD handle
* @retval HAL status
@@ -940,8 +945,8 @@
*/
/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -962,9 +967,10 @@
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
- (void)USB_DevConnect(hpcd->Instance);
__HAL_PCD_ENABLE(hpcd);
+ (void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
@@ -977,9 +983,7 @@
{
__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
-
- (void)USB_StopDevice(hpcd->Instance);
-
+ (void)USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
return HAL_OK;
@@ -1288,8 +1292,8 @@
*/
/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -1312,6 +1316,7 @@
__HAL_LOCK(hpcd);
(void)USB_DevConnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
@@ -1325,6 +1330,7 @@
__HAL_LOCK(hpcd);
(void)USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
@@ -1340,6 +1346,7 @@
hpcd->USB_Address = address;
(void)USB_SetDevAddress(hpcd->Instance, address);
__HAL_UNLOCK(hpcd);
+
return HAL_OK;
}
/**
@@ -1477,6 +1484,8 @@
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
+ ep->xfer_fill_db = 1U;
+ ep->xfer_len_db = len;
ep->xfer_count = 0U;
ep->is_in = 1U;
ep->num = ep_addr & EP_ADDR_MSK;
@@ -1610,8 +1619,8 @@
*/
/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State functions #####
@@ -1656,9 +1665,7 @@
static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{
PCD_EPTypeDef *ep;
- uint16_t count;
- uint16_t wIstr;
- uint16_t wEPVal;
+ uint16_t count, wIstr, wEPVal, TxByteNbre;
uint8_t epindex;
/* stay in loop while pending interrupts */
@@ -1725,7 +1732,6 @@
HAL_PCD_SetupStageCallback(hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
-
else if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
@@ -1756,19 +1762,20 @@
else
{
/* Decode and service non control endpoints interrupt */
-
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, epindex);
+
if ((wEPVal & USB_EP_CTR_RX) != 0U)
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex);
ep = &hpcd->OUT_ep[epindex];
- /* OUT double Buffering */
+ /* OUT Single Buffering */
if (ep->doublebuffer == 0U)
{
count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
+
if (count != 0U)
{
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
@@ -1776,25 +1783,35 @@
}
else
{
- /* free EP OUT Buffer */
- PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
-
- if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
+ /* manage double buffer bulk out */
+ if (ep->type == EP_TYPE_BULK)
{
- /* read from endpoint BUF0Addr buffer */
- count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
- if (count != 0U)
- {
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
- }
+ count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal);
}
- else
+ else /* manage double buffer iso out */
{
- /* read from endpoint BUF1Addr buffer */
- count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
- if (count != 0U)
+ /* free EP OUT Buffer */
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+
+ if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U)
{
- USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ /* read from endpoint BUF0Addr buffer */
+ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+
+ if (count != 0U)
+ {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ }
+ }
+ else
+ {
+ /* read from endpoint BUF1Addr buffer */
+ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+
+ if (count != 0U)
+ {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ }
}
}
}
@@ -1813,10 +1830,10 @@
}
else
{
- (void)HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ (void) USB_EPStartXfer(hpcd->Instance, ep);
}
- } /* if((wEPVal & EP_CTR_RX) */
+ }
if ((wEPVal & USB_EP_CTR_TX) != 0U)
{
@@ -1825,32 +1842,297 @@
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex);
- /* multi-packet on the NON control IN endpoint */
- ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
- ep->xfer_buff += ep->xfer_count;
-
- /* Zero Length Packet? */
- if (ep->xfer_len == 0U)
+ /* Manage all non bulk transaction or Bulk Single Buffer Transaction */
+ if ((ep->type != EP_TYPE_BULK) ||
+ ((ep->type == EP_TYPE_BULK) && ((wEPVal & USB_EP_KIND) == 0U)))
{
- /* TX COMPLETE */
+ /* multi-packet on the NON control IN endpoint */
+ TxByteNbre = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len > TxByteNbre)
+ {
+ ep->xfer_len -= TxByteNbre;
+ }
+ else
+ {
+ ep->xfer_len = 0U;
+ }
+
+ /* Zero Length Packet? */
+ if (ep->xfer_len == 0U)
+ {
+ /* TX COMPLETE */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
- hpcd->DataInStageCallback(hpcd, ep->num);
+ hpcd->DataInStageCallback(hpcd, ep->num);
#else
- HAL_PCD_DataInStageCallback(hpcd, ep->num);
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* Transfer is not yet Done */
+ ep->xfer_buff += TxByteNbre;
+ ep->xfer_count += TxByteNbre;
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
+ }
}
+ /* bulk in double buffer enable in case of transferLen> Ep_Mps */
else
{
- (void)HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
+ (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal);
}
}
}
}
+
return HAL_OK;
}
/**
+ * @brief Manage double buffer bulk out transaction from ISR
+ * @param hpcd PCD handle
+ * @param ep current endpoint handle
+ * @param wEPVal Last snapshot of EPRx register value taken in ISR
+ * @retval HAL status
+ */
+static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd,
+ PCD_EPTypeDef *ep, uint16_t wEPVal)
+{
+ uint16_t count;
+
+ /* Manage Buffer0 OUT */
+ if ((wEPVal & USB_EP_DTOG_RX) != 0U)
+ {
+ /* Get count of received Data on buffer0 */
+ count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len >= count)
+ {
+ ep->xfer_len -= count;
+ }
+ else
+ {
+ ep->xfer_len = 0U;
+ }
+
+ if (ep->xfer_len == 0U)
+ {
+ /* set NAK to OUT endpoint since double buffer is enabled */
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
+ }
+
+ /* Check if Buffer1 is in blocked sate which requires to toggle */
+ if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+ {
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ }
+
+ if (count != 0U)
+ {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
+ }
+ }
+ /* Manage Buffer 1 DTOG_RX=0 */
+ else
+ {
+ /* Get count of received data */
+ count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len >= count)
+ {
+ ep->xfer_len -= count;
+ }
+ else
+ {
+ ep->xfer_len = 0U;
+ }
+
+ if (ep->xfer_len == 0U)
+ {
+ /* set NAK on the current endpoint */
+ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK);
+ }
+
+ /*Need to FreeUser Buffer*/
+ if ((wEPVal & USB_EP_DTOG_TX) == 0U)
+ {
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, 0U);
+ }
+
+ if (count != 0U)
+ {
+ USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
+ }
+ }
+
+ return count;
+}
+
+
+/**
+ * @brief Manage double buffer bulk IN transaction from ISR
+ * @param hpcd PCD handle
+ * @param ep current endpoint handle
+ * @param wEPVal Last snapshot of EPRx register value taken in ISR
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd,
+ PCD_EPTypeDef *ep, uint16_t wEPVal)
+{
+ uint32_t len;
+ uint16_t TxByteNbre;
+
+ /* Data Buffer0 ACK received */
+ if ((wEPVal & USB_EP_DTOG_TX) != 0U)
+ {
+ /* multi-packet on the NON control IN endpoint */
+ TxByteNbre = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len > TxByteNbre)
+ {
+ ep->xfer_len -= TxByteNbre;
+ }
+ else
+ {
+ ep->xfer_len = 0U;
+ }
+ /* Transfer is completed */
+ if (ep->xfer_len == 0U)
+ {
+ /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ if ((wEPVal & USB_EP_DTOG_RX) != 0U)
+ {
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ }
+ }
+ else /* Transfer is not yet Done */
+ {
+ /* need to Free USB Buff */
+ if ((wEPVal & USB_EP_DTOG_RX) != 0U)
+ {
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ }
+
+ /* Still there is data to Fill in the next Buffer */
+ if (ep->xfer_fill_db == 1U)
+ {
+ ep->xfer_buff += TxByteNbre;
+ ep->xfer_count += TxByteNbre;
+
+ /* Calculate the len of the new buffer to fill */
+ if (ep->xfer_len_db >= ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ ep->xfer_len_db -= len;
+ }
+ else if (ep->xfer_len_db == 0U)
+ {
+ len = TxByteNbre;
+ ep->xfer_fill_db = 0U;
+ }
+ else
+ {
+ ep->xfer_fill_db = 0U;
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ /* Write remaining Data to Buffer */
+ /* Set the Double buffer counter for pma buffer1 */
+ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+
+ /* Copy user buffer to USB PMA */
+ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len);
+ }
+ }
+ }
+ else /* Data Buffer1 ACK received */
+ {
+ /* multi-packet on the NON control IN endpoint */
+ TxByteNbre = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
+
+ if (ep->xfer_len >= TxByteNbre)
+ {
+ ep->xfer_len -= TxByteNbre;
+ }
+ else
+ {
+ ep->xfer_len = 0U;
+ }
+
+ /* Transfer is completed */
+ if (ep->xfer_len == 0U)
+ {
+ /* TX COMPLETE */
+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
+ hpcd->DataInStageCallback(hpcd, ep->num);
+#else
+ HAL_PCD_DataInStageCallback(hpcd, ep->num);
+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
+
+ /*need to Free USB Buff*/
+ if ((wEPVal & USB_EP_DTOG_RX) == 0U)
+ {
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ }
+ }
+ else /* Transfer is not yet Done */
+ {
+ /* need to Free USB Buff */
+ if ((wEPVal & USB_EP_DTOG_RX) == 0U)
+ {
+ PCD_FreeUserBuffer(hpcd->Instance, ep->num, 1U);
+ }
+
+ /* Still there is data to Fill in the next Buffer */
+ if (ep->xfer_fill_db == 1U)
+ {
+ ep->xfer_buff += TxByteNbre;
+ ep->xfer_count += TxByteNbre;
+
+ /* Calculate the len of the new buffer to fill */
+ if (ep->xfer_len_db >= ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ ep->xfer_len_db -= len;
+ }
+ else if (ep->xfer_len_db == 0U)
+ {
+ len = TxByteNbre;
+ ep->xfer_fill_db = 0U;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ ep->xfer_fill_db = 0;
+ }
+
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+
+ /* Copy the user buffer to USB PMA */
+ USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len);
+ }
+ }
+ }
+
+ /*enable endpoint IN*/
+ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+
+ return HAL_OK;
+}
+
+
+
+/**
* @}
*/
#endif /* defined (USB) */
diff --git a/Src/stm32l5xx_hal_pcd_ex.c b/Src/stm32l5xx_hal_pcd_ex.c
index beb4549..3f7e500 100644
--- a/Src/stm32l5xx_hal_pcd_ex.c
+++ b/Src/stm32l5xx_hal_pcd_ex.c
@@ -49,7 +49,7 @@
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
- *
+ *
@verbatim
===============================================================================
##### Extended features functions #####
diff --git a/Src/stm32l5xx_hal_pka.c b/Src/stm32l5xx_hal_pka.c
index ef0e00a..ffb1fc9 100644
--- a/Src/stm32l5xx_hal_pka.c
+++ b/Src/stm32l5xx_hal_pka.c
@@ -94,7 +94,7 @@
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
The resulting size can be the input parameter or the input parameter size + 1 (overflow).
- (+) Arithmetic substraction using:
+ (+) Arithmetic subtraction using:
(++) HAL_PKA_Sub().
(++) HAL_PKA_Sub_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
@@ -114,7 +114,7 @@
(++) HAL_PKA_ModAdd_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
- (+) Modular substraction using:
+ (+) Modular subtraction using:
(++) HAL_PKA_ModSub().
(++) HAL_PKA_ModSub_IT().
(++) HAL_PKA_Arithmetic_GetResult() to retrieve the result of the operation.
@@ -156,7 +156,7 @@
[..]
(+) Add HAL_PKA_IRQHandler to the IRQHandler of PKA.
(+) Enable the IRQ using HAL_NVIC_EnableIRQ().
- (+) When an operation is started in interrupt mode, the function returns immediatly.
+ (+) When an operation is started in interrupt mode, the function returns immediately.
(+) When the operation is completed, the callback HAL_PKA_OperationCpltCallback is called.
(+) When an error is encountered, the callback HAL_PKA_ErrorCallback is called.
(+) To stop any operation in interrupt mode, use HAL_PKA_Abort().
@@ -440,7 +440,7 @@
hpka->State = HAL_PKA_STATE_BUSY;
/* Reset the control register */
- /* This abort any operation in progress (PKA RAM content is not guaranted in this case) */
+ /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
hpka->Instance->CR = 0;
/* Reset any pending flag */
@@ -692,7 +692,7 @@
(++) Blocking mode : The operation is performed in the polling mode.
These functions return when data operation is completed.
(++) No-Blocking mode : The operation is performed using Interrupts.
- These functions return immediatly.
+ These functions return immediately.
The end of the operation is indicated by HAL_PKA_ErrorCallback in case of error.
The end of the operation is indicated by HAL_PKA_OperationCpltCallback in case of success.
To stop any operation in interrupt mode, use HAL_PKA_Abort().
@@ -891,7 +891,7 @@
* @brief Retrieve operation result.
* @param hpka PKA handle
* @param out Output information
- * @param outExt Additionnal Output information (facultative)
+ * @param outExt Additional Output information (facultative)
*/
void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt)
{
@@ -905,7 +905,7 @@
PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size);
}
- /* If user requires the additionnal information */
+ /* If user requires the additional information */
if (outExt != NULL)
{
/* Move the result to appropriate location (indicated in outExt parameter) */
@@ -1041,7 +1041,7 @@
*/
uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka)
{
- /* Invert the value of the PKA RAM containig the result of the operation */
+ /* Invert the value of the PKA RAM containing the result of the operation */
return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == 0UL) ? 1UL : 0UL;
}
@@ -1159,7 +1159,7 @@
}
/**
- * @brief Arithmetic substraction in blocking mode.
+ * @brief Arithmetic subtraction in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
@@ -1175,7 +1175,7 @@
}
/**
- * @brief Arithmetic substraction in non-blocking mode with Interrupt.
+ * @brief Arithmetic subtraction in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
@@ -1314,7 +1314,7 @@
}
/**
- * @brief Modular substraction in blocking mode.
+ * @brief Modular subtraction in blocking mode.
* @param hpka PKA handle
* @param in Input information
* @param Timeout Timeout duration
@@ -1330,7 +1330,7 @@
}
/**
- * @brief Modular substraction in non-blocking mode with Interrupt.
+ * @brief Modular subtraction in non-blocking mode with Interrupt.
* @param hpka PKA handle
* @param in Input information
* @retval HAL status
@@ -1527,7 +1527,7 @@
HAL_StatusTypeDef err = HAL_OK;
/* Clear EN bit */
- /* This abort any operation in progress (PKA RAM content is not guaranted in this case) */
+ /* This abort any operation in progress (PKA RAM content is not guaranteed in this case) */
CLEAR_BIT(hpka->Instance->CR, PKA_CR_EN);
SET_BIT(hpka->Instance->CR, PKA_CR_EN);
diff --git a/Src/stm32l5xx_hal_pwr.c b/Src/stm32l5xx_hal_pwr.c
index 06d7e8f..062bb78 100644
--- a/Src/stm32l5xx_hal_pwr.c
+++ b/Src/stm32l5xx_hal_pwr.c
@@ -163,8 +163,8 @@
[..]
The devices feature 8 low-power modes:
(+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
- (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
- (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
+ (+) Sleep mode: Cortex-M33 core clock stopped, peripherals kept running, main and low power regulators on.
+ (+) Low-power Sleep mode: Cortex-M33 core clock stopped, peripherals kept running, main regulator off, low power regulator on.
(+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
(+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
(+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.
@@ -188,7 +188,7 @@
=========================================
[..]
(+) Entry:
- The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
+ The Sleep mode / Low-power Sleep mode is entered through HAL_PWR_EnterSLEEPMode() API
in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered.
(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
(++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
@@ -210,7 +210,7 @@
===============================
[..]
(+) Entry:
- The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
+ The Stop 0, Stop 1 or Stop 2 modes are entered through the following API's:
(++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
(++) HAL_PWREx_EnterSTOP2Mode() for mode 2.
(+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
@@ -244,7 +244,7 @@
and Standby circuitry.
(++) Entry:
- (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API.
+ (+++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API.
SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register.
To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API
@@ -265,7 +265,7 @@
SRAM and registers contents are lost except for backup domain registers.
(+) Entry:
- The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
+ The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API.
(+) Exit:
(++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event,
diff --git a/Src/stm32l5xx_hal_pwr_ex.c b/Src/stm32l5xx_hal_pwr_ex.c
index 1c09383..58dd81b 100644
--- a/Src/stm32l5xx_hal_pwr_ex.c
+++ b/Src/stm32l5xx_hal_pwr_ex.c
@@ -176,7 +176,7 @@
/**
* @brief Enable battery charging.
- * When VDD is present, charge the external battery on VBAT thru an internal resistor.
+ * When VDD is present, charge the external battery on VBAT through an internal resistor.
* @param ResistorSelection specifies the resistor impedance.
* This parameter can be one of the following values:
* @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
@@ -676,7 +676,7 @@
/* Configure EXTI 35 to 38 interrupts if so required:
- scan thru PVMType to detect which PVMx is set and
+ scan through PVMType to detect which PVMx is set and
configure the corresponding EXTI line accordingly. */
switch (sConfigPVM->PVMType)
{
@@ -1181,28 +1181,37 @@
*/
void HAL_PWREx_DisableUCPDStandbyMode(void)
{
+ /* Write 0 immediately after Standby exit when using UCPD,
+ and before writing any UCPD registers */
CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
}
/**
- * @brief Enable dead battery behavior.
+ * @brief Enable the USB Type-C dead battery pull-down behavior
+ * on UCPDx_CC1 and UCPDx_CC2 pins
* @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
* @retval None
*/
void HAL_PWREx_EnableUCPDDeadBattery(void)
{
- /* Enable dead battery behavior */
+ /* Write 0 to enable the USB Type-C dead battery pull-down behavior */
CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
}
/**
- * @brief Disable dead battery behavior.
+ * @brief Disable the USB Type-C dead battery pull-down behavior
+ * on UCPDx_CC1 and UCPDx_CC2 pins
* @note This feature is secured by secured UCPD1 when system implements security (TZEN=1).
+ * @note After exiting reset, the USB Type-C dead battery behavior will be enabled,
+ * which may have a pull-down effect on CC1 and CC2 pins.
+ * It is recommended to disable it in all cases, either to stop this pull-down
+ * or to hand over control to the UCPD (which should therefore be
+ * initialized before doing the disable).
* @retval None
*/
void HAL_PWREx_DisableUCPDDeadBattery(void)
{
- /* Disable dead battery behavior */
+ /* Write 1 to disable the USB Type-C dead battery pull-down behavior */
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
}
diff --git a/Src/stm32l5xx_hal_rcc.c b/Src/stm32l5xx_hal_rcc.c
index 760d140..696606a 100644
--- a/Src/stm32l5xx_hal_rcc.c
+++ b/Src/stm32l5xx_hal_rcc.c
@@ -17,8 +17,8 @@
(4 MHz) with Flash 0 wait state. I-Cache is disabled, and all peripherals
are off except internal SRAMs, Flash and JTAG.
- (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses:
- all peripherals mapped on these busses are running at MSI speed.
+ (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
+ all peripherals mapped on these buses are running at MSI speed.
(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
(+) All GPIOs are in analog mode, except the JTAG pins which
are assigned to be used for debug purpose.
@@ -28,7 +28,7 @@
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance)
(+) Configure the System clock frequency and Flash settings
- (+) Configure the AHB and APB busses prescalers
+ (+) Configure the AHB and APB buses prescalers
(+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals which clocks are not
derived from the System clock (SAIx, RTC, ADC, USB FS/SDMMC1/RNG, FDCAN)
@@ -67,10 +67,10 @@
/** @defgroup RCC_Private_Constants RCC Private Constants
* @{
*/
-#define LSI_TIMEOUT_VALUE ((uint32_t)7U) /* 7 ms (maximum 6ms + 1) */
-#define HSI48_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE ((uint32_t)2U) /* 2 ms (minimum Tick + 1) */
-#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
+#define LSI_TIMEOUT_VALUE 7UL /* 7 ms (maximum 6ms + 1) */
+#define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define PLL_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */
+#define CLOCKSWITCH_TIMEOUT_VALUE 5000UL /* 5 s */
/**
* @}
*/
@@ -113,14 +113,14 @@
===============================================================================
[..]
This section provides functions allowing to configure the internal and external oscillators
- (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
+ (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
and APB2).
[..] Internal/external clock and PLL configuration
(+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through
the PLL as System clock source.
- (+) MSI (Mutiple Speed Internal): Its frequency is software trimmable from 100KHz to 48MHz.
+ (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHz to 48MHz.
It can be used to generate the clock for the USB FS (48 MHz).
The number of flash wait states is automatically adjusted when MSI range is updated with
HAL_RCC_OscConfig() and the MSI is used as System clock source.
@@ -161,17 +161,17 @@
failure occurs it is not supplied anymore to the RTC. If the MSI was used in
PLL-mode, this mode is disabled. The CSS on LSE failure is detected by a tamper event.
- (+) MCO (microcontroller clock output): used to output LSI, LSE, System clock, HSI, HSI48,
+ (+) MCO (microcontroller clock output): used to output LSI, LSE, System clock, HSI, HSI48,
HSE, main PLL clock or MSI (through a configurable prescaler) on PA8 pin.
- [..] System, AHB and APB busses clocks configuration
+ [..] System, AHB and APB buses clocks configuration
(+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
HSE and main PLL.
The AHB clock (HCLK) is derived from System clock through configurable
prescaler and used to clock the CPU, memory and peripherals mapped
on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these busses. You can use
+ the peripherals mapped on these buses. You can use
"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
@@ -234,6 +234,8 @@
* - All interrupt and reset flags cleared
* @note This function doesn't modify the configuration of the
* - Peripheral clocks source selection
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and is updated by this function
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_DeInit(void)
@@ -271,13 +273,13 @@
SystemCoreClock = MSI_VALUE;
/* Configure the source of time base considering new system clock settings */
- if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ if (HAL_InitTick(uwTickPrio) != HAL_OK)
{
return HAL_ERROR;
}
/* Wait till system clock source is ready */
- while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RCC_SYSCLKSOURCE_STATUS_MSI)
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
{
@@ -393,6 +395,9 @@
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * and is updated by this function in case of simple MSI range update when MSI
+ * used as system clock.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
@@ -422,8 +427,8 @@
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
- if ((sysclk_source == RCC_CFGR_SWS_MSI) ||
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
+ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
+ ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI)))
{
if ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
{
@@ -459,7 +464,7 @@
/* Decrease number of wait states update if necessary */
/* Only possible when MSI is the System clock source */
- if (sysclk_source == RCC_CFGR_SWS_MSI)
+ if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
{
if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
{
@@ -469,10 +474,10 @@
}
/* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
+ SystemCoreClock = HAL_RCC_GetHCLKFreq();
/* Configure the source of time base considering new system clocks settings*/
- status = HAL_InitTick(TICK_INT_PRIORITY);
+ status = HAL_InitTick(uwTickPrio);
if (status != HAL_OK)
{
return status;
@@ -530,8 +535,8 @@
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
- if ((sysclk_source == RCC_CFGR_SWS_HSE) ||
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
+ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) ||
+ ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
@@ -582,8 +587,8 @@
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if ((sysclk_source == RCC_CFGR_SWS_HSI) ||
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
+ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) ||
+ ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
{
/* When HSI is used as system clock it will not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
@@ -760,7 +765,7 @@
}
}
- /* Enable LSESYS additionnally if requested */
+ /* Enable LSESYS additionally if requested */
if ((RCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSEN) != 0U)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN);
@@ -874,7 +879,7 @@
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
{
/* Check if the PLL is used as system clock or not */
- if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+ if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
{
@@ -981,7 +986,7 @@
}
/**
- * @brief Initialize the CPU, AHB and APB busses clocks according to the specified
+ * @brief Initialize the CPU, AHB and APB buses clocks according to the specified
* parameters in the RCC_ClkInitStruct.
* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC peripheral.
@@ -1005,7 +1010,7 @@
* @arg FLASH_LATENCY_15 FLASH 15 Latency cycles
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
- * and updated by HAL_RCC_GetHCLKFreq() function called within this function
+ * and is updated by this function
*
* @note The MSI is used by default as system clock source after
* startup from Reset, wake-up from STANDBY mode. After restart from Reset,
@@ -1038,7 +1043,6 @@
uint32_t tickstart;
uint32_t pllfreq;
uint32_t hpre = RCC_SYSCLK_DIV1;
- HAL_StatusTypeDef status;
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
@@ -1207,12 +1211,10 @@
}
/* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
+ SystemCoreClock = HAL_RCC_GetHCLKFreq();
/* Configure the source of time base considering new system clocks settings*/
- status = HAL_InitTick(TICK_INT_PRIORITY);
-
- return status;
+ return HAL_InitTick(uwTickPrio);
}
/**
@@ -1229,7 +1231,7 @@
[..]
This subsection provides a set of functions allowing to:
- (+) Ouput clock to MCO pin.
+ (+) Output clock to MCO pin.
(+) Retrieve current clock frequencies.
(+) Enable the Clock Security System.
@@ -1274,7 +1276,7 @@
/* MCO Clock Enable */
__MCO1_CLK_ENABLE();
- /* Configue the MCO1 pin in alternate function mode */
+ /* Configure the MCO1 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO1_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -1327,8 +1329,8 @@
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
- if ((sysclk_source == RCC_CFGR_SWS_MSI) ||
- ((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
+ if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) ||
+ ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
{
/* MSI or PLL with MSI source used as system clock source */
@@ -1346,18 +1348,18 @@
/*MSI frequency range in Hz*/
msirange = MSIRangeTable[msirange];
- if (sysclk_source == RCC_CFGR_SWS_MSI)
+ if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI)
{
/* MSI used as system clock source */
sysclockfreq = msirange;
}
}
- else if (sysclk_source == RCC_CFGR_SWS_HSI)
+ else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
}
- else if (sysclk_source == RCC_CFGR_SWS_HSE)
+ else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
@@ -1367,7 +1369,7 @@
/* unexpected case: sysclockfreq at 0 */
}
- if (sysclk_source == RCC_CFGR_SWS_PLL)
+ if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
/* PLL used as system clock source */
@@ -1403,15 +1405,11 @@
* @brief Return the HCLK frequency.
* @note Each time HCLK changes, this function must be called to update the
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
- SystemCoreClockUpdate();
-
- return SystemCoreClock;
+ return (HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]);
}
/**
diff --git a/Src/stm32l5xx_hal_rcc_ex.c b/Src/stm32l5xx_hal_rcc_ex.c
index c6e3b56..32c7083 100644
--- a/Src/stm32l5xx_hal_rcc_ex.c
+++ b/Src/stm32l5xx_hal_rcc_ex.c
@@ -1917,7 +1917,7 @@
/* LSCO Pin Clock Enable */
__LSCO_CLK_ENABLE();
- /* Configue the LSCO pin in analog mode */
+ /* Configure the LSCO pin in analog mode */
GPIO_InitStruct.Pin = LSCO_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
@@ -2020,7 +2020,7 @@
##### Extended Clock Recovery System Control functions #####
===============================================================================
[..]
- For devices with Clock Recovery System feature (CRS), RCC Extention HAL driver can be used as follows:
+ For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows:
(#) In System clock config, HSI48 needs to be enabled
diff --git a/Src/stm32l5xx_hal_rng.c b/Src/stm32l5xx_hal_rng.c
index f2619b7..c009a58 100644
--- a/Src/stm32l5xx_hal_rng.c
+++ b/Src/stm32l5xx_hal_rng.c
@@ -110,6 +110,19 @@
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
+/** @defgroup RNG_Private_Defines RNG Private Defines
+ * @{
+ */
+/* Health test control register information to use in CCM algorithm */
+#define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */
+#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
+#define RNG_HTCFG 0x000CAA74U /*!< For best latency and to be compliant with NIST */
+#else /* RNG_VER_3_2 */
+#define RNG_HTCFG 0x00007274U /*!< For best latency and to be compliant with NIST */
+#endif /* RNG_VER_3_0 || RNG_VER_3_1 */
+/**
+ * @}
+ */
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RNG_Private_Constants RNG Private Constants
@@ -121,7 +134,14 @@
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/** @addtogroup RNG_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
+
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNG_Exported_Functions
@@ -129,8 +149,8 @@
*/
/** @addtogroup RNG_Exported_Functions_Group1
- * @brief Initialization and configuration functions
- *
+ * @brief Initialization and configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and configuration functions #####
@@ -195,23 +215,29 @@
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
-
/* Disable RNG */
__HAL_RNG_DISABLE(hrng);
/* Clock Error Detection Configuration when CONDRT bit is set to 1 */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST);
- /* Writing bits CONDRST=0*/
+#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
+ /*!< magic number must be written immediately before to RNG_HTCRG */
+ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
+ /* for best latency and to be compliant with NIST */
+ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
+#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */
+
+ /* Writing bit CONDRST=0 */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for conditioning reset process to be completed */
- while(HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
{
- if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_READY;
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
@@ -260,6 +286,7 @@
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
{
uint32_t tickstart;
+
/* Check the RNG handle allocation */
if (hrng == NULL)
{
@@ -269,22 +296,25 @@
/* Clear Clock Error Detection bit when CONDRT bit is set to 1 */
MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, RNG_CED_ENABLE | RNG_CR_CONDRST);
- /* Writing bits CONDRST=0*/
+ /* Writing bit CONDRST=0 */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for conditioning reset process to be completed */
- while(HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
+ while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
{
- if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_READY;
hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
return HAL_ERROR;
}
}
+
/* Disable the RNG Peripheral */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
@@ -360,7 +390,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
+ pRNG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -377,44 +408,44 @@
{
switch (CallbackID)
{
- case HAL_RNG_ERROR_CB_ID :
- hrng->ErrorCallback = pCallback;
- break;
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = pCallback;
+ break;
- case HAL_RNG_MSPINIT_CB_ID :
- hrng->MspInitCallback = pCallback;
- break;
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
- case HAL_RNG_MSPDEINIT_CB_ID :
- hrng->MspDeInitCallback = pCallback;
- break;
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else if (HAL_RNG_STATE_RESET == hrng->State)
{
switch (CallbackID)
{
- case HAL_RNG_MSPINIT_CB_ID :
- hrng->MspInitCallback = pCallback;
- break;
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = pCallback;
+ break;
- case HAL_RNG_MSPDEINIT_CB_ID :
- hrng->MspDeInitCallback = pCallback;
- break;
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = pCallback;
+ break;
- default :
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -452,44 +483,44 @@
{
switch (CallbackID)
{
- case HAL_RNG_ERROR_CB_ID :
- hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
- break;
+ case HAL_RNG_ERROR_CB_ID :
+ hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */
+ break;
- case HAL_RNG_MSPINIT_CB_ID :
- hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
- break;
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
- case HAL_RNG_MSPDEINIT_CB_ID :
- hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
- break;
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */
+ break;
- default :
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else if (HAL_RNG_STATE_RESET == hrng->State)
{
switch (CallbackID)
{
- case HAL_RNG_MSPINIT_CB_ID :
- hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
- break;
+ case HAL_RNG_MSPINIT_CB_ID :
+ hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */
+ break;
- case HAL_RNG_MSPDEINIT_CB_ID :
- hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
- break;
+ case HAL_RNG_MSPDEINIT_CB_ID :
+ hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */
+ break;
- default :
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
- /* Return error status */
- status = HAL_ERROR;
- break;
+ default :
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -579,8 +610,8 @@
*/
/** @addtogroup RNG_Exported_Functions_Group2
- * @brief Peripheral Control functions
- *
+ * @brief Peripheral Control functions
+ *
@verbatim
===============================================================================
##### Peripheral Control functions #####
@@ -597,11 +628,11 @@
/**
* @brief Generates a 32-bit random number.
* @note This function checks value of RNG_FLAG_DRDY flag to know if valid
- * random number is available in the DR register (RNG_FLAG_DRDY flag set
+ * random number is available in the DR register (RNG_FLAG_DRDY flag set
* whenever a random number is available through the RNG_DR register).
- * After transitioning from 0 to 1 (random number available),
- * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
- * four words from the RNG_DR register, i.e. further function calls
+ * After transitioning from 0 to 1 (random number available),
+ * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
+ * four words from the RNG_DR register, i.e. further function calls
* will immediately return a new u32 random number (additional words are
* available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
* @note When no more random number data is available in DR register, RNG_FLAG_DRDY
@@ -625,6 +656,18 @@
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
+ /* Check if there is a seed error */
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ /* Reset from seed error */
+ status = RNG_RecoverSeedError(hrng);
+ if (status == HAL_ERROR)
+ {
+ return status;
+ }
+ }
/* Get tick */
tickstart = HAL_GetTick();
@@ -644,8 +687,19 @@
/* Get a 32bit Random number */
hrng->RandomNumber = hrng->Instance->DR;
- *random32bit = hrng->RandomNumber;
-
+ /* In case of seed error, the value available in the RNG_DR register must not
+ be used as it may not have enough entropy */
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ /* Clear bit DRDY */
+ CLEAR_BIT(hrng->Instance->SR, RNG_FLAG_DRDY);
+ }
+ else /* No seed error */
+ {
+ *random32bit = hrng->RandomNumber;
+ }
hrng->State = HAL_RNG_STATE_READY;
}
else
@@ -728,9 +782,21 @@
}
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{
- /* Update the error code */
- hrng->ErrorCode = HAL_RNG_ERROR_SEED;
- rngclockerror = 1U;
+ /* Check if Seed Error Current Status (SECS) is set */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+ {
+ /* RNG IP performed the reset automatically (auto-reset) */
+ /* Clear bit SEIS */
+ CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+ }
+ else
+ {
+ /* Seed Error has not been recovered : Update the error code */
+ hrng->ErrorCode = HAL_RNG_ERROR_SEED;
+ rngclockerror = 1U;
+ /* Disable the IT */
+ __HAL_RNG_DISABLE_IT(hrng);
+ }
}
else
{
@@ -752,6 +818,8 @@
/* Clear the clock error flag */
__HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI);
+
+ return;
}
/* Check RNG data ready interrupt occurred */
@@ -797,7 +865,7 @@
* @note When RNG_FLAG_DRDY flag value is set, first random number has been read
* from DR register in IRQ Handler and is provided as callback parameter.
* Depending on valid data available in the conditioning output buffer,
- * additional words can be read by the application from DR register till
+ * additional words can be read by the application from DR register till
* DRDY bit remains high.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
@@ -834,8 +902,8 @@
/** @addtogroup RNG_Exported_Functions_Group3
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
===============================================================================
##### Peripheral State functions #####
@@ -863,7 +931,7 @@
* @brief Return the RNG handle error code.
* @param hrng: pointer to a RNG_HandleTypeDef structure.
* @retval RNG Error Code
-*/
+ */
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng)
{
/* Return RNG Error Code */
@@ -876,6 +944,94 @@
/**
* @}
*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup RNG_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief RNG sequence to recover from a seed error
+ * @param hrng pointer to a RNG_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng)
+{
+ __IO uint32_t count = 0U;
+
+ /*Check if seed error current status (SECS)is set */
+ if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) == RESET)
+ {
+ /* RNG performed the reset automatically (auto-reset) */
+ /* Clear bit SEIS */
+ CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+ }
+ else /* Sequence to fully recover from a seed error*/
+ {
+ /* Writing bit CONDRST=1*/
+ SET_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+ /* Writing bit CONDRST=0*/
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+
+ /* Wait for conditioning reset process to be completed */
+ count = RNG_TIMEOUT_VALUE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hrng->ErrorCallback(hrng);
+#else
+ /* Call legacy weak Error callback */
+ HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+ return HAL_ERROR;
+ }
+ }
+ while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST));
+
+ if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
+ {
+ /* Clear bit SEIS */
+ CLEAR_BIT(hrng->Instance->SR, RNG_IT_SEI);
+ }
+
+ /* Wait for SECS to be cleared */
+ count = RNG_TIMEOUT_VALUE;
+ do
+ {
+ count-- ;
+ if (count == 0U)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT;
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrng);
+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
+ /* Call registered Error callback */
+ hrng->ErrorCallback(hrng);
+#else
+ /* Call legacy weak Error callback */
+ HAL_RNG_ErrorCallback(hrng);
+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
+ return HAL_ERROR;
+ }
+ }
+ while (HAL_IS_BIT_SET(hrng->Instance->SR, RNG_FLAG_SECS));
+ }
+ /* Update the error code */
+ hrng->ErrorCode &= ~ HAL_RNG_ERROR_SEED;
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
#endif /* HAL_RNG_MODULE_ENABLED */
diff --git a/Src/stm32l5xx_hal_rng_ex.c b/Src/stm32l5xx_hal_rng_ex.c
index 0c1c2e2..718721b 100644
--- a/Src/stm32l5xx_hal_rng_ex.c
+++ b/Src/stm32l5xx_hal_rng_ex.c
@@ -29,7 +29,7 @@
* @{
*/
-#if defined (RNG)
+#if defined(RNG)
/** @addtogroup RNGEx
* @brief RNG Extended HAL module driver.
@@ -37,28 +37,25 @@
*/
#ifdef HAL_RNG_MODULE_ENABLED
-#if defined (RNG_CR_CONDRST)
-
+#if defined(RNG_CR_CONDRST)
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
-
-/** @addtogroup RNGEx_Private_Defines
+/** @defgroup RNGEx_Private_Defines RNGEx Private Defines
* @{
*/
/* Health test control register information to use in CCM algorithm */
#define RNG_HTCFG_1 0x17590ABCU /*!< magic number */
#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
#define RNG_HTCFG 0x000CAA74U /*!< for best latency and To be compliant with NIST */
-#else /*RNG_VER_3_2*/
-#define RNG_HTCFG 0x00005A4EU /*!< for best latency and To be compliant with NIST */
-#endif
+#else /* RNG_VER_3_2 */
+#define RNG_HTCFG 0x00007274U /*!< for best latency and To be compliant with NIST */
+#endif /* RNG_VER_3_1 || RNG_VER_3_0 */
/**
* @}
*/
-
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RNGEx_Private_Constants
+/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2U
@@ -67,7 +64,15 @@
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/** @addtogroup RNG_Private_Functions
+ * @{
+ */
+HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
+
+/**
+ * @}
+ */
+/* Private functions --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNGEx_Exported_Functions
@@ -75,8 +80,8 @@
*/
/** @addtogroup RNGEx_Exported_Functions_Group1
- * @brief Configuration functions
- *
+ * @brief Configuration functions
+ *
@verbatim
===============================================================================
##### Configuration and lock functions #####
@@ -98,7 +103,7 @@
* the configuration information for RNG module
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
{
uint32_t tickstart;
@@ -106,7 +111,7 @@
HAL_StatusTypeDef status ;
/* Check the RNG handle allocation */
- if ((hrng == NULL)||(pConf == NULL))
+ if ((hrng == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
@@ -128,51 +133,51 @@
/* Disable RNG */
__HAL_RNG_DISABLE(hrng);
- /* RNG CR register configuration. Set value in CR register for :
- - NIST Compliance setting
- - Clock divider value
- - CONFIG 1, CONFIG 2 and CONFIG 3 values */
+ /* RNG CR register configuration. Set value in CR register for :
+ - NIST Compliance setting
+ - Clock divider value
+ - CONFIG 1, CONFIG 2 and CONFIG 3 values */
- cr_value = (uint32_t) ( pConf->ClockDivider | pConf->NistCompliance
- | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos)
- | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos)
- | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos));
+ cr_value = (uint32_t)(pConf->ClockDivider | pConf->NistCompliance
+ | (pConf->Config1 << RNG_CR_RNG_CONFIG1_Pos)
+ | (pConf->Config2 << RNG_CR_RNG_CONFIG2_Pos)
+ | (pConf->Config3 << RNG_CR_RNG_CONFIG3_Pos));
- MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1
- | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3,
- (uint32_t) (RNG_CR_CONDRST | cr_value));
+ MODIFY_REG(hrng->Instance->CR, RNG_CR_NISTC | RNG_CR_CLKDIV | RNG_CR_RNG_CONFIG1
+ | RNG_CR_RNG_CONFIG2 | RNG_CR_RNG_CONFIG3,
+ (uint32_t)(RNG_CR_CONDRST | cr_value));
-#if defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
- /*!< magic number must be written immediately before to RNG_HTCRG */
- WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
- /* for best latency and to be compliant with NIST */
- WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
-#endif
+#if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0)
+ /*!< magic number must be written immediately before to RNG_HTCRG */
+ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1);
+ /* for best latency and to be compliant with NIST */
+ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG);
+#endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */
- /* Writing bits CONDRST=0*/
- CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Writing bit CONDRST=0*/
+ CLEAR_BIT(hrng->Instance->CR, RNG_CR_CONDRST);
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Wait for conditioning reset process to be completed */
- while(HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
- {
- if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+ /* Wait for conditioning reset process to be completed */
+ while (HAL_IS_BIT_SET(hrng->Instance->CR, RNG_CR_CONDRST))
{
- hrng->State = HAL_RNG_STATE_READY;
- hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
- return HAL_ERROR;
+ if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
+ {
+ hrng->State = HAL_RNG_STATE_READY;
+ hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
+ return HAL_ERROR;
+ }
}
- }
- /* Enable RNG */
- __HAL_RNG_ENABLE(hrng);
+ /* Enable RNG */
+ __HAL_RNG_ENABLE(hrng);
- /* Initialize the RNG state */
- hrng->State = HAL_RNG_STATE_READY;
+ /* Initialize the RNG state */
+ hrng->State = HAL_RNG_STATE_READY;
- /* function status */
- status = HAL_OK;
+ /* function status */
+ status = HAL_OK;
}
else
{
@@ -193,14 +198,14 @@
* the configuration information for RNG module
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf)
{
HAL_StatusTypeDef status ;
/* Check the RNG handle allocation */
- if ((hrng == NULL)||(pConf == NULL))
+ if ((hrng == NULL) || (pConf == NULL))
{
return HAL_ERROR;
}
@@ -212,8 +217,8 @@
hrng->State = HAL_RNG_STATE_BUSY;
/* Get RNG parameters */
- pConf->Config1 = (uint32_t) ((hrng->Instance->CR & RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos) ;
- pConf->Config2 = (uint32_t) ((hrng->Instance->CR & RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
+ pConf->Config1 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos) ;
+ pConf->Config2 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);
pConf->Config3 = (uint32_t)((hrng->Instance->CR & RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);
pConf->ClockDivider = (hrng->Instance->CR & RNG_CR_CLKDIV);
pConf->NistCompliance = (hrng->Instance->CR & RNG_CR_NISTC);
@@ -237,12 +242,12 @@
/**
* @brief RNG current configuration lock.
* @note This function allows to lock RNG peripheral configuration.
- * Once locked, HW RNG reset has to be perfomed prior any further
+ * Once locked, HW RNG reset has to be performed prior any further
* configuration update.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng)
{
HAL_StatusTypeDef status;
@@ -254,7 +259,7 @@
}
/* Check RNG peripheral state */
- if(hrng->State == HAL_RNG_STATE_READY)
+ if (hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
@@ -283,11 +288,63 @@
* @}
*/
+/** @addtogroup RNGEx_Exported_Functions_Group2
+ * @brief Recover from seed error function
+ *
+@verbatim
+ ===============================================================================
+ ##### Configuration and lock functions #####
+ ===============================================================================
+ [..] This section provide function allowing to:
+ (+) Recover from a seed error
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief RNG sequence to recover from a seed error
+ * @param hrng: pointer to a RNG_HandleTypeDef structure.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check the RNG handle allocation */
+ if (hrng == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check RNG peripheral state */
+ if (hrng->State == HAL_RNG_STATE_READY)
+ {
+ /* Change RNG peripheral state */
+ hrng->State = HAL_RNG_STATE_BUSY;
+
+ /* sequence to fully recover from a seed error */
+ status = RNG_RecoverSeedError(hrng);
+ }
+ else
+ {
+ hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
+ status = HAL_ERROR;
+ }
+
+ /* Return the function status */
+ return status;
+}
+
/**
* @}
*/
-#endif /* CONDRST */
+/**
+ * @}
+ */
+
+#endif /* RNG_CR_CONDRST */
#endif /* HAL_RNG_MODULE_ENABLED */
/**
* @}
diff --git a/Src/stm32l5xx_hal_rtc_ex.c b/Src/stm32l5xx_hal_rtc_ex.c
index f328a27..b39715a 100644
--- a/Src/stm32l5xx_hal_rtc_ex.c
+++ b/Src/stm32l5xx_hal_rtc_ex.c
@@ -757,7 +757,7 @@
{
if ((RTC->SMISR & RTC_SMISR_WUTMF) != 0u)
{
- /* Immediatly clear flags */
+ /* Immediately clear flags */
WRITE_REG(RTC->SCR, RTC_SCR_CWUTF);
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/* Call wake up timer registered Callback */
@@ -1987,7 +1987,7 @@
/* Get secure interrupt status */
tmp = READ_REG(TAMP->SMISR);
- /* Immediatly clear flags */
+ /* Immediately clear flags */
WRITE_REG(TAMP->SCR, tmp);
/* Check Tamper1 status */
diff --git a/Src/stm32l5xx_hal_sai.c b/Src/stm32l5xx_hal_sai.c
index 8e105db..7c59b38 100644
--- a/Src/stm32l5xx_hal_sai.c
+++ b/Src/stm32l5xx_hal_sai.c
@@ -1525,7 +1525,7 @@
/* Enable SAI Tx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
- /* Wait untill FIFO is not empty */
+ /* Wait until FIFO is not empty */
while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY)
{
/* Check for the Timeout */
@@ -2370,7 +2370,7 @@
*/
static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai)
{
- register uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
+ uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7U / 1000U);
HAL_StatusTypeDef status = HAL_OK;
/* Disable the SAI instance */
diff --git a/Src/stm32l5xx_hal_sd.c b/Src/stm32l5xx_hal_sd.c
index 48c63bb..2789511 100644
--- a/Src/stm32l5xx_hal_sd.c
+++ b/Src/stm32l5xx_hal_sd.c
@@ -472,7 +472,16 @@
Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE;
Init.BusWide = SDMMC_BUS_WIDE_1B;
Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE;
- Init.ClockDiv = SDMMC_INIT_CLK_DIV;
+
+ /* Init Clock should be less or equal to 400Khz*/
+ sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1);
+ if (sdmmc_clk == 0U)
+ {
+ hsd->State = HAL_SD_STATE_READY;
+ hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER;
+ return HAL_ERROR;
+ }
+ Init.ClockDiv = sdmmc_clk/(2U*400000U);
#if (USE_SD_TRANSCEIVER != 0U)
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
@@ -493,16 +502,8 @@
/* wait 74 Cycles: required power up waiting time before starting
the SD initialization sequence */
- sdmmc_clk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SDMMC1)/(2U*SDMMC_INIT_CLK_DIV);
-
- if(sdmmc_clk != 0U)
- {
- HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
- }
- else
- {
- HAL_Delay(2U);
- }
+ sdmmc_clk = sdmmc_clk/(2U*Init.ClockDiv);
+ HAL_Delay(1U+ (74U*1000U/(sdmmc_clk)));
/* Identify card operating voltage */
errorstate = SD_PowerON(hsd);
@@ -555,7 +556,7 @@
hsd->State = HAL_SD_STATE_BUSY;
#if (USE_SD_TRANSCEIVER != 0U)
- /* Desactivate the 1.8V Mode */
+ /* Deactivate the 1.8V Mode */
if (hsd->Init.TranceiverPresent == SDMMC_TRANSCEIVER_PRESENT)
{
#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
diff --git a/Src/stm32l5xx_hal_sd_ex.c b/Src/stm32l5xx_hal_sd_ex.c
index f7ab072..ef291b2 100644
--- a/Src/stm32l5xx_hal_sd_ex.c
+++ b/Src/stm32l5xx_hal_sd_ex.c
@@ -74,8 +74,8 @@
/**
* @brief Configure DMA Dual Buffer mode. The Data transfer is managed by an Internal DMA.
* @param hsd: SD handle
- * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transfered data
- * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transfered data
+ * @param pDataBuffer0: Pointer to the buffer0 that will contain/receive the transferred data
+ * @param pDataBuffer1: Pointer to the buffer1 that will contain/receive the transferred data
* @param BufferSize: Size of Buffer0 in Blocks. Buffer0 and Buffer1 must have the same size.
* @retval HAL status
*/
@@ -120,6 +120,7 @@
DmaBase0_reg = hsd->Instance->IDMABASE0;
DmaBase1_reg = hsd->Instance->IDMABASE1;
+
if ((hsd->Instance->IDMABSIZE == 0U) || (DmaBase0_reg == 0U) || (DmaBase1_reg == 0U))
{
hsd->ErrorCode = HAL_SD_ERROR_ADDR_OUT_OF_RANGE;
@@ -178,7 +179,7 @@
}
/**
- * @brief Write block(s) to a specified address in a card. The transfered Data are stored in Buffer0 and Buffer1.
+ * @brief Write block(s) to a specified address in a card. The transferred Data are stored in Buffer0 and Buffer1.
* Buffer0, Buffer1 and BufferSize need to be configured by function HAL_SDEx_ConfigDMAMultiBuffer before call this function.
* @param hsd: SD handle
* @param BlockAdd: Block Address from where data is to be read
diff --git a/Src/stm32l5xx_hal_smartcard.c b/Src/stm32l5xx_hal_smartcard.c
index 67f74de..75a6777 100644
--- a/Src/stm32l5xx_hal_smartcard.c
+++ b/Src/stm32l5xx_hal_smartcard.c
@@ -35,7 +35,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer complete
+ interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
@@ -107,8 +108,8 @@
allows the user to configure dynamically the driver callbacks.
[..]
- Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback.
- Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
+ Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback.
+ Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
(+) RxCpltCallback : Rx Complete Callback.
(+) ErrorCallback : Error Callback.
@@ -123,9 +124,9 @@
and a pointer to the user callback function.
[..]
- Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
+ Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function.
- @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+ HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) TxCpltCallback : Tx Complete Callback.
@@ -140,13 +141,13 @@
(+) MspDeInitCallback : SMARTCARD MspDeInit.
[..]
- By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
+ By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
- examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback().
+ examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback().
Exception done for MspInit and MspDeInit functions that are respectively
- reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init()
- and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
- If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit()
+ reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init()
+ and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand).
+ If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
@@ -155,8 +156,8 @@
in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user)
MspInit/DeInit callbacks can be used during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks
- using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit()
- or @ref HAL_SMARTCARD_Init() function.
+ using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit()
+ or HAL_SMARTCARD_Init() function.
[..]
When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or
@@ -483,7 +484,8 @@
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
- HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback)
+ HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
+ pSMARTCARD_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -618,43 +620,45 @@
switch (CallbackID)
{
case HAL_SMARTCARD_TX_COMPLETE_CB_ID :
- hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_SMARTCARD_RX_COMPLETE_CB_ID :
- hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_SMARTCARD_ERROR_CB_ID :
- hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID :
- hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID :
- hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback*/
break;
case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID :
- hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
break;
case HAL_SMARTCARD_RX_FIFO_FULL_CB_ID :
- hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
break;
case HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID :
- hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
break;
case HAL_SMARTCARD_MSPINIT_CB_ID :
- hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
+ hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_SMARTCARD_MSPDEINIT_CB_ID :
- hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
+ hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -725,62 +729,67 @@
(+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
[..]
- (+) There are two modes of transfer:
- (++) Blocking mode: The communication is performed in polling mode.
+ (#) There are two modes of transfer:
+ (##) Blocking mode: The communication is performed in polling mode.
The HAL status of all data processing is returned by the same function
after finishing transfer.
- (++) Non-Blocking mode: The communication is performed using Interrupts
+ (##) Non-Blocking mode: The communication is performed using Interrupts
or DMA, the relevant API's return the HAL status.
The end of the data processing will be indicated through the
dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
using DMA mode.
- (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+ (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
will be executed respectively at the end of the Transmit or Receive process
The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
error is detected.
- (+) Blocking mode APIs are :
- (++) HAL_SMARTCARD_Transmit()
- (++) HAL_SMARTCARD_Receive()
+ (#) Blocking mode APIs are :
+ (##) HAL_SMARTCARD_Transmit()
+ (##) HAL_SMARTCARD_Receive()
- (+) Non Blocking mode APIs with Interrupt are :
- (++) HAL_SMARTCARD_Transmit_IT()
- (++) HAL_SMARTCARD_Receive_IT()
- (++) HAL_SMARTCARD_IRQHandler()
+ (#) Non Blocking mode APIs with Interrupt are :
+ (##) HAL_SMARTCARD_Transmit_IT()
+ (##) HAL_SMARTCARD_Receive_IT()
+ (##) HAL_SMARTCARD_IRQHandler()
- (+) Non Blocking mode functions with DMA are :
- (++) HAL_SMARTCARD_Transmit_DMA()
- (++) HAL_SMARTCARD_Receive_DMA()
+ (#) Non Blocking mode functions with DMA are :
+ (##) HAL_SMARTCARD_Transmit_DMA()
+ (##) HAL_SMARTCARD_Receive_DMA()
- (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
- (++) HAL_SMARTCARD_TxCpltCallback()
- (++) HAL_SMARTCARD_RxCpltCallback()
- (++) HAL_SMARTCARD_ErrorCallback()
+ (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+ (##) HAL_SMARTCARD_TxCpltCallback()
+ (##) HAL_SMARTCARD_RxCpltCallback()
+ (##) HAL_SMARTCARD_ErrorCallback()
[..]
(#) Non-Blocking mode transfers could be aborted using Abort API's :
- (++) HAL_SMARTCARD_Abort()
- (++) HAL_SMARTCARD_AbortTransmit()
- (++) HAL_SMARTCARD_AbortReceive()
- (++) HAL_SMARTCARD_Abort_IT()
- (++) HAL_SMARTCARD_AbortTransmit_IT()
- (++) HAL_SMARTCARD_AbortReceive_IT()
+ (##) HAL_SMARTCARD_Abort()
+ (##) HAL_SMARTCARD_AbortTransmit()
+ (##) HAL_SMARTCARD_AbortReceive()
+ (##) HAL_SMARTCARD_Abort_IT()
+ (##) HAL_SMARTCARD_AbortTransmit_IT()
+ (##) HAL_SMARTCARD_AbortReceive_IT()
- (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
- (++) HAL_SMARTCARD_AbortCpltCallback()
- (++) HAL_SMARTCARD_AbortTransmitCpltCallback()
- (++) HAL_SMARTCARD_AbortReceiveCpltCallback()
+ (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT),
+ a set of Abort Complete Callbacks are provided:
+ (##) HAL_SMARTCARD_AbortCpltCallback()
+ (##) HAL_SMARTCARD_AbortTransmitCpltCallback()
+ (##) HAL_SMARTCARD_AbortReceiveCpltCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
- (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
- If user wants to abort it, Abort services should be called by user.
- (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
- This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+ (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer,
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+ If user wants to abort it, Abort services should be called by user.
+ (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+ This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt
+ mode reception and all errors in DMA mode.
+ Error code is set to allow user to identify error type,
+ and HAL_SMARTCARD_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -824,14 +833,23 @@
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
hsmartcard->TxXferSize = Size;
hsmartcard->TxXferCount = Size;
@@ -846,20 +864,28 @@
hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU);
ptmpdata++;
}
- if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart,
- Timeout) != HAL_OK)
+ if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET,
+ tickstart, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
- /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
- /* Disable the Peripheral first to update modes */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* At end of Tx process, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -980,14 +1006,23 @@
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
/* Configure Tx interrupt processing */
if (hsmartcard->FifoMode == SMARTCARD_FIFOMODE_ENABLE)
{
@@ -1128,14 +1163,23 @@
/* Disable the Peripheral first to update mode for TX master */
CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- /* Disable Rx, enable Tx */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- SET_BIT(hsmartcard->Instance->RQR, (uint16_t)SMARTCARD_RXDATA_FLUSH_REQUEST);
+ /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor
+ the bidirectional line to detect a NACK signal in case of parity error.
+ Therefore, the receiver block must be enabled as well (RE bit must be set). */
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+ }
+ /* Enable Tx */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
/* Enable the Peripheral */
SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* Perform a TX/RX FIFO Flush */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+
/* Set the SMARTCARD DMA transfer complete callback */
hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
@@ -1276,7 +1320,8 @@
*/
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
{
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
@@ -1338,8 +1383,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1430,7 +1475,8 @@
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
@@ -1470,8 +1516,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1498,14 +1544,16 @@
{
uint32_t abortcplt = 1U;
- /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE, RXFT, TXFT and
+ ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(hsmartcard->Instance->CR1,
(USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE | USART_CR1_RTOIE |
USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
- /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
- before any call to DMA Abort functions */
+ /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle,
+ DMA Abort complete callbacks should be initialised before any call
+ to DMA Abort functions */
/* DMA Tx Handle is valid */
if (hsmartcard->hdmatx != NULL)
{
@@ -1599,8 +1647,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -1732,7 +1780,8 @@
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Disable RTOIE, EOBIE, RXNE, PE, RXFT and ERR (Frame error, noise error, overrun error) interrupts */
- CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+ CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE |
+ USART_CR1_EOBIE));
CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Check if a Transmit process is ongoing or not. If not disable ERR IT */
@@ -1771,8 +1820,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -1797,8 +1846,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF |
+ SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -2269,14 +2318,18 @@
void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard)
{
/* Init the SMARTCARD Callback settings */
- hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
- hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
- hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
- hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
- hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
- hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */
- hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
- hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */
+ hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak
+ AbortTransmitCpltCallback */
+ hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak
+ AbortReceiveCpltCallback */
+ hsmartcard->RxFifoFullCallback = HAL_SMARTCARDEx_RxFifoFullCallback; /* Legacy weak
+ RxFifoFullCallback */
+ hsmartcard->TxFifoEmptyCallback = HAL_SMARTCARDEx_TxFifoEmptyCallback; /* Legacy weak
+ TxFifoEmptyCallback */
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
@@ -2366,21 +2419,26 @@
{
case SMARTCARD_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_HSI:
- tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
- tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
case SMARTCARD_CLOCKSOURCE_LSE:
- tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
+ tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) +
+ (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break;
default:
ret = HAL_ERROR;
@@ -2541,7 +2599,8 @@
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
{
- /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+ /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
+ interrupts for the interrupt process */
CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
@@ -2735,8 +2794,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -2784,8 +2843,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
@@ -2846,8 +2905,8 @@
/* Clear the Error flags in the ICR register */
__HAL_SMARTCARD_CLEAR_FLAG(hsmartcard,
- SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF |
- SMARTCARD_CLEAR_EOBF);
+ SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF |
+ SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
/* Restore hsmartcard->RxState to Ready */
hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
@@ -2950,15 +3009,22 @@
CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
}
- /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
- if (hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ /* Disable the Peripheral first to update mode */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX)
+ && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
{
- /* Disable the Peripheral first to update modes */
- CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
- /* Enable the Peripheral */
- SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+ /* In case of TX only mode, if NACK is enabled, receiver block has been enabled
+ for Transmit phase. Disable this receiver block. */
+ CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
}
+ if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+ || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE))
+ {
+ /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */
+ __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard);
+ }
+ SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
/* Tx process is ended, restore hsmartcard->gState to Ready */
hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
diff --git a/Src/stm32l5xx_hal_smartcard_ex.c b/Src/stm32l5xx_hal_smartcard_ex.c
index 95cacba..c7d3100 100644
--- a/Src/stm32l5xx_hal_smartcard_ex.c
+++ b/Src/stm32l5xx_hal_smartcard_ex.c
@@ -472,8 +472,10 @@
tx_fifo_depth = TX_FIFO_DEPTH;
rx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
tx_fifo_threshold = (uint8_t)(READ_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
- hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
- hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+ hsmartcard->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / \
+ (uint16_t)denominator[tx_fifo_threshold];
+ hsmartcard->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / \
+ (uint16_t)denominator[rx_fifo_threshold];
}
}
diff --git a/Src/stm32l5xx_hal_smbus.c b/Src/stm32l5xx_hal_smbus.c
index 4164105..855883e 100644
--- a/Src/stm32l5xx_hal_smbus.c
+++ b/Src/stm32l5xx_hal_smbus.c
@@ -203,7 +203,8 @@
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout);
static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest);
@@ -214,7 +215,8 @@
static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request);
/**
* @}
*/
@@ -226,8 +228,8 @@
*/
/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
@@ -579,7 +581,8 @@
* @param pCallback pointer to the Callback function
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID,
+ pSMBUS_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -858,8 +861,8 @@
*/
/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
- *
+ * @brief Data transfers functions
+ *
@verbatim
===============================================================================
##### IO operation functions #####
@@ -911,7 +914,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
@@ -950,7 +954,8 @@
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
}
else
{
@@ -1010,7 +1015,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData,
+ uint16_t Size, uint32_t XferOptions)
{
uint32_t tmp;
@@ -1050,7 +1056,8 @@
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
}
else
{
@@ -1165,7 +1172,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -1213,7 +1221,8 @@
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE))
{
- SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize,
+ SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
}
else
{
@@ -1259,7 +1268,8 @@
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
+ uint32_t XferOptions)
{
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
@@ -1417,7 +1427,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -1526,8 +1537,7 @@
/* Increment Trials */
SMBUS_Trials++;
- }
- while (SMBUS_Trials < Trials);
+ } while (SMBUS_Trials < Trials);
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -1549,8 +1559,8 @@
*/
/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
- * @{
- */
+ * @{
+ */
/**
* @brief Handle SMBUS event interrupt request.
@@ -1566,7 +1576,12 @@
uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1);
/* SMBUS in mode Transmitter ---------------------------------------------------*/
- if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) &&
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
@@ -1585,7 +1600,12 @@
}
/* SMBUS in mode Receiver ----------------------------------------------------*/
- if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) &&
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
@@ -1604,7 +1624,12 @@
}
/* SMBUS in mode Listener Only --------------------------------------------------*/
- if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
+ if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) ||
+ (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) ||
+ (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) &&
+ ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) ||
+ (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)))
{
if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
@@ -1744,8 +1769,8 @@
*/
/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
- *
+ * @brief Peripheral State and Errors functions
+ *
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
@@ -1771,11 +1796,11 @@
}
/**
-* @brief Return the SMBUS error code.
+ * @brief Return the SMBUS error code.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
-* @retval SMBUS Error Code
-*/
+ * @retval SMBUS Error Code
+ */
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus)
{
return hsmbus->ErrorCode;
@@ -1790,7 +1815,7 @@
*/
/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions
- * @brief Data transfers Private functions
+ * @brief Data transfers Private functions
* @{
*/
@@ -1854,7 +1879,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* REenable the selected SMBUS peripheral */
+ /* Re-enable the selected SMBUS peripheral */
__HAL_SMBUS_ENABLE(hsmbus);
/* Call the corresponding callback to inform upper layer of End of Transfer */
@@ -1941,7 +1966,8 @@
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
- SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE,
+ (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
@@ -2155,7 +2181,8 @@
HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
}
- else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
+ else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) ||
+ (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET))
{
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
{
@@ -2210,7 +2237,8 @@
{
if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
- SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)),
+ SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
else
@@ -2554,7 +2582,8 @@
* @param Timeout Timeout duration
* @retval HAL status
*/
-static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status,
+ uint32_t Timeout)
{
uint32_t tickstart = HAL_GetTick();
@@ -2603,7 +2632,8 @@
* @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
-static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
+static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
+ uint32_t Request)
{
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
@@ -2611,12 +2641,16 @@
assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
/* update CR2 register */
- MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
- (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
+ MODIFY_REG(hsmbus->Instance->CR2,
+ ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
+ (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
- * @brief Convert SMBUSx OTHER_xxx XferOptions to functionnal XferOptions.
+ * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions.
* @param hsmbus SMBUS handle.
* @retval None
*/
diff --git a/Src/stm32l5xx_hal_spi.c b/Src/stm32l5xx_hal_spi.c
index 31c965c..9fd89ca 100644
--- a/Src/stm32l5xx_hal_spi.c
+++ b/Src/stm32l5xx_hal_spi.c
@@ -131,7 +131,7 @@
DataSize = SPI_DATASIZE_8BIT:
+----------------------------------------------------------------------------------------------+
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | Process | Transfer mode |---------------------|----------------------|----------------------|
| | | Master | Slave | Master | Slave | Master | Slave |
|==============================================================================================|
| T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
@@ -156,7 +156,7 @@
DataSize = SPI_DATASIZE_16BIT:
+----------------------------------------------------------------------------------------------+
| | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
- | Process | Tranfert mode |---------------------|----------------------|----------------------|
+ | Process | Transfer mode |---------------------|----------------------|----------------------|
| | | Master | Slave | Master | Slave | Master | Slave |
|==============================================================================================|
| T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
@@ -337,6 +337,24 @@
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
+
+ if (hspi->Init.Mode == SPI_MODE_MASTER)
+ {
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+ }
+ else
+ {
+ /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
+ hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
+ }
+ }
+ else
+ {
+ assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
+
+ /* Force polarity and phase to TI protocaol requirements */
+ hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
+ hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
}
#if (USE_SPI_CRC != 0U)
assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
@@ -400,44 +418,56 @@
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
}
- /* Align the CRC Length on the data size */
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
- {
- /* CRC Length aligned on the data size : value set by default */
- if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
- {
- hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
- }
- else
- {
- hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
- }
- }
-
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
- WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
- hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
- hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
+ WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
+ (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
+ (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
+ (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
+ (hspi->Init.NSS & SPI_CR1_SSM) |
+ (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
+ (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
+ (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
#if (USE_SPI_CRC != 0U)
- /* Configure : CRC Length */
- if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ /*---------------------------- SPIx CRCL Configuration -------------------*/
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- hspi->Instance->CR1 |= SPI_CR1_CRCL;
+ /* Align the CRC Length on the data size */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
+ {
+ /* CRC Length aligned on the data size : value set by default */
+ if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
+ }
+ else
+ {
+ hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
+ }
+ }
+
+ /* Configure : CRC Length */
+ if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
+ {
+ SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL);
+ }
}
#endif /* USE_SPI_CRC */
/* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
- WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
- hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
+ WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
+ (hspi->Init.TIMode & SPI_CR2_FRF) |
+ (hspi->Init.NSSPMode & SPI_CR2_NSSP) |
+ (hspi->Init.DataSize & SPI_CR2_DS_Msk) |
+ (frxth & SPI_CR2_FRXTH)));
#if (USE_SPI_CRC != 0U)
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
- WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
+ WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
}
#endif /* USE_SPI_CRC */
@@ -835,6 +865,8 @@
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi);
}
@@ -1042,6 +1074,8 @@
/* Configure communication direction: 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi);
}
@@ -1544,6 +1578,8 @@
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi);
}
@@ -1635,6 +1671,8 @@
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi);
}
@@ -1835,6 +1873,8 @@
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
SPI_1LINE_TX(hspi);
}
@@ -1965,6 +2005,8 @@
/* Configure communication direction : 1Line */
if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
{
+ /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
+ __HAL_SPI_DISABLE(hspi);
SPI_1LINE_RX(hspi);
}
@@ -2278,8 +2320,7 @@
break;
}
count--;
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2296,8 +2337,7 @@
break;
}
count--;
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2442,8 +2482,7 @@
break;
}
count--;
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -2460,8 +2499,7 @@
break;
}
count--;
- }
- while (hspi->State != HAL_SPI_STATE_ABORT);
+ } while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */
count = resetcount;
}
@@ -3482,7 +3520,7 @@
*/
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- /* Read 8bit CRC to flush Data Regsiter */
+ /* Read 8bit CRC to flush Data Register */
READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
hspi->CRCSize--;
@@ -3590,7 +3628,7 @@
*/
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
{
- /* Read 16bit CRC to flush Data Regsiter */
+ /* Read 16bit CRC to flush Data Register */
READ_REG(hspi->Instance->DR);
/* Disable RXNE interrupt */
@@ -3807,69 +3845,22 @@
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
uint32_t Timeout, uint32_t Tickstart)
{
+ __IO uint32_t count;
+ uint32_t tmp_timeout;
+ uint32_t tmp_tickstart;
+
+ /* Adjust Timeout value in case of end of transfer */
+ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
+ tmp_tickstart = HAL_GetTick();
+
+ /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
+ count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
+
while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
{
if (Timeout != HAL_MAX_DELAY)
{
- if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
- {
- /* Disable the SPI and reset the CRC: the CRC value should be cleared
- on both master and slave sides in order to resynchronize the master
- and slave for their respective CRC calculation */
-
- /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
- __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
- if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
- || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
- {
- /* Disable SPI peripheral */
- __HAL_SPI_DISABLE(hspi);
- }
-
- /* Reset CRC Calculation */
- if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
- {
- SPI_RESET_CRC(hspi);
- }
-
- hspi->State = HAL_SPI_STATE_READY;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hspi);
-
- return HAL_TIMEOUT;
- }
- }
- }
-
- return HAL_OK;
-}
-
-/**
- * @brief Handle SPI FIFO Communication Timeout.
- * @param hspi pointer to a SPI_HandleTypeDef structure that contains
- * the configuration information for SPI module.
- * @param Fifo Fifo to check
- * @param State Fifo state to check
- * @param Timeout Timeout duration
- * @param Tickstart tick start value
- * @retval HAL status
- */
-static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
- uint32_t Timeout, uint32_t Tickstart)
-{
- while ((hspi->Instance->SR & Fifo) != State)
- {
- if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
- {
- /* Read 8bit CRC to flush Data Register */
- READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
- }
-
- if (Timeout != HAL_MAX_DELAY)
- {
- if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
+ if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
{
/* Disable the SPI and reset the CRC: the CRC value should be cleared
on both master and slave sides in order to resynchronize the master
@@ -3898,6 +3889,87 @@
return HAL_TIMEOUT;
}
+ /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
+ if(count == 0U)
+ {
+ tmp_timeout = 0U;
+ }
+ count--;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Handle SPI FIFO Communication Timeout.
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
+ * the configuration information for SPI module.
+ * @param Fifo Fifo to check
+ * @param State Fifo state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
+ uint32_t Timeout, uint32_t Tickstart)
+{
+ __IO uint32_t count;
+ uint32_t tmp_timeout;
+ uint32_t tmp_tickstart;
+
+ /* Adjust Timeout value in case of end of transfer */
+ tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
+ tmp_tickstart = HAL_GetTick();
+
+ /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
+ count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U);
+
+ while ((hspi->Instance->SR & Fifo) != State)
+ {
+ if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
+ {
+ /* Read 8bit CRC to flush Data Register */
+ READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
+ }
+
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
+ {
+ /* Disable the SPI and reset the CRC: the CRC value should be cleared
+ on both master and slave sides in order to resynchronize the master
+ and slave for their respective CRC calculation */
+
+ /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
+ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
+
+ if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
+ || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
+ {
+ /* Disable SPI peripheral */
+ __HAL_SPI_DISABLE(hspi);
+ }
+
+ /* Reset CRC Calculation */
+ if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
+ {
+ SPI_RESET_CRC(hspi);
+ }
+
+ hspi->State = HAL_SPI_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hspi);
+
+ return HAL_TIMEOUT;
+ }
+ /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
+ if(count == 0U)
+ {
+ tmp_timeout = 0U;
+ }
+ count--;
}
}
@@ -3984,7 +4056,7 @@
{
uint32_t tickstart;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Disable ERR interrupt */
@@ -4184,8 +4256,7 @@
break;
}
count--;
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
@@ -4226,8 +4297,7 @@
break;
}
count--;
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
{
@@ -4258,8 +4328,7 @@
break;
}
count--;
- }
- while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
+ } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
/* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
diff --git a/Src/stm32l5xx_hal_sram.c b/Src/stm32l5xx_hal_sram.c
index 55e2f1f..b3ca520 100644
--- a/Src/stm32l5xx_hal_sram.c
+++ b/Src/stm32l5xx_hal_sram.c
@@ -135,9 +135,9 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-static void SRAM_DMACplt (DMA_HandleTypeDef *hdma);
+static void SRAM_DMACplt(DMA_HandleTypeDef *hdma);
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma);
-static void SRAM_DMAError (DMA_HandleTypeDef *hdma);
+static void SRAM_DMAError(DMA_HandleTypeDef *hdma);
/**
@endcond
*/
@@ -170,7 +170,8 @@
* @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
+ FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the SRAM handle parameter */
if (hsram == NULL)
@@ -184,7 +185,7 @@
hsram->Lock = HAL_UNLOCKED;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- if(hsram->MspInitCallback == NULL)
+ if (hsram->MspInitCallback == NULL)
{
hsram->MspInitCallback = HAL_SRAM_MspInit;
}
@@ -206,7 +207,8 @@
(void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
/* Initialize SRAM extended mode timing Interface */
- (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
+ (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,
+ hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
@@ -226,7 +228,7 @@
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
{
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
- if(hsram->MspDeInitCallback == NULL)
+ if (hsram->MspDeInitCallback == NULL)
{
hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
}
@@ -341,11 +343,12 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
- uint8_t * pdestbuff = pDstBuffer;
+ uint8_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
@@ -388,11 +391,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint8_t *psramaddress = (uint8_t *)pAddress;
- uint8_t * psrcbuff = pSrcBuffer;
+ uint8_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
@@ -434,7 +438,8 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
@@ -451,11 +456,11 @@
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
- /* Check if the size is a 32-bits mulitple */
+ /* Check if the size is a 32-bits multiple */
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Read data from memory */
- for (size = BufferSize; size != limit; size-=2U)
+ for (size = BufferSize; size != limit; size -= 2U)
{
*pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU);
pdestbuff++;
@@ -493,11 +498,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
__IO uint32_t *psramaddress = pAddress;
- uint16_t * psrcbuff = pSrcBuffer;
+ uint16_t *psrcbuff = pSrcBuffer;
uint8_t limit;
/* Check the SRAM controller state */
@@ -509,11 +515,11 @@
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
- /* Check if the size is a 32-bits mulitple */
+ /* Check if the size is a 32-bits multiple */
limit = (((BufferSize % 2U) != 0U) ? 1U : 0U);
/* Write data to memory */
- for (size = BufferSize; size != limit; size-=2U)
+ for (size = BufferSize; size != limit; size -= 2U)
{
*psramaddress = (uint32_t)(*psrcbuff);
psrcbuff++;
@@ -551,11 +557,12 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
- __IO uint32_t * psramaddress = pAddress;
- uint32_t * pdestbuff = pDstBuffer;
+ __IO uint32_t *psramaddress = pAddress;
+ uint32_t *pdestbuff = pDstBuffer;
HAL_SRAM_StateTypeDef state = hsram->State;
/* Check the SRAM controller state */
@@ -598,11 +605,12 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
{
uint32_t size;
- __IO uint32_t * psramaddress = pAddress;
- uint32_t * psrcbuff = pSrcBuffer;
+ __IO uint32_t *psramaddress = pAddress;
+ uint32_t *psrcbuff = pSrcBuffer;
/* Check the SRAM controller state */
if (hsram->State == HAL_SRAM_STATE_READY)
@@ -644,7 +652,8 @@
* @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
+ uint32_t BufferSize)
{
HAL_StatusTypeDef status;
HAL_SRAM_StateTypeDef state = hsram->State;
@@ -692,7 +701,8 @@
* @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
+ uint32_t BufferSize)
{
HAL_StatusTypeDef status;
@@ -735,12 +745,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -749,20 +760,20 @@
__HAL_LOCK(hsram);
state = hsram->State;
- if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SRAM_MSP_INIT_CB_ID :
- hsram->MspInitCallback = pCallback;
- break;
- case HAL_SRAM_MSP_DEINIT_CB_ID :
- hsram->MspDeInitCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = pCallback;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -788,7 +799,7 @@
* @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID
* @retval status
*/
-HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
@@ -797,42 +808,42 @@
__HAL_LOCK(hsram);
state = hsram->State;
- if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SRAM_MSP_INIT_CB_ID :
- hsram->MspInitCallback = HAL_SRAM_MspInit;
- break;
- case HAL_SRAM_MSP_DEINIT_CB_ID :
- hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
- break;
- case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
- hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
- break;
- case HAL_SRAM_DMA_XFER_ERR_CB_ID :
- hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
- else if(state == HAL_SRAM_STATE_RESET)
+ else if (state == HAL_SRAM_STATE_RESET)
{
switch (CallbackId)
{
- case HAL_SRAM_MSP_INIT_CB_ID :
- hsram->MspInitCallback = HAL_SRAM_MspInit;
- break;
- case HAL_SRAM_MSP_DEINIT_CB_ID :
- hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_MSP_INIT_CB_ID :
+ hsram->MspInitCallback = HAL_SRAM_MspInit;
+ break;
+ case HAL_SRAM_MSP_DEINIT_CB_ID :
+ hsram->MspDeInitCallback = HAL_SRAM_MspDeInit;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -857,12 +868,13 @@
* @param pCallback : pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
+ pSRAM_DmaCallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
HAL_SRAM_StateTypeDef state;
- if(pCallback == NULL)
+ if (pCallback == NULL)
{
return HAL_ERROR;
}
@@ -871,20 +883,20 @@
__HAL_LOCK(hsram);
state = hsram->State;
- if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
+ if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED))
{
switch (CallbackId)
{
- case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
- hsram->DmaXferCpltCallback = pCallback;
- break;
- case HAL_SRAM_DMA_XFER_ERR_CB_ID :
- hsram->DmaXferErrorCallback = pCallback;
- break;
- default :
- /* update return status */
- status = HAL_ERROR;
- break;
+ case HAL_SRAM_DMA_XFER_CPLT_CB_ID :
+ hsram->DmaXferCpltCallback = pCallback;
+ break;
+ case HAL_SRAM_DMA_XFER_ERR_CB_ID :
+ hsram->DmaXferErrorCallback = pCallback;
+ break;
+ default :
+ /* update return status */
+ status = HAL_ERROR;
+ break;
}
}
else
@@ -904,8 +916,8 @@
*/
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
- * @brief Control functions
- *
+ * @brief Control functions
+ *
@verbatim
==============================================================================
##### SRAM Control functions #####
@@ -927,7 +939,7 @@
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_PROTECTED)
+ if (hsram->State == HAL_SRAM_STATE_PROTECTED)
{
/* Process Locked */
__HAL_LOCK(hsram);
@@ -961,7 +973,7 @@
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
{
/* Check the SRAM controller state */
- if(hsram->State == HAL_SRAM_STATE_READY)
+ if (hsram->State == HAL_SRAM_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsram);
@@ -991,8 +1003,8 @@
*/
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
- *
+ * @brief Peripheral State functions
+ *
@verbatim
==============================================================================
##### SRAM State functions #####
@@ -1034,7 +1046,7 @@
*/
static void SRAM_DMACplt(DMA_HandleTypeDef *hdma)
{
- SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
@@ -1056,7 +1068,7 @@
*/
static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma)
{
- SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
@@ -1078,7 +1090,7 @@
*/
static void SRAM_DMAError(DMA_HandleTypeDef *hdma)
{
- SRAM_HandleTypeDef* hsram = ( SRAM_HandleTypeDef* )(hdma->Parent);
+ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent);
/* Disable the DMA channel */
__HAL_DMA_DISABLE(hdma);
diff --git a/Src/stm32l5xx_hal_tim.c b/Src/stm32l5xx_hal_tim.c
index e330665..feabba4 100644
--- a/Src/stm32l5xx_hal_tim.c
+++ b/Src/stm32l5xx_hal_tim.c
@@ -307,6 +307,9 @@
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
@@ -344,6 +347,9 @@
HAL_TIM_Base_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
/* Change the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
@@ -410,8 +416,15 @@
htim->State = HAL_TIM_STATE_BUSY;
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -465,8 +478,15 @@
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -550,8 +570,15 @@
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -661,6 +688,9 @@
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
@@ -698,6 +728,9 @@
HAL_TIM_OC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
/* Change the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
@@ -780,8 +813,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -898,8 +938,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1112,8 +1159,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1271,6 +1325,9 @@
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
@@ -1308,6 +1365,9 @@
HAL_TIM_PWM_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
/* Change the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
@@ -1390,8 +1450,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1507,8 +1574,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1720,8 +1794,15 @@
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1879,6 +1960,9 @@
/* Init the base time for the input capture */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
@@ -1916,6 +2000,9 @@
HAL_TIM_IC_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
/* Change the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
@@ -1994,8 +2081,15 @@
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -2102,8 +2196,15 @@
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -2309,8 +2410,15 @@
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -2336,6 +2444,9 @@
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
+ /* Disable the Input Capture channel */
+ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
+
switch (Channel)
{
case TIM_CHANNEL_1:
@@ -2374,9 +2485,6 @@
break;
}
- /* Disable the Input Capture channel */
- TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
@@ -2477,6 +2585,9 @@
/* Configure the OPM Mode */
htim->Instance->CR1 |= OnePulseMode;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -2516,6 +2627,9 @@
HAL_TIM_OnePulse_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
@@ -2902,6 +3016,9 @@
/* Write to TIMx CCER */
htim->Instance->CCER = tmpccer;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -2942,6 +3059,9 @@
HAL_TIM_Encoder_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
/* Set the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
@@ -4291,8 +4411,8 @@
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR2
+ * @arg TIM_DMABASE_OR3
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4308,20 +4428,74 @@
* @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
- uint32_t *BurstBuffer, uint32_t BurstLength)
+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
+{
+ return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR1
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_OR2
+ * @arg TIM_DMABASE_OR3
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -4329,7 +4503,7 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
}
}
else
@@ -4348,7 +4522,8 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4365,7 +4540,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4382,7 +4557,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4399,7 +4574,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4416,7 +4591,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4433,7 +4608,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4450,7 +4625,7 @@
/* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
- (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4459,14 +4634,12 @@
default:
break;
}
- /* configure the DMA Burst Mode */
- htim->Instance->DCR = (BurstBaseAddress | BurstLength);
+ /* Configure the DMA Burst Mode */
+ htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -4479,7 +4652,6 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4488,51 +4660,51 @@
{
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -4562,8 +4734,8 @@
* @arg TIM_DMABASE_CCMR3
* @arg TIM_DMABASE_CCR5
* @arg TIM_DMABASE_CCR6
- * @arg TIM_DMABASE_AF1
- * @arg TIM_DMABASE_AF2
+ * @arg TIM_DMABASE_OR2
+ * @arg TIM_DMABASE_OR3
* @param BurstRequestSrc TIM DMA Request sources
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
@@ -4582,17 +4754,71 @@
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{
+ return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
+ ((BurstLength) >> 8U) + 1U);
+}
+
+/**
+ * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
+ * @param htim TIM handle
+ * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
+ * This parameter can be one of the following values:
+ * @arg TIM_DMABASE_CR1
+ * @arg TIM_DMABASE_CR2
+ * @arg TIM_DMABASE_SMCR
+ * @arg TIM_DMABASE_DIER
+ * @arg TIM_DMABASE_SR
+ * @arg TIM_DMABASE_EGR
+ * @arg TIM_DMABASE_CCMR1
+ * @arg TIM_DMABASE_CCMR2
+ * @arg TIM_DMABASE_CCER
+ * @arg TIM_DMABASE_CNT
+ * @arg TIM_DMABASE_PSC
+ * @arg TIM_DMABASE_ARR
+ * @arg TIM_DMABASE_RCR
+ * @arg TIM_DMABASE_CCR1
+ * @arg TIM_DMABASE_CCR2
+ * @arg TIM_DMABASE_CCR3
+ * @arg TIM_DMABASE_CCR4
+ * @arg TIM_DMABASE_BDTR
+ * @arg TIM_DMABASE_OR1
+ * @arg TIM_DMABASE_CCMR3
+ * @arg TIM_DMABASE_CCR5
+ * @arg TIM_DMABASE_CCR6
+ * @arg TIM_DMABASE_OR2
+ * @arg TIM_DMABASE_OR3
+ * @param BurstRequestSrc TIM DMA Request sources
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: TIM update Interrupt source
+ * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+ * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+ * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+ * @arg TIM_DMA_COM: TIM Commutation DMA source
+ * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
+ * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
+ * @param DataLength Data length. This parameter can be one value
+ * between 1 and 0xFFFF.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
+ uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
+ uint32_t BurstLength, uint32_t DataLength)
+{
/* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength));
+ assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
- if (htim->State == HAL_TIM_STATE_BUSY)
+ if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
{
return HAL_BUSY;
}
- else if (htim->State == HAL_TIM_STATE_READY)
+ else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
{
if ((BurstBuffer == NULL) && (BurstLength > 0U))
{
@@ -4600,7 +4826,7 @@
}
else
{
- htim->State = HAL_TIM_STATE_BUSY;
+ htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
}
}
else
@@ -4619,7 +4845,8 @@
htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4635,7 +4862,8 @@
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4643,7 +4871,7 @@
}
case TIM_DMA_CC2:
{
- /* Set the DMA capture/compare callbacks */
+ /* Set the DMA capture callbacks */
htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
@@ -4651,7 +4879,8 @@
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4667,7 +4896,8 @@
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4683,7 +4913,8 @@
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4699,7 +4930,8 @@
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4715,7 +4947,8 @@
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */
- if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8U) + 1U) != HAL_OK)
+ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
+ DataLength) != HAL_OK)
{
return HAL_ERROR;
}
@@ -4725,14 +4958,12 @@
break;
}
- /* configure the DMA Burst Mode */
+ /* Configure the DMA Burst Mode */
htim->Instance->DCR = (BurstBaseAddress | BurstLength);
/* Enable the TIM DMA Request */
__HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
- htim->State = HAL_TIM_STATE_READY;
-
/* Return function status */
return HAL_OK;
}
@@ -4745,7 +4976,6 @@
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
{
- HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
@@ -4754,51 +4984,51 @@
{
case TIM_DMA_UPDATE:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
break;
}
case TIM_DMA_CC1:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
break;
}
case TIM_DMA_CC2:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
break;
}
case TIM_DMA_CC3:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
break;
}
case TIM_DMA_CC4:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
break;
}
case TIM_DMA_COM:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
break;
}
case TIM_DMA_TRIGGER:
{
- status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
+ (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
break;
}
default:
break;
}
- if (HAL_OK == status)
- {
- /* Disable the TIM Update DMA request */
- __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
- }
+ /* Disable the TIM Update DMA request */
+ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
+
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
/* Return function status */
- return status;
+ return HAL_OK;
}
/**
@@ -5135,13 +5365,13 @@
case TIM_CLOCKSOURCE_ITR1:
case TIM_CLOCKSOURCE_ITR2:
case TIM_CLOCKSOURCE_ITR3:
- {
- /* Check whether or not the timer instance supports internal trigger input */
- assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
+ {
+ /* Check whether or not the timer instance supports internal trigger input */
+ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
- TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- break;
- }
+ TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
+ break;
+ }
default:
break;
@@ -6117,6 +6347,19 @@
}
/**
+ * @brief Return actual state of a DMA burst operation.
+ * @param htim TIM handle
+ * @retval DMA burst state
+ */
+HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
+{
+ /* Check the parameters */
+ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
+
+ return htim->DMABurstState;
+}
+
+/**
* @}
*/
@@ -6496,7 +6739,7 @@
/**
* @brief Timer Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6571,7 +6814,7 @@
/**
* @brief Timer Output Compare 2 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6647,7 +6890,7 @@
/**
* @brief Timer Output Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6721,7 +6964,7 @@
/**
* @brief Timer Output Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -6781,7 +7024,7 @@
/**
* @brief Timer Output Compare 5 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
@@ -6834,7 +7077,7 @@
/**
* @brief Timer Output Compare 6 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config The ouput configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
@@ -6938,7 +7181,7 @@
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
- if(sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
+ if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)
{
return HAL_ERROR;
}
@@ -6990,11 +7233,11 @@
case TIM_TS_ITR1:
case TIM_TS_ITR2:
case TIM_TS_ITR3:
- {
- /* Check the parameter */
- assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
- break;
- }
+ {
+ /* Check the parameter */
+ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
+ break;
+ }
default:
break;
diff --git a/Src/stm32l5xx_hal_tim_ex.c b/Src/stm32l5xx_hal_tim_ex.c
index c86a79b..f98b64b 100644
--- a/Src/stm32l5xx_hal_tim_ex.c
+++ b/Src/stm32l5xx_hal_tim_ex.c
@@ -225,6 +225,9 @@
htim->Instance->CR2 &= ~TIM_CR2_MMS;
htim->Instance->CR2 |= TIM_TRGO_OC2REF;
+ /* Initialize the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
@@ -264,6 +267,9 @@
HAL_TIMEx_HallSensor_MspDeInit(htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ /* Change the DMA burst operation state */
+ htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
+
/* Change the TIM channels state */
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
@@ -345,8 +351,15 @@
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -421,8 +434,15 @@
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -520,8 +540,15 @@
__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -619,8 +646,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -726,8 +760,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -914,8 +955,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1053,8 +1101,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1158,8 +1213,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -1347,8 +1409,15 @@
__HAL_TIM_MOE_ENABLE(htim);
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
- tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ {
+ tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ {
+ __HAL_TIM_ENABLE(htim);
+ }
+ }
+ else
{
__HAL_TIM_ENABLE(htim);
}
@@ -2051,10 +2120,10 @@
/* Set the break input polarity */
if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
/* Set TIMx_OR2 */
htim->Instance->OR2 = tmporx;
@@ -2071,10 +2140,10 @@
/* Set the break input polarity */
if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
- {
- tmporx &= ~bkin_polarity_mask;
- tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
- }
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
/* Set TIMx_OR3 */
htim->Instance->OR3 = tmporx;
@@ -2171,7 +2240,7 @@
*
* For TIM17, the parameter can have the following values:
* @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
- * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock)
+ * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (constraints: MSI clock < 1/4 TIM APB clock)
* @arg TIM_TIM17_TI1_HSE_32: TIM17 TI1 is connected to HSE div 32
* @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
*
@@ -2179,8 +2248,8 @@
*/
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
{
- uint32_t tmpor1 = 0U;
- uint32_t tmpor2 = 0U;
+ uint32_t tmpor1;
+ uint32_t tmpor2;
__HAL_LOCK(htim);
diff --git a/Src/stm32l5xx_hal_timebase_rtc_wakeup_template.c b/Src/stm32l5xx_hal_timebase_rtc_wakeup_template.c
index 45ac20a..cc7a033 100644
--- a/Src/stm32l5xx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32l5xx_hal_timebase_rtc_wakeup_template.c
@@ -6,7 +6,7 @@
*
* This file overrides the native HAL time base functions (defined as weak)
* to use the RTC WAKEUP for the time base generation:
- * + Intializes the RTC peripheral and configures the wakeup timer to be
+ * + Initializes the RTC peripheral and configures the wakeup timer to be
* incremented each 1ms
* + The wakeup feature is configured to assert an interrupt each 1ms
* + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
diff --git a/Src/stm32l5xx_hal_timebase_tim_template.c b/Src/stm32l5xx_hal_timebase_tim_template.c
index e1589ab..0e0f38d 100644
--- a/Src/stm32l5xx_hal_timebase_tim_template.c
+++ b/Src/stm32l5xx_hal_timebase_tim_template.c
@@ -6,7 +6,7 @@
*
* This file override the native HAL time base functions (defined as weak)
* the TIM time base:
- * + Intializes the TIM6 peripheral to generate a Period elapsed Event each 1ms
+ * + Initializes the TIM6 peripheral to generate a Period elapsed Event each 1ms
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
*
@verbatim
diff --git a/Src/stm32l5xx_hal_uart.c b/Src/stm32l5xx_hal_uart.c
index 1cc13f4..d6e7fec 100644
--- a/Src/stm32l5xx_hal_uart.c
+++ b/Src/stm32l5xx_hal_uart.c
@@ -114,6 +114,10 @@
(+) MspDeInitCallback : UART MspDeInit.
[..]
+ For specific callback RxEventCallback, use dedicated registration/reset functions:
+ respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().
+
+ [..]
By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
all callbacks are set to the corresponding weak (surcharged) functions:
examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().
@@ -191,6 +195,8 @@
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
@@ -643,6 +649,7 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
__HAL_UNLOCK(huart);
@@ -930,6 +937,74 @@
return status;
}
+
+/**
+ * @brief Register a User UART Rx Event Callback
+ * To be used instead of the weak predefined callback
+ * @param huart Uart handle
+ * @param pCallback Pointer to the Rx Event Callback function
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if (pCallback == NULL)
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = pCallback;
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister the UART Rx Event Callback
+ * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+ * @param huart Uart handle
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(huart);
+
+ if (huart->gState == HAL_UART_STATE_READY)
+ {
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
+ }
+ else
+ {
+ huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(huart);
+ return status;
+}
+
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
/**
@@ -995,6 +1070,9 @@
(+) HAL_UART_AbortTransmitCpltCallback()
(+) HAL_UART_AbortReceiveCpltCallback()
+ (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:
+ (+) HAL_UARTEx_RxEventCallback()
+
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
@@ -1047,7 +1125,7 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
huart->TxXferSize = Size;
@@ -1136,8 +1214,9 @@
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
huart->RxXferSize = Size;
@@ -1288,58 +1367,10 @@
__HAL_LOCK(huart);
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
- huart->RxXferCount = Size;
- huart->RxISR = NULL;
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- /* Computation of UART mask to apply to RDR register */
- UART_MASK_COMPUTATION(huart);
-
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Configure Rx interrupt processing*/
- if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
- {
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- huart->RxISR = UART_RxISR_16BIT_FIFOEN;
- }
- else
- {
- huart->RxISR = UART_RxISR_8BIT_FIFOEN;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
- }
- else
- {
- /* Set the Rx ISR function pointer according to the data word length */
- if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- {
- huart->RxISR = UART_RxISR_16BIT;
- }
- else
- {
- huart->RxISR = UART_RxISR_8BIT;
- }
-
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
- }
-
- return HAL_OK;
+ return(UART_Start_Receive_IT(huart, pData, Size));
}
else
{
@@ -1445,53 +1476,10 @@
__HAL_LOCK(huart);
- huart->pRxBuffPtr = pData;
- huart->RxXferSize = Size;
+ /* Set Reception type to Standard reception */
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- huart->ErrorCode = HAL_UART_ERROR_NONE;
- huart->RxState = HAL_UART_STATE_BUSY_RX;
-
- if (huart->hdmarx != NULL)
- {
- /* Set the UART DMA transfer complete callback */
- huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
- /* Set the UART DMA Half transfer complete callback */
- huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
- /* Set the DMA error callback */
- huart->hdmarx->XferErrorCallback = UART_DMAError;
-
- /* Set the DMA abort callback */
- huart->hdmarx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
- {
- /* Set error code to DMA */
- huart->ErrorCode = HAL_UART_ERROR_DMA;
-
- __HAL_UNLOCK(huart);
-
- /* Restore huart->gState to ready */
- huart->gState = HAL_UART_STATE_READY;
-
- return HAL_ERROR;
- }
- }
- __HAL_UNLOCK(huart);
-
- /* Enable the UART Parity Error Interrupt */
- SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-
- /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
- SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
- /* Enable the DMA transfer for the receiver request by setting the DMAR bit
- in the UART CR3 register */
- SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
- return HAL_OK;
+ return(UART_Start_Receive_DMA(huart, pData, Size));
}
else
{
@@ -1552,7 +1540,7 @@
/* Clear the Overrun flag before resuming the Rx transfer */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -1651,6 +1639,12 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* Disable the UART DMA Tx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
@@ -1720,6 +1714,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
huart->ErrorCode = HAL_UART_ERROR_NONE;
@@ -1802,6 +1797,12 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
@@ -1838,6 +1839,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
return HAL_OK;
}
@@ -1864,6 +1866,12 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
before any call to DMA Abort functions */
/* DMA Tx Handle is valid */
@@ -1972,6 +1980,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2096,6 +2105,12 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+ }
+
/* Disable the UART DMA Rx request if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
@@ -2131,6 +2146,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2155,6 +2171,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* As no DMA to be aborted, call directly user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -2337,6 +2354,93 @@
} /* End if some error occurs */
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ &&((isrflags & USART_ISR_IDLE) != 0U)
+ &&((cr1its & USART_ISR_IDLE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* Check if DMA mode is enabled in UART */
+ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ {
+ /* DMA mode enabled */
+ /* Check received length : If all expected data are received, do nothing,
+ (DMA cplt callback will be called).
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+ if ( (nb_remaining_rx_data > 0U)
+ &&(nb_remaining_rx_data < huart->RxXferSize))
+ {
+ /* Reception is not complete */
+ huart->RxXferCount = nb_remaining_rx_data;
+
+ /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+ if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+ {
+ /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+ in the UART CR3 register */
+ CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Last bytes received, so no need as the abort is immediate */
+ (void)HAL_DMA_Abort(huart->hdmarx);
+ }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif
+ }
+ return;
+ }
+ else
+ {
+ /* DMA mode not enabled */
+ /* Check received length : If all expected data are received, do nothing.
+ Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ if ( (huart->RxXferCount > 0U)
+ &&(nb_rx_data > 0U) )
+ {
+ /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+ CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+ /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+ /* Rx process is completed, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+ /* Clear RxISR function pointer */
+ huart->RxISR = NULL;
+
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxEventCallback(huart, nb_rx_data);
+#else
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif
+ }
+ return;
+ }
+ }
+
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
{
@@ -2522,6 +2626,24 @@
}
/**
+ * @brief Reception Event Callback (Rx event notification called after use of advanced reception service).
+ * @param huart UART handle
+ * @param Size Number of data available in application reception buffer (indicates a position in
+ * reception buffer until which, data are available)
+ * @retval None
+ */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(huart);
+ UNUSED(Size);
+
+ /* NOTE : This function should not be modified, when the callback is needed,
+ the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+ */
+}
+
+/**
* @}
*/
@@ -2843,6 +2965,7 @@
huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */
huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */
}
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
@@ -2857,9 +2980,9 @@
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
- uint32_t usartdiv = 0x00000000U;
+ uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
- uint32_t lpuart_ker_ck_pres = 0x00000000U;
+ uint32_t lpuart_ker_ck_pres;
uint32_t pclk;
/* Check the parameters */
@@ -2926,29 +3049,33 @@
switch (clocksource)
{
case UART_CLOCKSOURCE_PCLK1:
- lpuart_ker_ck_pres = (HAL_RCC_GetPCLK1Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK1Freq();
break;
case UART_CLOCKSOURCE_PCLK2:
- lpuart_ker_ck_pres = (HAL_RCC_GetPCLK2Freq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetPCLK2Freq();
break;
case UART_CLOCKSOURCE_HSI:
- lpuart_ker_ck_pres = ((uint32_t)HSI_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = (uint32_t) HSI_VALUE;
break;
case UART_CLOCKSOURCE_SYSCLK:
- lpuart_ker_ck_pres = (HAL_RCC_GetSysClockFreq() / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = HAL_RCC_GetSysClockFreq();
break;
case UART_CLOCKSOURCE_LSE:
- lpuart_ker_ck_pres = ((uint32_t)LSE_VALUE / UART_GET_DIV_FACTOR(huart->Init.ClockPrescaler));
+ pclk = (uint32_t) LSE_VALUE;
break;
default:
+ pclk = 0U;
ret = HAL_ERROR;
break;
}
- /* if proper clock source reported */
- if (lpuart_ker_ck_pres != 0U)
+ /* If proper clock source reported */
+ if (pclk != 0U)
{
- /* ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+ /* Compute clock after Prescaler */
+ lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+
+ /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
{
@@ -2956,32 +3083,9 @@
}
else
{
- switch (clocksource)
- {
- case UART_CLOCKSOURCE_PCLK1:
- pclk = HAL_RCC_GetPCLK1Freq();
- usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- case UART_CLOCKSOURCE_PCLK2:
- pclk = HAL_RCC_GetPCLK2Freq();
- usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint32_t)(UART_DIV_LPUART(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- case UART_CLOCKSOURCE_SYSCLK:
- pclk = HAL_RCC_GetSysClockFreq();
- usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint32_t)(UART_DIV_LPUART(LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- break;
- default:
- ret = HAL_ERROR;
- break;
- }
-
- /* It is forbidden to write values lower than 0x300 in the LPUART_BRR register */
+ /* Check computed UsartDiv value is in allocated range
+ (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+ usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, (uint64_t)huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
{
huart->Instance->BRR = usartdiv;
@@ -2990,8 +3094,8 @@
{
ret = HAL_ERROR;
}
- } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
- } /* if (lpuart_ker_ck_pres != 0) */
+ } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+ } /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
@@ -3000,37 +3104,39 @@
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) HSI_VALUE;
break;
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING8((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) LSE_VALUE;
break;
default:
+ pclk = 0U;
ret = HAL_ERROR;
break;
}
/* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ if (pclk != 0U)
{
- brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- huart->Instance->BRR = brrtemp;
- }
- else
- {
- ret = HAL_ERROR;
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ huart->Instance->BRR = brrtemp;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
}
}
else
@@ -3039,35 +3145,37 @@
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_HSI:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) HSI_VALUE;
break;
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
break;
case UART_CLOCKSOURCE_LSE:
- usartdiv = (uint16_t)(UART_DIV_SAMPLING16((uint32_t)LSE_VALUE, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ pclk = (uint32_t) LSE_VALUE;
break;
default:
+ pclk = 0U;
ret = HAL_ERROR;
break;
}
- /* USARTDIV must be greater than or equal to 0d16 */
- if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ if (pclk != 0U)
{
- huart->Instance->BRR = usartdiv;
- }
- else
- {
- ret = HAL_ERROR;
+ /* USARTDIV must be greater than or equal to 0d16 */
+ usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ {
+ huart->Instance->BRR = usartdiv;
+ }
+ else
+ {
+ ret = HAL_ERROR;
+ }
}
}
@@ -3168,7 +3276,7 @@
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
@@ -3196,6 +3304,7 @@
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
__HAL_UNLOCK(huart);
@@ -3240,7 +3349,7 @@
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
-
+
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_TXEIE_TXFNFIE));
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -3248,10 +3357,10 @@
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ErrorCode = HAL_UART_ERROR_RTO;
-
+
/* Process Unlocked */
__HAL_UNLOCK(huart);
-
+
return HAL_TIMEOUT;
}
}
@@ -3260,6 +3369,134 @@
return HAL_OK;
}
+/**
+ * @brief Start Receive operation in interrupt mode.
+ * @note This function could be called by all HAL UART API providing reception in Interrupt mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+ huart->RxISR = NULL;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Configure Rx interrupt processing */
+ if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+ }
+ else
+ {
+ /* Set the Rx ISR function pointer according to the data word length */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ huart->RxISR = UART_RxISR_16BIT;
+ }
+ else
+ {
+ huart->RxISR = UART_RxISR_8BIT;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+ }
+ return HAL_OK;
+}
+
+/**
+ * @brief Start Receive operation in DMA mode.
+ * @note This function could be called by all HAL UART API providing reception in DMA mode.
+ * @note When calling this function, parameters validity is considered as already checked,
+ * i.e. Rx State, buffer address, ...
+ * UART Handle is assumed as Locked.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (u8 or u16 data elements).
+ * @param Size Amount of data elements (u8 or u16) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ huart->pRxBuffPtr = pData;
+ huart->RxXferSize = Size;
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+ if (huart->hdmarx != NULL)
+ {
+ /* Set the UART DMA transfer complete callback */
+ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+ /* Set the UART DMA Half transfer complete callback */
+ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+ /* Set the DMA error callback */
+ huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+ /* Set the DMA abort callback */
+ huart->hdmarx->XferAbortCallback = NULL;
+
+ /* Enable the DMA channel */
+ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ {
+ /* Set error code to DMA */
+ huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+ __HAL_UNLOCK(huart);
+
+ /* Restore huart->gState to ready */
+ huart->gState = HAL_UART_STATE_READY;
+
+ return HAL_ERROR;
+ }
+ }
+ __HAL_UNLOCK(huart);
+
+ /* Enable the UART Parity Error Interrupt */
+ SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+ /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+ SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+ /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+ in the UART CR3 register */
+ SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+ return HAL_OK;
+}
+
/**
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
@@ -3288,8 +3525,15 @@
CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
@@ -3372,15 +3616,37 @@
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+
+ /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
}
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
}
/**
@@ -3392,13 +3658,29 @@
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : use Rx Event callback */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx Half complete callback*/
- huart->RxHalfCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize/2U);
#else
- /*Call legacy weak Rx Half complete callback*/
- HAL_UART_RxHalfCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ else
+ {
+ /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx Half complete callback*/
+ huart->RxHalfCpltCallback(huart);
+#else
+ /*Call legacy weak Rx Half complete callback*/
+ HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
}
/**
@@ -3503,6 +3785,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Call user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -3554,6 +3837,7 @@
/* Restore huart->gState and huart->RxState to Ready */
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Call user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -3621,6 +3905,7 @@
/* Restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
/* Call user Abort complete callback */
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
@@ -3633,7 +3918,7 @@
}
/**
- * @brief TX interrrupt handler for 7 or 8 bits data word length .
+ * @brief TX interrupt handler for 7 or 8 bits data word length .
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
@@ -3662,7 +3947,7 @@
}
/**
- * @brief TX interrrupt handler for 9 bits data word length.
+ * @brief TX interrupt handler for 9 bits data word length.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
@@ -3694,7 +3979,7 @@
}
/**
- * @brief TX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
@@ -3734,7 +4019,7 @@
}
/**
- * @brief TX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Transmit_IT().
* @param huart UART handle.
@@ -3802,7 +4087,7 @@
}
/**
- * @brief RX interrrupt handler for 7 or 8 bits data word length .
+ * @brief RX interrupt handler for 7 or 8 bits data word length .
* @param huart UART handle.
* @retval None
*/
@@ -3833,13 +4118,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -3850,7 +4155,7 @@
}
/**
- * @brief RX interrrupt handler for 9 bits data word length .
+ * @brief RX interrupt handler for 9 bits data word length .
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
@@ -3885,13 +4190,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
else
@@ -3902,7 +4227,7 @@
}
/**
- * @brief RX interrrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+ * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
@@ -3912,18 +4237,66 @@
{
uint16_t uhMask = huart->Mask;
uint16_t uhdata;
- uint16_t nb_rx_data;
+ uint16_t nb_rx_data;
uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
huart->pRxBuffPtr++;
huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
if (huart->RxXferCount == 0U)
{
@@ -3939,13 +4312,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
@@ -3974,7 +4367,7 @@
}
/**
- * @brief RX interrrupt handler for 9 bits data word length and FIFO mode is enabled.
+ * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
* @note Function is called under interruption only, once
* interruptions have been enabled by HAL_UART_Receive_IT()
* @param huart UART handle.
@@ -3985,19 +4378,67 @@
uint16_t *tmp;
uint16_t uhMask = huart->Mask;
uint16_t uhdata;
- uint16_t nb_rx_data;
+ uint16_t nb_rx_data;
uint16_t rxdatacount;
+ uint32_t isrflags = READ_REG(huart->Instance->ISR);
+ uint32_t cr1its = READ_REG(huart->Instance->CR1);
+ uint32_t cr3its = READ_REG(huart->Instance->CR3);
/* Check that a Rx process is ongoing */
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
{
- for (nb_rx_data = huart->NbRxDataToProcess ; nb_rx_data > 0U ; nb_rx_data--)
+ nb_rx_data = huart->NbRxDataToProcess;
+ while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
{
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
tmp = (uint16_t *) huart->pRxBuffPtr ;
*tmp = (uint16_t)(uhdata & uhMask);
huart->pRxBuffPtr += 2U;
huart->RxXferCount--;
+ isrflags = READ_REG(huart->Instance->ISR);
+
+ /* If some non blocking errors occurred */
+ if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+ {
+ /* UART parity error interrupt occurred -------------------------------------*/
+ if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_PE;
+ }
+
+ /* UART frame error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_FE;
+ }
+
+ /* UART noise error interrupt occurred --------------------------------------*/
+ if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+ huart->ErrorCode |= HAL_UART_ERROR_NE;
+ }
+
+ /* Call UART Error Call back function if need be ----------------------------*/
+ if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ {
+ /* Non Blocking error : transfer could go on.
+ Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered error callback*/
+ huart->ErrorCallback(huart);
+#else
+ /*Call legacy weak error callback*/
+ HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ }
+ }
if (huart->RxXferCount == 0U)
{
@@ -4013,13 +4454,33 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Check current reception Mode :
+ If Reception till IDLE event has been selected : */
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ /* Disable IDLE interrupt */
+ CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
- /*Call registered Rx complete callback*/
- huart->RxCpltCallback(huart);
+ /*Call registered Rx Event callback*/
+ huart->RxEventCallback(huart, huart->RxXferSize);
#else
- /*Call legacy weak Rx complete callback*/
- HAL_UART_RxCpltCallback(huart);
+ /*Call legacy weak Rx Event callback*/
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif
+ }
+ else
+ {
+ /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+ /*Call registered Rx complete callback*/
+ huart->RxCpltCallback(huart);
+#else
+ /*Call legacy weak Rx complete callback*/
+ HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+ }
+ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
}
}
diff --git a/Src/stm32l5xx_hal_uart_ex.c b/Src/stm32l5xx_hal_uart_ex.c
index f3cc004..aa75591 100644
--- a/Src/stm32l5xx_hal_uart_ex.c
+++ b/Src/stm32l5xx_hal_uart_ex.c
@@ -332,6 +332,41 @@
(+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
(+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+ [..] This subsection also provides a set of additional functions providing enhanced reception
+ services to user. (For example, these functions allow application to handle use cases
+ where number of data to be received is unknown).
+
+ (#) Compared to standard reception services which only consider number of received
+ data elements as reception completion criteria, these functions also consider additional events
+ as triggers for updating reception status to caller :
+ (+) Detection of inactivity period (RX line has not been active for a given period).
+ (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+ for 1 frame time, after last received byte.
+ (++) RX inactivity detected by RTO, i.e. line has been in idle state
+ for a programmable time, after last received byte.
+ (+) Detection that a specific character has been received.
+
+ (#) There are two mode of transfer:
+ (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+ or till IDLE event occurs. Reception is handled only during function execution.
+ When function exits, no data reception could occur. HAL status and number of actually received data elements,
+ are returned by function after finishing transfer.
+ (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+ These API's return the HAL status.
+ The end of the data processing will be indicated through the
+ dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+ The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+ The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+ (#) Blocking mode API:
+ (+) HAL_UARTEx_ReceiveToIdle()
+
+ (#) Non-Blocking mode API with Interrupt:
+ (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+ (#) Non-Blocking mode API with DMA:
+ (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
@endverbatim
* @{
*/
@@ -416,7 +451,7 @@
/* Enable the Peripheral */
__HAL_UART_ENABLE(huart);
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Wait until REACK flag is set */
@@ -653,6 +688,254 @@
}
/**
+ * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
+ * @note HAL_OK is returned if reception is completed (expected number of data has been received)
+ * or if reception is stopped after IDLE event (less than the expected number of data has been received)
+ * In this case, RxLen output parameter indicates number of data available in reception buffer.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+ * is not empty. Read operations from the RDR register are performed when
+ * RXFNE flag is set. From hardware perspective, RXFNE flag and
+ * RXNE are mapped on the same bit-field.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
+ * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)
+{
+ uint8_t *pdata8bits;
+ uint16_t *pdata16bits;
+ uint16_t uhMask;
+ uint32_t tickstart;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ huart->ErrorCode = HAL_UART_ERROR_NONE;
+ huart->RxState = HAL_UART_STATE_BUSY_RX;
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ /* Init tickstart for timeout management */
+ tickstart = HAL_GetTick();
+
+ huart->RxXferSize = Size;
+ huart->RxXferCount = Size;
+
+ /* Computation of UART mask to apply to RDR register */
+ UART_MASK_COMPUTATION(huart);
+ uhMask = huart->Mask;
+
+ /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ {
+ pdata8bits = NULL;
+ pdata16bits = (uint16_t *) pData;
+ }
+ else
+ {
+ pdata8bits = pData;
+ pdata16bits = NULL;
+ }
+
+ __HAL_UNLOCK(huart);
+
+ /* Initialize output number of received elements */
+ *RxLen = 0U;
+
+ /* as long as data have to be received */
+ while (huart->RxXferCount > 0U)
+ {
+ /* Check if IDLE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+ {
+ /* Clear IDLE flag in ISR */
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+ /* If Set, but no data ever received, clear flag without exiting loop */
+ /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+ if (*RxLen > 0U)
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ }
+
+ /* Check if RXNE flag is set */
+ if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+ {
+ if (pdata8bits == NULL)
+ {
+ *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+ pdata16bits++;
+ }
+ else
+ {
+ *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+ pdata8bits++;
+ }
+ /* Increment number of received elements */
+ *RxLen += 1U;
+ huart->RxXferCount--;
+ }
+
+ /* Check for the Timeout */
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+ {
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set number of received elements in output parameter : RxLen */
+ *RxLen = huart->RxXferSize - huart->RxXferCount;
+ /* At end of Rx process, restore huart->RxState to Ready */
+ huart->RxState = HAL_UART_STATE_READY;
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+ * number of received data elements.
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_IT(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
+ * @note Reception is initiated by this function call. Further progress of reception is achieved thanks
+ * to DMA services, transferring automatically received data elements in user reception buffer and
+ * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+ * reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+ * @note When the UART parity is enabled (PCE = 1), the received data contain
+ * the parity bit (MSB position).
+ * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+ * of uint16_t available through pData.
+ * @param huart UART handle.
+ * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+ * @param Size Amount of data elements (uint8_t or uint16_t) to be received.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+ HAL_StatusTypeDef status;
+
+ /* Check that a Rx process is not already ongoing */
+ if (huart->RxState == HAL_UART_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
+ {
+ return HAL_ERROR;
+ }
+
+ __HAL_LOCK(huart);
+
+ /* Set Reception type to reception till IDLE Event*/
+ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+ status = UART_Start_Receive_DMA(huart, pData, Size);
+
+ /* Check Rx process has been successfully started */
+ if (status == HAL_OK)
+ {
+ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ {
+ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ }
+ else
+ {
+ /* In case of errors already pending when reception is started,
+ Interrupts may have already been raised and lead to reception abortion.
+ (Overrun error for instance).
+ In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+ status = HAL_ERROR;
+ }
+ }
+
+ return status;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
* @}
*/
diff --git a/Src/stm32l5xx_hal_usart.c b/Src/stm32l5xx_hal_usart.c
index 8828048..848ee95 100644
--- a/Src/stm32l5xx_hal_usart.c
+++ b/Src/stm32l5xx_hal_usart.c
@@ -39,7 +39,8 @@
(+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
(+++) Configure the DMA Tx/Rx channel.
(+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle.
- (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+ (+++) Configure the priority and enable the NVIC for the transfer
+ complete interrupt on the DMA Tx/Rx channel.
(#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode
(Receiver/Transmitter) in the husart handle Init structure.
@@ -532,9 +533,9 @@
}
/**
- * @brief Unregister an UART Callback
- * UART callaback is redirected to the weak predefined callback
- * @param husart uart handle
+ * @brief Unregister an USART Callback
+ * USART callaback is redirected to the weak predefined callback
+ * @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
* @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
@@ -562,47 +563,47 @@
switch (CallbackID)
{
case HAL_USART_TX_HALFCOMPLETE_CB_ID :
- husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
+ husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
break;
case HAL_USART_TX_COMPLETE_CB_ID :
- husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
+ husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */
break;
case HAL_USART_RX_HALFCOMPLETE_CB_ID :
- husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
+ husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
break;
case HAL_USART_RX_COMPLETE_CB_ID :
- husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
+ husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */
break;
case HAL_USART_TX_RX_COMPLETE_CB_ID :
- husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
+ husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
break;
case HAL_USART_ERROR_CB_ID :
- husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
+ husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */
break;
case HAL_USART_ABORT_COMPLETE_CB_ID :
- husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
+ husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
break;
case HAL_USART_RX_FIFO_FULL_CB_ID :
- husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
+ husart->RxFifoFullCallback = HAL_USARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */
break;
case HAL_USART_TX_FIFO_EMPTY_CB_ID :
- husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
+ husart->TxFifoEmptyCallback = HAL_USARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */
break;
case HAL_USART_MSPINIT_CB_ID :
- husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
+ husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */
break;
case HAL_USART_MSPDEINIT_CB_ID :
- husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
+ husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */
break;
default :
@@ -721,13 +722,16 @@
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
Errors are handled as follows :
(++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
- to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
- Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
- and HAL_USART_ErrorCallback() user callback is executed. Transfer is kept ongoing on USART side.
+ to be evaluated by user : this concerns Frame Error,
+ Parity Error or Noise Error in Interrupt mode reception .
+ Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify
+ error type, and HAL_USART_ErrorCallback() user callback is executed.
+ Transfer is kept ongoing on USART side.
If user wants to abort it, Abort services should be called by user.
(++) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
- Error code is set to allow user to identify error type, and HAL_USART_ErrorCallback() user callback is executed.
+ Error code is set to allow user to identify error type,
+ and HAL_USART_ErrorCallback() user callback is executed.
@endverbatim
* @{
@@ -735,7 +739,7 @@
/**
* @brief Simplex send an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -763,7 +767,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_TX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->TxXferSize = Size;
@@ -832,7 +836,7 @@
/**
* @brief Receive an amount of data in blocking mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -861,7 +865,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@@ -943,7 +947,7 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -977,7 +981,7 @@
husart->ErrorCode = HAL_USART_ERROR_NONE;
husart->State = HAL_USART_STATE_BUSY_RX;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
husart->RxXferSize = Size;
@@ -1092,7 +1096,7 @@
/**
* @brief Send an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -1175,7 +1179,7 @@
/**
* @brief Receive an amount of data in interrupt mode.
* @note To receive synchronous data, dummy data are simultaneously transmitted.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -1278,7 +1282,7 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -1377,7 +1381,7 @@
/**
* @brief Send an amount of data in DMA mode.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must indicate the number
* of u16 provided through pTxData.
* @param husart USART handle.
@@ -1462,7 +1466,7 @@
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position).
* @note The USART DMA transmit channel must be configured in order to generate the clock for the slave.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must indicate the number
* of u16 available through pRxData.
* @param husart USART handle.
@@ -1578,7 +1582,7 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
- * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+ * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number
* of u16 available through pTxData and through pRxData.
* @param husart USART handle.
@@ -1769,7 +1773,7 @@
/* Clear the Overrun flag before resuming the Rx transfer*/
__HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF);
- /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+ /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
SET_BIT(husart->Instance->CR1, USART_CR1_PEIE);
SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
@@ -2092,7 +2096,8 @@
uint32_t errorcode;
/* If no error occurs */
- errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF | USART_ISR_UDR));
+ errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF |
+ USART_ISR_UDR));
if (errorflags == 0U)
{
/* USART in mode Receiver ---------------------------------------------------*/
@@ -2952,7 +2957,7 @@
/* Initialize the USART ErrorCode */
husart->ErrorCode = HAL_USART_ERROR_NONE;
- /* Init tickstart for timeout managment*/
+ /* Init tickstart for timeout management */
tickstart = HAL_GetTick();
/* Check if the Transmitter is enabled */
@@ -3421,7 +3426,8 @@
/* Disable the USART Parity Error Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Clear RxISR function pointer */
@@ -3555,7 +3561,8 @@
/* Disable the USART Parity Error Interrupt */
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
- /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+ /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error)
+ and RX FIFO Threshold interrupt */
CLEAR_BIT(husart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
/* Clear RxISR function pointer */
diff --git a/Src/stm32l5xx_hal_usart_ex.c b/Src/stm32l5xx_hal_usart_ex.c
index f829fcd..597cdee 100644
--- a/Src/stm32l5xx_hal_usart_ex.c
+++ b/Src/stm32l5xx_hal_usart_ex.c
@@ -515,10 +515,14 @@
{
rx_fifo_depth = RX_FIFO_DEPTH;
tx_fifo_depth = TX_FIFO_DEPTH;
- rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
- tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
- husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold];
- husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold];
+ rx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos) & 0xFFU);
+ tx_fifo_threshold = (uint8_t)((READ_BIT(husart->Instance->CR3,
+ USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos) & 0xFFU);
+ husart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ (uint16_t)denominator[tx_fifo_threshold];
+ husart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+ (uint16_t)denominator[rx_fifo_threshold];
}
}
/**
diff --git a/Src/stm32l5xx_hal_wwdg.c b/Src/stm32l5xx_hal_wwdg.c
index d776434..b1e0ff3 100644
--- a/Src/stm32l5xx_hal_wwdg.c
+++ b/Src/stm32l5xx_hal_wwdg.c
@@ -32,10 +32,10 @@
(++) min time (mS) = 1000 * (Counter - Window) / WWDG clock
(++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock
(+) Typical values:
- (++) Counter min (T[5;0] = 0x00) @56MHz (PCLK1) with zero prescaler:
- max timeout before reset: ~73.14µs
- (++) Counter max (T[5;0] = 0x3F) @56MHz (PCLK1) with prescaler dividing by 128:
- max timeout before reset: ~599.18ms
+ (++) Counter min (T[5;0] = 0x00) @110MHz (PCLK1) with zero prescaler:
+ max timeout before reset: ~37.23µs
+ (++) Counter max (T[5;0] = 0x3F) @110MHz (PCLK1) with prescaler dividing by 128:
+ max timeout before reset: ~19.07ms
==============================================================================
##### How to use this driver #####
@@ -198,7 +198,7 @@
#else
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
@@ -243,7 +243,8 @@
* @param pCallback pointer to the Callback function
* @retval status
*/
-HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
+ pWWDG_CallbackTypeDef pCallback)
{
HAL_StatusTypeDef status = HAL_OK;
@@ -304,7 +305,7 @@
return status;
}
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
@@ -372,7 +373,7 @@
#else
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
-#endif
+#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
}
}
}
diff --git a/Src/stm32l5xx_ll_adc.c b/Src/stm32l5xx_ll_adc.c
index 7511b65..195558e 100644
--- a/Src/stm32l5xx_ll_adc.c
+++ b/Src/stm32l5xx_ll_adc.c
@@ -81,7 +81,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
- ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
+ (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
@@ -101,26 +101,26 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
- ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
+ (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
)
#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
- ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
+ (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
)
#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
- ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
+ (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group regular */
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
- ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
+ (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
@@ -140,23 +140,23 @@
)
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
- ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
+ (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
)
#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
- ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
+ (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
)
#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
- ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
+ (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
|| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
)
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
- ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
+ (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
@@ -175,7 +175,7 @@
)
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
- ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
+ (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
@@ -189,7 +189,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group injected */
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
- ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
+ (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
@@ -209,25 +209,25 @@
)
#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
- ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
+ (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
)
#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
- ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
+ (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
|| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
- ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
+ (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
- ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
+ (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
|| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
)
@@ -235,7 +235,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* multimode. */
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
- ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
+ (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
@@ -246,7 +246,7 @@
)
#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
- ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
+ (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
@@ -254,7 +254,7 @@
)
#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
- ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
+ (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
@@ -269,7 +269,7 @@
)
#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
- ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
+ (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
)
@@ -296,7 +296,7 @@
* the same ADC common instance to their default reset values.
* @note This function is performing a hard reset, using high level
* clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
+ * Caution: On this STM32 series, if several ADC instances are available
* on the selected device, RCC ADC reset will reset
* all ADC instances belonging to the common ADC instance.
* To de-initialize only 1 ADC instance, use
@@ -355,7 +355,7 @@
/* Note: Hardware constraint (refer to description of functions */
/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
- /* On this STM32 serie, setting of these features is conditioned to */
+ /* On this STM32 series, setting of these features is conditioned to */
/* ADC state: */
/* All ADC instances of the ADC common group must be disabled. */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
@@ -442,7 +442,7 @@
* is in an unknown state.
* In this case, perform a hard reset using high level
* clock source RCC ADC reset.
- * Caution: On this STM32 serie, if several ADC instances are available
+ * Caution: On this STM32 series, if several ADC instances are available
* on the selected device, RCC ADC reset will reset
* all ADC instances belonging to the common ADC instance.
* Refer to function @ref LL_ADC_CommonDeInit().
@@ -681,10 +681,10 @@
/* ADC instance is in an unknown state */
/* Need to performing a hard reset of ADC instance, using high level */
/* clock source RCC ADC reset. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* Caution: On this STM32 series, if several ADC instances are available */
/* on the selected device, RCC ADC reset will reset */
/* all ADC instances belonging to the common ADC instance. */
- /* Caution: On this STM32 serie, if several ADC instances are available */
+ /* Caution: On this STM32 series, if several ADC instances are available */
/* on the selected device, RCC ADC reset will reset */
/* all ADC instances belonging to the common ADC instance. */
status = ERROR;
@@ -762,6 +762,7 @@
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
+
return status;
}
@@ -842,7 +843,7 @@
/* - Set ADC group regular conversion data transfer: no transfer or */
/* transfer by DMA, and DMA requests mode */
/* - Set ADC group regular overrun behavior */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
@@ -904,7 +905,7 @@
{
/* Set ADC_REG_InitStruct fields to default values */
/* Set fields of ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
@@ -971,7 +972,7 @@
/* - Set ADC group injected sequencer discontinuous mode */
/* - Set ADC group injected conversion trigger: independent or */
/* from ADC group regular */
- /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
+ /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
diff --git a/Src/stm32l5xx_ll_fmc.c b/Src/stm32l5xx_ll_fmc.c
index f16b637..220210f 100644
--- a/Src/stm32l5xx_ll_fmc.c
+++ b/Src/stm32l5xx_ll_fmc.c
@@ -16,7 +16,7 @@
==============================================================================
[..] The Flexible memory controller (FMC) includes following memory controllers:
(+) The NOR/PSRAM memory controller
- (+) The NAND memory controller
+ (+) The NAND memory controller
[..] The FMC functional block makes the interface with synchronous and asynchronous static
memories. Its main purposes are:
@@ -64,7 +64,7 @@
* @brief FMC driver modules
* @{
*/
-
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -175,7 +175,8 @@
* @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
+HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_InitTypeDef *Init)
{
uint32_t flashaccess;
uint32_t btcr_reg;
@@ -266,7 +267,7 @@
}
/* Check PSRAM chip select counter state */
- if(Init->MaxChipSelectPulse == ENABLE)
+ if (Init->MaxChipSelectPulse == ENABLE)
{
/* Check the parameters */
assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime));
@@ -308,7 +309,8 @@
* @param Bank NORSRAM bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
+HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_DEVICE(Device));
@@ -334,27 +336,27 @@
ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
/* De-initialize PSRAM chip select counter */
- switch (Bank)
- {
- case FMC_NORSRAM_BANK1 :
- CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
- break;
+ switch (Bank)
+ {
+ case FMC_NORSRAM_BANK1 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN);
+ break;
- case FMC_NORSRAM_BANK2 :
- CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
- break;
+ case FMC_NORSRAM_BANK2 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN);
+ break;
- case FMC_NORSRAM_BANK3 :
- CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
- break;
+ case FMC_NORSRAM_BANK3 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN);
+ break;
- case FMC_NORSRAM_BANK4 :
- CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
- break;
+ case FMC_NORSRAM_BANK4 :
+ CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN);
+ break;
- default :
- break;
- }
+ default :
+ break;
+ }
return HAL_OK;
}
@@ -367,7 +369,8 @@
* @param Bank NORSRAM bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
{
uint32_t tmpr;
@@ -385,13 +388,13 @@
/* Set FMC_NORSRAM device timing parameters */
MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime |
- ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
- ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
- ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
- ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
- (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
- (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
- (Timing->AccessMode)));
+ ((Timing->AddressHoldTime) << FMC_BTRx_ADDHLD_Pos) |
+ ((Timing->DataSetupTime) << FMC_BTRx_DATAST_Pos) |
+ ((Timing->DataHoldTime) << FMC_BTRx_DATAHLD_Pos) |
+ ((Timing->BusTurnAroundDuration) << FMC_BTRx_BUSTURN_Pos) |
+ (((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos) |
+ (((Timing->DataLatency) - 2U) << FMC_BTRx_DATLAT_Pos) |
+ (Timing->AccessMode)));
/* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
@@ -416,7 +419,8 @@
* @arg FMC_EXTENDED_MODE_ENABLE
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
+HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
+ FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
{
/* Check the parameters */
assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
@@ -460,8 +464,8 @@
*/
/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
- * @brief management functions
- *
+ * @brief management functions
+ *
@verbatim
==============================================================================
##### FMC_NORSRAM Control functions #####
@@ -545,8 +549,8 @@
*/
/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
- *
+ * @brief Initialization and Configuration functions
+ *
@verbatim
==============================================================================
##### Initialization and de_initialization functions #####
@@ -600,7 +604,8 @@
* @param Bank NAND bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -630,7 +635,8 @@
* @param Bank NAND bank number
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
+HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
+ FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
{
/* Check the parameters */
assert_param(IS_FMC_NAND_DEVICE(Device));
@@ -751,7 +757,8 @@
* @param Timeout Timeout wait value
* @retval HAL status
*/
-HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
+HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
+ uint32_t Timeout)
{
uint32_t tickstart;
@@ -802,5 +809,8 @@
/**
* @}
*/
+/**
+ * @}
+ */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/Src/stm32l5xx_ll_lptim.c b/Src/stm32l5xx_ll_lptim.c
index 98365ad..c6c00f2 100644
--- a/Src/stm32l5xx_ll_lptim.c
+++ b/Src/stm32l5xx_ll_lptim.c
@@ -211,17 +211,17 @@
/* Save LPTIM source clock */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
- break;
- case LPTIM2_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
- break;
- case LPTIM3_BASE:
- tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
+ break;
+ case LPTIM2_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
+ break;
+ case LPTIM3_BASE:
+ tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE);
+ break;
+ default:
+ break;
}
/* Save LPTIM configuration registers */
@@ -243,17 +243,17 @@
/* Force LPTIM source kernel clock from APB */
switch ((uint32_t)LPTIMx)
{
- case LPTIM1_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
- break;
- case LPTIM2_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1);
- break;
- case LPTIM3_BASE:
- LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK1);
- break;
- default:
- break;
+ case LPTIM1_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1);
+ break;
+ case LPTIM2_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE_PCLK1);
+ break;
+ case LPTIM3_BASE:
+ LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE_PCLK1);
+ break;
+ default:
+ break;
}
if (tmpCMP != 0UL)
@@ -266,7 +266,8 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_CMPOK(LPTIMx);
}
@@ -281,7 +282,8 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}
@@ -296,7 +298,8 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- } while (((LL_LPTIM_IsActiveFlag_REPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ }
+ while (((LL_LPTIM_IsActiveFlag_REPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_REPOK(LPTIMx);
}
diff --git a/Src/stm32l5xx_ll_rng.c b/Src/stm32l5xx_ll_rng.c
index 030ed4e..a9b9739 100644
--- a/Src/stm32l5xx_ll_rng.c
+++ b/Src/stm32l5xx_ll_rng.c
@@ -26,7 +26,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32L5xx_LL_Driver
* @{
@@ -52,7 +52,7 @@
#define IS_LL_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == LL_RNG_NIST_COMPLIANT) || \
- ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT))
+ ((__NIST_COMPLIANCE__) == LL_RNG_NOTNIST_COMPLIANT))
#define IS_LL_RNG_CONFIG1 (__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
diff --git a/Src/stm32l5xx_ll_sdmmc.c b/Src/stm32l5xx_ll_sdmmc.c
index fcf87ce..7975f91 100644
--- a/Src/stm32l5xx_ll_sdmmc.c
+++ b/Src/stm32l5xx_ll_sdmmc.c
@@ -170,11 +170,6 @@
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout);
-static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx);
-static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA);
/* Exported functions --------------------------------------------------------*/
@@ -511,7 +506,7 @@
*/
/**
- * @brief Send the Data Block Lenght command and check the response
+ * @brief Send the Data Block Length command and check the response
* @param SDMMCx: Pointer to SDMMC register base
* @retval HAL status
*/
@@ -1040,6 +1035,31 @@
}
/**
+ * @brief Send the Set Relative Address command to MMC card (not SD card).
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param RCA Card RCA
+ * @retval HAL status
+ */
+uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA)
+{
+ SDMMC_CmdInitTypeDef sdmmc_cmdinit;
+ uint32_t errorstate;
+
+ /* Send CMD3 SD_CMD_SET_REL_ADDR */
+ sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U);
+ sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR;
+ sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT;
+ sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO;
+ sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE;
+ (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit);
+
+ /* Check for error conditions */
+ errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT);
+
+ return errorstate;
+}
+
+/**
* @brief Send the Status command and check the response.
* @param SDMMCx: Pointer to SDMMC register base
* @param Argument: Command Argument
@@ -1112,7 +1132,7 @@
}
/**
- * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
+ * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command
* @param SDMMCx: Pointer to SDMMC register base
* @parame Argument: Argument used for the command
* @retval HAL status
@@ -1186,56 +1206,38 @@
return errorstate;
}
-
/**
* @}
*/
-/* Private function ----------------------------------------------------------*/
-/** @addtogroup SD_Private_Functions
+
+/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions
+ * @brief Responses functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Responses management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the needed responses.
+
+@endverbatim
* @{
*/
-
-/**
- * @brief Checks for error conditions for CMD0.
- * @param hsd: SD handle
- * @retval SD Card error state
- */
-static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
-{
- /* 8 is the number of required instructions cycles for the below loop statement.
- The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
-
- do
- {
- if (count-- == 0U)
- {
- return SDMMC_ERROR_TIMEOUT;
- }
-
- }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
-
- /* Clear all the static flags */
- __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
-
- return SDMMC_ERROR_NONE;
-}
-
/**
* @brief Checks for error conditions for R1 response.
* @param hsd: SD handle
* @param SD_CMD: The sent command index
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
+uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
{
uint32_t response_r1;
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The Timeout is expressed in ms */
- register uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
+ uint32_t count = Timeout * (SystemCoreClock / 8U /1000U);
do
{
@@ -1363,12 +1365,12 @@
* @param hsd: SD handle
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
{
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
@@ -1407,12 +1409,12 @@
* @param hsd: SD handle
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
{
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
@@ -1447,14 +1449,14 @@
* address RCA
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
+uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA)
{
uint32_t response_r1;
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
@@ -1520,12 +1522,12 @@
* @param hsd: SD handle
* @retval SD Card error state
*/
-static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
+uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
{
uint32_t sta_reg;
/* 8 is the number of required instructions cycles for the below loop statement.
The SDMMC_CMDTIMEOUT is expressed in ms */
- register uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
do
{
@@ -1571,6 +1573,41 @@
* @}
*/
+/* Private function ----------------------------------------------------------*/
+/** @addtogroup SD_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Checks for error conditions for CMD0.
+ * @param hsd: SD handle
+ * @retval SD Card error state
+ */
+static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
+{
+ /* 8 is the number of required instructions cycles for the below loop statement.
+ The SDMMC_CMDTIMEOUT is expressed in ms */
+ uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U);
+
+ do
+ {
+ if (count-- == 0U)
+ {
+ return SDMMC_ERROR_TIMEOUT;
+ }
+
+ }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT));
+
+ /* Clear all the static flags */
+ __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS);
+
+ return SDMMC_ERROR_NONE;
+}
+
+/**
+ * @}
+ */
+
#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */
/**
* @}
diff --git a/Src/stm32l5xx_ll_ucpd.c b/Src/stm32l5xx_ll_ucpd.c
index 9ee0da4..5417077 100644
--- a/Src/stm32l5xx_ll_ucpd.c
+++ b/Src/stm32l5xx_ll_ucpd.c
@@ -94,7 +94,7 @@
/* Release reset of ucpd clock */
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1);
- /* Disbale ucpd clock */
+ /* Disable ucpd clock */
LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1);
status = SUCCESS;
@@ -143,10 +143,10 @@
void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct)
{
/* Set UCPD_InitStruct fields to default values */
- UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV1;
+ UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV2;
UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */
UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */
- UCPD_InitStruct->HbitClockDiv = 0x1A; /* Divide by 27 to produce HBITCLK */
+ UCPD_InitStruct->HbitClockDiv = 0x0D; /* Divide by 14 to produce HBITCLK */
}
/**
diff --git a/Src/stm32l5xx_ll_usart.c b/Src/stm32l5xx_ll_usart.c
index 40bb756..36001d3 100644
--- a/Src/stm32l5xx_ll_usart.c
+++ b/Src/stm32l5xx_ll_usart.c
@@ -187,8 +187,9 @@
/**
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
@@ -239,7 +240,8 @@
/*---------------------------- USART CR3 Configuration ---------------------
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
- * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
+ * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
+ * USART_InitStruct->HardwareFlowControl value.
*/
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
@@ -327,13 +329,15 @@
/**
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
- * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
- * USART Peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
+ * @note As some bits in USART configuration registers can only be written when
+ * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
+ * this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
- * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
+ * - SUCCESS: USART registers related to Clock settings are initialized according
+ * to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
@@ -399,9 +403,12 @@
{
/* Set LL_USART_ClockInitStruct fields with default values */
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
- USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
- USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
+ USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
+ LL_USART_CLOCK_DISABLE */
}
/**
diff --git a/Src/stm32l5xx_ll_usb.c b/Src/stm32l5xx_ll_usb.c
index 1bad891..c6a748f 100644
--- a/Src/stm32l5xx_ll_usb.c
+++ b/Src/stm32l5xx_ll_usb.c
@@ -85,6 +85,9 @@
{
uint32_t winterruptmask;
+ /* Clear pending interrupts */
+ USBx->ISTR = 0U;
+
/* Set winterruptmask variable */
winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
USB_CNTR_SUSPM | USB_CNTR_ERRM |
@@ -92,7 +95,7 @@
USB_CNTR_RESETM | USB_CNTR_L1REQM;
/* Set interrupt mask */
- USBx->CNTR |= (uint16_t)winterruptmask;
+ USBx->CNTR = (uint16_t)winterruptmask;
return HAL_OK;
}
@@ -102,7 +105,7 @@
* Disable the controller's Global Int in the AHB Config reg
* @param USBx : Selected device
* @retval HAL status
-*/
+ */
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx)
{
uint32_t winterruptmask;
@@ -124,7 +127,7 @@
* @param USBx : Selected device
* @param mode : current core mode
* This parameter can be one of the these values:
- * @arg USB_DEVICE_MODE: Peripheral mode mode
+ * @arg USB_DEVICE_MODE: Peripheral mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode)
@@ -166,9 +169,6 @@
/*Set Btable Address*/
USBx->BTABLE = BTABLE_ADDRESS;
- /* Enable USB Device Interrupt mask */
- (void)USB_EnableGlobalInt(USBx);
-
return HAL_OK;
}
@@ -318,9 +318,6 @@
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
- /* Reset value of the data toggle bits for the endpoint out */
- PCD_TX_DTOG(USBx, ep->num);
-
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS);
}
@@ -329,7 +326,7 @@
/* Clear the data toggle bits for the endpoint IN/OUT */
PCD_CLEAR_RX_DTOG(USBx, ep->num);
PCD_CLEAR_TX_DTOG(USBx, ep->num);
- PCD_RX_DTOG(USBx, ep->num);
+
if (ep->type != EP_TYPE_ISOC)
{
@@ -412,20 +409,19 @@
{
uint16_t pmabuffer;
uint32_t len;
+ uint16_t wEPVal;
/* IN endpoint */
if (ep->is_in == 1U)
{
- /*Multi packet transfer*/
+ /* Multi packet transfer */
if (ep->xfer_len > ep->maxpacket)
{
len = ep->maxpacket;
- ep->xfer_len -= len;
}
else
{
len = ep->xfer_len;
- ep->xfer_len = 0U;
}
/* configure and validate Tx endpoint */
@@ -436,49 +432,171 @@
}
else
{
- /* Write the data to the USB endpoint */
- if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+ /* double buffer bulk management */
+ if (ep->type == EP_TYPE_BULK)
{
- /* Set the Double buffer counter for pmabuffer1 */
- PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr1;
- }
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ /* enable double buffer */
+ PCD_SET_EP_DBUF(USBx, ep->num);
+
+ /* each Time to write in PMA xfer_len_db will */
+ ep->xfer_len_db -= len;
+
+ /* Fill the two first buffer in the Buffer0 & Buffer1 */
+ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ else
+ {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ ep->xfer_buff += len;
+
+ if (ep->xfer_len_db > ep->maxpacket)
+ {
+ ep->xfer_len_db -= len;
+ }
+ else
+ {
+ len = ep->xfer_len_db;
+ ep->xfer_len_db = 0U;
+ }
+
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ }
+ /* auto Switch to single buffer mode when transfer <Mps no need to manage in double buffer*/
+ else
+ {
+ len = ep->xfer_len_db;
+ /* disable double buffer mode */
+ PCD_CLEAR_EP_DBUF(USBx, ep->num);
+
+ /* Set Tx count with nbre of byte to be transmitted */
+ PCD_SET_EP_TX_CNT(USBx, ep->num, len);
+ pmabuffer = ep->pmaaddr0;
+
+ /* Write the user buffer to USB PMA */
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ }
+ }/* end if bulk double buffer */
+
+ /* manage isochronous double buffer IN mode */
else
{
- /* Set the Double buffer counter for pmabuffer0 */
- PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
- pmabuffer = ep->pmaaddr0;
+ /* Write the data to the USB endpoint */
+ if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U)
+ {
+ /* Set the Double buffer counter for pmabuffer1 */
+ PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr1;
+ }
+ else
+ {
+ /* Set the Double buffer counter for pmabuffer0 */
+ PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len);
+ pmabuffer = ep->pmaaddr0;
+ }
+ USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
+ PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
}
- USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len);
- PCD_FreeUserBuffer(USBx, ep->num, ep->is_in);
}
PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID);
}
else /* OUT endpoint */
{
- /* Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket)
- {
- len = ep->maxpacket;
- ep->xfer_len -= len;
- }
- else
- {
- len = ep->xfer_len;
- ep->xfer_len = 0U;
- }
-
- /* configure and validate Rx endpoint */
if (ep->doublebuffer == 0U)
{
+ /* Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ ep->xfer_len -= len;
+ }
+ else
+ {
+ len = ep->xfer_len;
+ ep->xfer_len = 0U;
+ }
+ /* configure and validate Rx endpoint */
/*Set RX buffer count*/
PCD_SET_EP_RX_CNT(USBx, ep->num, len);
}
else
{
+ /*First Transfer Coming From HAL_PCD_EP_Receive & From ISR*/
/*Set the Double buffer counter*/
- PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
+ if (ep->type == EP_TYPE_BULK)
+ {
+ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket);
+ /*Coming from ISR*/
+ if (ep->xfer_count != 0U)
+ {
+ /* update last value to check if there is blocking state*/
+ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num);
+ /*Blocking State */
+ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) ||
+ (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U)))
+ {
+ PCD_FreeUserBuffer(USBx, ep->num, 0U);
+ }
+ }
+ }
+ /*iso out double */
+ else if (ep->type == EP_TYPE_ISOC)
+ {
+ /* Multi packet transfer*/
+ if (ep->xfer_len > ep->maxpacket)
+ {
+ len = ep->maxpacket;
+ ep->xfer_len -= len;
+ }
+ else
+ {
+ len = ep->xfer_len;
+ ep->xfer_len = 0U;
+ }
+ PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len);
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
}
PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID);
@@ -732,7 +850,7 @@
/**
* @brief USB_ClearInterrupts: clear a USB interrupt
* @param USBx Selected device
- * @param interrupt interrupt flag
+ * @param interrupt flag
* @retval None
*/
void USB_ClearInterrupts(USB_TypeDef *USBx, uint32_t interrupt)
@@ -822,7 +940,7 @@
}
/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
+ * @brief Copy data from packet memory area (PMA) to user memory buffer
* @param USBx: USB peripheral instance register address.
* @param pbUsrBuf pointer to user memory area.
* @param wPMABufAddr address into PMA.
diff --git a/Src/stm32l5xx_ll_utils.c b/Src/stm32l5xx_ll_utils.c
index 69fe74e..b0333bd 100644
--- a/Src/stm32l5xx_ll_utils.c
+++ b/Src/stm32l5xx_ll_utils.c
@@ -41,9 +41,9 @@
/** @addtogroup UTILS_LL_Private_Constants
* @{
*/
-#define UTILS_MAX_FREQUENCY_SCALE0 110000000U /*!< Maximum frequency for system clock at power scale0, in Hz */
-#define UTILS_MAX_FREQUENCY_SCALE1 80000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
-#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE0 110000000U /*!< Maximum frequency for system clock at power scale 0, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE1 80000000U /*!< Maximum frequency for system clock at power scale 1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2 26000000U /*!< Maximum frequency for system clock at power scale 2, in Hz */
/* Defines used for PLL range */
#define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */
@@ -54,21 +54,6 @@
/* Defines used for HSE range */
#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
#define UTILS_HSE_FREQUENCY_MAX 48000000U /*!< Frequency max for HSE frequency, in Hz */
-
-/* Defines used for FLASH latency according to HCLK Frequency */
-#define UTILS_SCALE0_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 0 */
-#define UTILS_SCALE0_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 0 */
-#define UTILS_SCALE0_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 0 */
-#define UTILS_SCALE0_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 0 */
-#define UTILS_SCALE0_LATENCY5_FREQ 100000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 0 */
-#define UTILS_SCALE0_LATENCY6_FREQ 110000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 0 */
-#define UTILS_SCALE1_LATENCY1_FREQ 20000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
-#define UTILS_SCALE1_LATENCY2_FREQ 40000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
-#define UTILS_SCALE1_LATENCY3_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
-#define UTILS_SCALE1_LATENCY4_FREQ 80000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
-#define UTILS_SCALE2_LATENCY1_FREQ 8000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
-#define UTILS_SCALE2_LATENCY2_FREQ 16000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
-#define UTILS_SCALE2_LATENCY3_FREQ 26000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
/**
* @}
*/
@@ -127,6 +112,8 @@
|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
+
+#define COUNTOF(a) (sizeof(a) / sizeof(*(a)))
/**
* @}
*/
@@ -226,7 +213,7 @@
(++) | | voltage range 0 | voltage range 1 | voltage range 2 |
(++) | | 1.28 V | 1.2 V | 1.0 V |
(++) |-----------------|-------------------|------------------|------------------|
- (++) |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 8 | 0 < HCLK <= 8 |
+ (++) |0WS(1 CPU cycles)| 0 < HCLK <= 20 | 0 < HCLK <= 20 | 0 < HCLK <= 8 |
(++) |-----------------|-------------------|------------------|------------------|
(++) |1WS(2 CPU cycles)| 20 < HCLK <= 40 | 20 < HCLK <= 40 | 8 < HCLK <= 16 |
(++) |-----------------|-------------------|------------------|------------------|
@@ -268,101 +255,78 @@
uint32_t timeout;
uint32_t getlatency;
uint32_t latency;
- ErrorStatus status = SUCCESS;
+ uint8_t index;
+ ErrorStatus status = ERROR;
- /* Frequency cannot be equal to 0 or greater than max clock */
- if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE0_LATENCY6_FREQ))
- {
- status = ERROR;
- }
- else
+ /* Array used for FLASH latency according to HCLK Frequency */
+ /* Flash Clock source (HCLK) range in MHz with a VCORE is range 0 */
+ const uint32_t UTILS_CLK_SRC_RANGE_VOS0[] = {20000000UL, 40000000UL, 60000000UL,
+ 80000000UL, 100000000UL, UTILS_MAX_FREQUENCY_SCALE0};
+
+ /* Flash Clock source (HCLK) range in MHz with a VCORE is range 1 */
+ const uint32_t UTILS_CLK_SRC_RANGE_VOS1[] = {20000000UL, 40000000UL, 60000000UL,
+ UTILS_MAX_FREQUENCY_SCALE1};
+
+ /* Flash Clock source (HCLK3) range in MHz with a VCORE is range2 */
+ const uint32_t UTILS_CLK_SRC_RANGE_VOS2[] = {8000000UL, 16000000UL, UTILS_MAX_FREQUENCY_SCALE2};
+
+ /* Flash Latency range */
+ const uint32_t UTILS_LATENCY_RANGE[] = {LL_FLASH_LATENCY_0, LL_FLASH_LATENCY_1, LL_FLASH_LATENCY_2,
+ LL_FLASH_LATENCY_3, LL_FLASH_LATENCY_4, LL_FLASH_LATENCY_5};
+
+ /* Frequency cannot be equal to 0 */
+ if (HCLKFrequency != 0U)
{
if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE0)
{
- if (HCLKFrequency > UTILS_SCALE0_LATENCY5_FREQ)
+ /* Frequency cannot be greater than a defined max clock */
+ if (HCLKFrequency <= UTILS_MAX_FREQUENCY_SCALE0)
{
- /* 100 < HCLK <= 110 => 5WS (6 CPU cycles) */
- latency = LL_FLASH_LATENCY_5;
- }
- else if (HCLKFrequency > UTILS_SCALE0_LATENCY4_FREQ)
- {
- /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
- latency = LL_FLASH_LATENCY_4;
- }
- else if (HCLKFrequency > UTILS_SCALE0_LATENCY3_FREQ)
- {
- /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
- latency = LL_FLASH_LATENCY_3;
- }
- else if (HCLKFrequency > UTILS_SCALE0_LATENCY2_FREQ)
- {
- /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else if (HCLKFrequency > UTILS_SCALE0_LATENCY1_FREQ)
- {
- /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- else
- {
- /* HCLK <= 20MHz => 0WS (1 CPU cycle) */
- latency = LL_FLASH_LATENCY_0;
+ for (index = 0; index < COUNTOF(UTILS_CLK_SRC_RANGE_VOS0); index++)
+ {
+ if (HCLKFrequency <= UTILS_CLK_SRC_RANGE_VOS0[index])
+ {
+ latency = UTILS_LATENCY_RANGE[index];
+ status = SUCCESS;
+ break;
+ }
+ }
}
}
else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
{
- if (HCLKFrequency > UTILS_SCALE1_LATENCY4_FREQ)
+ /* Frequency cannot be greater than a defined max clock */
+ if (HCLKFrequency <= UTILS_MAX_FREQUENCY_SCALE1)
{
- /* Unexpected HCLK > 80 */
- status = ERROR;
- }
- else if (HCLKFrequency > UTILS_SCALE1_LATENCY3_FREQ)
- {
- /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
- latency = LL_FLASH_LATENCY_3;
- }
- else if (HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)
- {
- /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else if (HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ)
- {
- /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- else
- {
- /* HCLK <= 20MHz => 0WS (1 CPU cycle) */
- latency = LL_FLASH_LATENCY_0;
+ for (index = 0; index < COUNTOF(UTILS_CLK_SRC_RANGE_VOS1); index++)
+ {
+ if (HCLKFrequency <= UTILS_CLK_SRC_RANGE_VOS1[index])
+ {
+ latency = UTILS_LATENCY_RANGE[index];
+ status = SUCCESS;
+ break;
+ }
+ }
}
}
else /* SCALE2 */
{
- if (HCLKFrequency > UTILS_SCALE2_LATENCY3_FREQ)
+ /* Frequency cannot be greater than a defined max clock */
+ if (HCLKFrequency <= UTILS_MAX_FREQUENCY_SCALE2)
{
- /* Unexpected HCLK > 26 */
- status = ERROR;
- }
- else if (HCLKFrequency > UTILS_SCALE2_LATENCY2_FREQ)
- {
- /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
- latency = LL_FLASH_LATENCY_2;
- }
- else if (HCLKFrequency > UTILS_SCALE2_LATENCY1_FREQ)
- {
- /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
- latency = LL_FLASH_LATENCY_1;
- }
- else
- {
- /* HCLK <= 8MHz => 0WS (1 CPU cycle) */
- latency = LL_FLASH_LATENCY_0;
+ for (index = 0; index < COUNTOF(UTILS_CLK_SRC_RANGE_VOS2); index++)
+ {
+ if (HCLKFrequency <= UTILS_CLK_SRC_RANGE_VOS2[index])
+ {
+ latency = UTILS_LATENCY_RANGE[index];
+ status = SUCCESS;
+ break;
+ }
+ }
}
}
- if (status != ERROR)
+ if (status == SUCCESS)
{
LL_FLASH_SetLatency(latency);
