Release v1.14.2
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index dc7f695..6e2d2d2 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -548,6 +548,16 @@
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
+#if defined(STM32U0)
+#define OB_USER_nRST_STOP OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
+#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
+#define OB_USER_nBOOT0 OB_USER_NBOOT0
+#define OB_USER_nBOOT1 OB_USER_NBOOT1
+#define OB_nBOOT0_RESET OB_NBOOT0_RESET
+#define OB_nBOOT0_SET OB_NBOOT0_SET
+#endif /* STM32U0 */
/**
* @}
@@ -1239,10 +1249,10 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
-#if defined(STM32H5)
+#if defined(STM32H5) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
-#endif /* STM32H5 */
+#endif /* STM32H5 || STM32H7RS */
#if defined(STM32WBA)
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1254,10 +1264,10 @@
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
#endif /* STM32WBA */
-#if defined(STM32H5) || defined(STM32WBA)
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
-#endif /* STM32H5 || STM32WBA */
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
#if defined(STM32F7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1595,6 +1605,8 @@
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
+#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
+
/**
* @}
*/
@@ -1987,12 +1999,12 @@
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
* @{
*/
-#if defined(STM32H5) || defined(STM32WBA)
+#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
-#endif /* STM32H5 || STM32WBA */
+#endif /* STM32H5 || STM32WBA || STM32H7RS */
/**
* @}
@@ -2307,8 +2319,8 @@
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
+#endif
+#if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2341,8 +2353,8 @@
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#endif
+#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2399,8 +2411,8 @@
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
+#endif
+#if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2417,7 +2429,7 @@
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
+#endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -3642,9 +3654,12 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
- defined(STM32WL) || defined(STM32C0)
+#if defined(STM32U0)
+#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
+#endif
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
+ defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3746,8 +3761,10 @@
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
+#if !defined(STM32U0)
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+#endif
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3893,8 +3910,7 @@
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
- defined (STM32WBA) || defined (STM32H5) || \
- defined (STM32C0)
+ defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
@@ -4216,7 +4232,8 @@
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
-#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
+
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
/**
diff --git a/Inc/stm32wbxx_hal_cortex.h b/Inc/stm32wbxx_hal_cortex.h
index 8664363..fb1555c 100644
--- a/Inc/stm32wbxx_hal_cortex.h
+++ b/Inc/stm32wbxx_hal_cortex.h
@@ -293,6 +293,8 @@
#if (__MPU_PRESENT == 1U)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
+void HAL_MPU_EnableRegion(uint32_t RegionNumber);
+void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
diff --git a/Inc/stm32wbxx_hal_cryp.h b/Inc/stm32wbxx_hal_cryp.h
index 8dc0f14..07b0ec6 100644
--- a/Inc/stm32wbxx_hal_cryp.h
+++ b/Inc/stm32wbxx_hal_cryp.h
@@ -53,7 +53,8 @@
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
- 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
+ 128 or 256 bit key length in TinyAES
+ This parameter can be a value of @ref CRYP_Key_Size */
uint32_t *pKey; /*!< The key used for encryption/decryption */
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
diff --git a/Inc/stm32wbxx_hal_qspi.h b/Inc/stm32wbxx_hal_qspi.h
index ce9d996..54eb65f 100644
--- a/Inc/stm32wbxx_hal_qspi.h
+++ b/Inc/stm32wbxx_hal_qspi.h
@@ -589,13 +589,13 @@
* @{
*/
/* Peripheral Control and State functions ************************************/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
-uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi);
+uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
+uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
diff --git a/Inc/stm32wbxx_hal_spi_ex.h b/Inc/stm32wbxx_hal_spi_ex.h
index 54cc0c5..946cbd0 100644
--- a/Inc/stm32wbxx_hal_spi_ex.h
+++ b/Inc/stm32wbxx_hal_spi_ex.h
@@ -48,7 +48,7 @@
/** @addtogroup SPIEx_Exported_Functions_Group1
* @{
*/
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi);
/**
* @}
*/
diff --git a/Inc/stm32wbxx_ll_rtc.h b/Inc/stm32wbxx_ll_rtc.h
index 0a59502..aeda9dd 100644
--- a/Inc/stm32wbxx_ll_rtc.h
+++ b/Inc/stm32wbxx_ll_rtc.h
@@ -1093,7 +1093,7 @@
/**
* @brief Get time format (AM or PM notation)
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1127,7 +1127,7 @@
/**
* @brief Get Hours in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1165,7 +1165,7 @@
/**
* @brief Get Minutes in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1203,7 +1203,7 @@
/**
* @brief Get Seconds in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1257,7 +1257,7 @@
/**
* @brief Get time (hour, minute and second) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
@@ -1403,7 +1403,7 @@
/**
* @brief Get Year in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
* @rmtoll DR YT LL_RTC_DATE_GetYear\n
@@ -1440,7 +1440,7 @@
/**
* @brief Get Week day
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @rmtoll DR WDU LL_RTC_DATE_GetWeekDay
* @param RTCx RTC Instance
@@ -1487,7 +1487,7 @@
/**
* @brief Get Month in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
* @rmtoll DR MT LL_RTC_DATE_GetMonth\n
@@ -1532,7 +1532,7 @@
/**
* @brief Get Day in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll DR DT LL_RTC_DATE_GetDay\n
@@ -1598,7 +1598,7 @@
/**
* @brief Get date (WeekDay, Day, Month and Year) in BCD format
- * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
+ * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
* and __LL_RTC_GET_DAY are available to get independently each parameter.
diff --git a/Inc/stm32wbxx_ll_utils.h b/Inc/stm32wbxx_ll_utils.h
index 9742652..f9d186e 100644
--- a/Inc/stm32wbxx_ll_utils.h
+++ b/Inc/stm32wbxx_ll_utils.h
@@ -256,7 +256,7 @@
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field))
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
- * @param Ticks Number of ticks
+ * @param Ticks Frequency of Ticks (Hz)
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
diff --git a/Release_Notes.html b/Release_Notes.html
index ad7371d..967724d 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -40,7 +40,7 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section17" checked aria-hidden="true"> <label for="collapse-section17" aria-hidden="true">V1.14.1 / 31-October-2023</label>
+<input type="checkbox" id="collapse-section18" checked aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.14.2/ 07-February-2024</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
@@ -50,6 +50,68 @@
<h2 id="contents">Contents</h2>
<h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
<ul>
+<li><strong>HAL GPIO</strong> driver
+<ul>
+<li>Replace GPIO_Pin_x with GPIO_PIN_x to be compliant with macros definition</li>
+</ul></li>
+<li><strong>HAL CRYP</strong> driver
+<ul>
+<li>Update CRYP_AESGCM_Process_IT() and CRYP_AESCCM_Process_IT() to prevent ‘Computation Completed’ IRQ from firing before the DINR pointer gets incremented.</li>
+</ul></li>
+<li><strong>HAL I2C</strong> driver
+<ul>
+<li>Update HAL_I2C_Slave_Transmit to check if the received NACK is the good one</li>
+</ul></li>
+<li><strong>HAL SMBUS</strong> driver
+<ul>
+<li>Update SMBUS_ITErrorHandler to flash TXDR just in case of error</li>
+</ul></li>
+<li><strong>HAL QSPI</strong> driver
+<ul>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers</li>
+<li>Fix incorrect word ‘surcharged’ in functions headers</li>
+</ul></li>
+<li><strong>HAL CORTEX</strong> driver
+<ul>
+<li>Updated HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field.</li>
+<li>Add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion().</li>
+</ul></li>
+<li><strong>HAL TIM</strong> driver
+<ul>
+<li>Update interrupt flag is cleared when the update event is generated by software.</li>
+<li>Fix typo in PWM asymmetric mode macros’ names.</li>
+</ul></li>
+<li><strong>HAL LPTIM</strong> driver
+<ul>
+<li>Removed redundant IS_LPTIM_AUTORELOAD macro.</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<ul>
+<li><strong>LL UTILS</strong> driver
+<ul>
+<li>Fix a note about Ticks parameter.</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section17" aria-hidden="true"> <label for="collapse-section17" aria-hidden="true">V1.14.1 / 01-November-2023</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
+<li>HAL/LL code quality enhancement</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<ul>
<li><strong>HAL I2C</strong> driver
<ul>
<li>Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice</li>
@@ -83,7 +145,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL I2C</strong> driver
<ul>
@@ -101,20 +163,20 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section16" aria-hidden="true"> <label for="collapse-section16" aria-hidden="true">V1.14.0 / 07-June-2023</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
<li>HAL/LL code quality enhancement</li>
</ul>
-<h2 id="contents-1">Contents</h2>
-<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-2">Contents</h2>
+<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL CRYP</strong> driver
<ul>
@@ -153,7 +215,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL USB</strong> driver
<ul>
@@ -162,20 +224,20 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section15" aria-hidden="true"> <label for="collapse-section15" aria-hidden="true">V1.13.0 / 8-February-2023</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
<li>HAL/LL code quality enhancement</li>
</ul>
-<h2 id="contents-2">Contents</h2>
-<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-3">Contents</h2>
+<h3 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL FLASH</strong> driver
<ul>
@@ -206,20 +268,20 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-2">Backward Compatibility</h2>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section14" aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.12.0 / 09-November-2022</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
<li>Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (IRDA, LPTIM, SMARTCARD, TIM, UART, USART)</li>
</ul>
-<h2 id="contents-3">Contents</h2>
-<h3 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-4">Contents</h2>
+<h3 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL ADC</strong> driver
<ul>
@@ -266,7 +328,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL ADC</strong> driver
<ul>
@@ -287,20 +349,20 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-3">Backward Compatibility</h2>
+<h2 id="backward-compatibility-4">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.11.0 / 01-June-2022</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<ul>
<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
<li>Correct English spelling errors and typos</li>
</ul>
-<h2 id="contents-4">Contents</h2>
-<h3 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-5">Contents</h2>
+<h3 id="hal-drivers-updates-5"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL EXTI</strong> driver
<ul>
@@ -376,7 +438,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL I2C</strong> driver
<ul>
@@ -412,19 +474,19 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-4">Backward Compatibility</h2>
+<h2 id="backward-compatibility-5">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.10.1 / 27-March-2022</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<ul>
<li>Patch release of <strong>HAL and Low Layer</strong> drivers</li>
</ul>
-<h2 id="contents-5">Contents</h2>
-<h3 id="hal-drivers-updates-5"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-6">Contents</h2>
+<h3 id="hal-drivers-updates-6"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL COMP</strong> driver
<ul>
@@ -433,7 +495,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-5"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL COMP</strong> driver
<ul>
@@ -442,21 +504,21 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-5">Backward Compatibility</h2>
+<h2 id="backward-compatibility-6">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.10.0 / 12-November-2021</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
<li>All source files: update disclaimer to add reference to the new license agreement</li>
<li>Correct English spelling errors and typos</li>
</ul>
-<h2 id="contents-6">Contents</h2>
-<h3 id="hal-drivers-updates-6"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-7">Contents</h2>
+<h3 id="hal-drivers-updates-7"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL ADC</strong> driver
<ul>
@@ -527,7 +589,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-5"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-6"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL ADC</strong> driver
<ul>
@@ -542,14 +604,14 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-6">Backward Compatibility</h2>
+<h2 id="backward-compatibility-7">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.9.0 / 24-June-2021</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
<li>Update of HAL SMBUS driver to introduce fast mode and fast mode plus
@@ -563,8 +625,8 @@
</ul>
<p><br />
</p>
-<h2 id="contents-7">Contents</h2>
-<h3 id="hal-drivers-updates-7"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-8">Contents</h2>
+<h3 id="hal-drivers-updates-8"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL CORTEX</strong> driver
<ul>
@@ -640,7 +702,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-6"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-7"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL DMA</strong> driver
<ul>
@@ -667,14 +729,14 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-7">Backward Compatibility</h2>
+<h2 id="backward-compatibility-8">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">v1.8.0 / 12-February-2021</label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<h3 id="add-support-for-stm32wb15xx-and-stm32wb10xx">Add support for STM32WB15xx and STM32WB10xx</h3>
<table>
<thead>
@@ -810,14 +872,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-8">Backward Compatibility</h2>
+<h2 id="backward-compatibility-9">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">v1.7.0 / 30-October-2020</label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<h3 id="maitenance-release">Maitenance release</h3>
<p>All peripheral</p>
<table>
@@ -890,14 +952,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-9">Backward Compatibility</h2>
+<h2 id="backward-compatibility-10">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">v1.6.0 / 05-June-2020</label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<h3 id="maitenance-release-1">Maitenance release</h3>
<p>All peripheral</p>
<table>
@@ -1002,14 +1064,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-10">Backward Compatibility</h2>
+<h2 id="backward-compatibility-11">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.5.0 / 12-February-2020</label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<h3 id="introduction-of-stm32wb5m-stm32wb35xx-and-stm32wb30xx-product">Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product</h3>
<p>This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.</p>
<p>Added features:</p>
@@ -1054,14 +1116,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-11">Backward Compatibility</h2>
+<h2 id="backward-compatibility-12">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">v1.4.0 / 15-December-2019</label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<h3 id="maitenance-release-2">Maitenance release</h3>
<table>
<thead>
@@ -1105,7 +1167,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-12">Backward Compatibility</h2>
+<h2 id="backward-compatibility-13">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1115,7 +1177,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.3.0 / 11-September-2019</label>
<div>
-<h2 id="main-changes-13">Main Changes</h2>
+<h2 id="main-changes-14">Main Changes</h2>
<h3 id="maitenance-release-3">Maitenance release</h3>
<table>
<thead>
@@ -1187,7 +1249,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-13">Backward Compatibility</h2>
+<h2 id="backward-compatibility-14">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-1">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1197,7 +1259,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
<div>
-<h2 id="main-changes-14">Main Changes</h2>
+<h2 id="main-changes-15">Main Changes</h2>
<h3 id="stm32wb50xx-introduction-and-maintenance-release">STM32WB50xx introduction and maintenance release</h3>
<p>First release for STM32WBxx HAL drivers introducing <strong>stm32wb50xx</strong> devices.</p>
<table>
@@ -1266,7 +1328,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-14">Backward Compatibility</h2>
+<h2 id="backward-compatibility-15">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-2">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1276,7 +1338,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-15">Main Changes</h2>
+<h2 id="main-changes-16">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<p>Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.</p>
<table>
@@ -1330,7 +1392,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-15">Backward Compatibility</h2>
+<h2 id="backward-compatibility-16">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-3">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1340,7 +1402,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
<div>
-<h2 id="main-changes-16">Main Changes</h2>
+<h2 id="main-changes-17">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.</p>
</div>
diff --git a/Src/stm32wbxx_hal.c b/Src/stm32wbxx_hal.c
index ec62ac7..e19fb9a 100644
--- a/Src/stm32wbxx_hal.c
+++ b/Src/stm32wbxx_hal.c
@@ -56,7 +56,7 @@
*/
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WBxx_HAL_VERSION_SUB1 (0x0EU) /*!< [23:16] sub1 version */
-#define __STM32WBxx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32WBxx_HAL_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
|(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\
diff --git a/Src/stm32wbxx_hal_cortex.c b/Src/stm32wbxx_hal_cortex.c
index 3e2384e..5c34a39 100644
--- a/Src/stm32wbxx_hal_cortex.c
+++ b/Src/stm32wbxx_hal_cortex.c
@@ -416,6 +416,38 @@
}
/**
+ * @brief Enable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_EnableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Enable the Region */
+ SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+ * @brief Disable the MPU Region.
+ * @retval None
+ */
+void HAL_MPU_DisableRegion(uint32_t RegionNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
+
+ /* Set the Region number */
+ MPU->RNR = RegionNumber;
+
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
* @brief Initialize and configure the Region and the memory to be protected.
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
@@ -426,38 +458,32 @@
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+ assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+ assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+ assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+ assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+ assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+ assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+ assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+ assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
- if ((MPU_Init->Enable) != 0U)
- {
- /* Check the parameters */
- assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
- assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
- assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
- assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
- assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
- assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
- assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
- assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+ /* Disable the Region */
+ CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
- MPU->RBAR = MPU_Init->BaseAddress;
- MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
- ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
- ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
- ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
- ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
- ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
- ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
- ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
- ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
- }
- else
- {
- MPU->RBAR = 0x00U;
- MPU->RASR = 0x00U;
- }
+ /* Apply configuration */
+ MPU->RBAR = MPU_Init->BaseAddress;
+ MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
+ ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
+ ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
+ ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
+ ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
+ ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
+ ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
+ ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
+ ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
#endif /* __MPU_PRESENT */
diff --git a/Src/stm32wbxx_hal_crc.c b/Src/stm32wbxx_hal_crc.c
index d1b1b63..d7882aa 100644
--- a/Src/stm32wbxx_hal_crc.c
+++ b/Src/stm32wbxx_hal_crc.c
@@ -200,7 +200,7 @@
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
- CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
+ CLEAR_REG(hcrc->Instance->IDR);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
diff --git a/Src/stm32wbxx_hal_cryp.c b/Src/stm32wbxx_hal_cryp.c
index 938dc2e..a1dd12c 100644
--- a/Src/stm32wbxx_hal_cryp.c
+++ b/Src/stm32wbxx_hal_cryp.c
@@ -30,7 +30,8 @@
The CRYP HAL driver can be used in CRYP or TinyAES peripheral as follows:
(#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
- (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
+ (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()
+ or __HAL_RCC_AES_CLK_ENABLE for TinyAES peripheral
(##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
(+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
(+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
@@ -58,8 +59,10 @@
(##) The DataWidthUnit field. It specifies whether the data length (or the payload length for authentication
algorithms) is in words or bytes.
(##) The Header used only in AES GCM and CCM Algorithm for authentication.
- (##) The HeaderSize providing the size of the header buffer in words or bytes, depending upon HeaderWidthUnit field.
- (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms) is in words or bytes.
+ (##) The HeaderSize providing the size of the header buffer in words or bytes,
+ depending upon HeaderWidthUnit field.
+ (##) The HeaderWidthUnit field. It specifies whether the header length (for authentication algorithms)
+ is in words or bytes.
(##) The B0 block is the first authentication block used only in AES CCM mode.
(##) The KeyIVConfigSkip used to process several messages in a row (please see more information below).
@@ -316,7 +319,8 @@
* @{
*/
#define CRYP_TIMEOUT_KEYPREPARATION 82U /* The latency of key preparation operation is 82 clock cycles.*/
-#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
+#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey
+ is 299 clock cycles.*/
#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
@@ -350,7 +354,8 @@
* @{
*/
-#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR, AES_CR_GCMPH, (uint32_t)(__PHASE__))
+#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) MODIFY_REG((__HANDLE__)->Instance->CR,\
+ AES_CR_GCMPH, (uint32_t)(__PHASE__))
/**
* @}
@@ -923,8 +928,6 @@
hcryp->SuspendRequest = HAL_CRYP_SUSPEND;
}
-
-
/**
* @brief CRYP processing suspension and peripheral internal parameters storage.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
@@ -977,7 +980,8 @@
hcryp->CrypOutCount_saved = hcryp->CrypOutCount;
hcryp->Phase_saved = hcryp->Phase;
hcryp->State_saved = hcryp->State;
- hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size / 4U) : hcryp->Size);
+ hcryp->Size_saved = ((hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? \
+ (hcryp->Size / 4U) : hcryp->Size);
hcryp->SizesSum_saved = hcryp->SizesSum;
hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation;
hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount;
@@ -1068,14 +1072,16 @@
hcryp->ResumingFlag = 1U;
if (READ_BIT(hcryp->CR_saved, AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
{
- if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+ if (HAL_CRYP_Encrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \
+ hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
{
return HAL_ERROR;
}
}
else
{
- if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
+ if (HAL_CRYP_Decrypt_IT(hcryp, hcryp->pCrypInBuffPtr_saved, hcryp->Size_saved, \
+ hcryp->pCrypOutBuffPtr_saved) != HAL_OK)
{
return HAL_ERROR;
}
@@ -1708,7 +1714,8 @@
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Start DMA process transfer for AES */
- CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
+ CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), \
+ (uint32_t)(hcryp->pCrypOutBuffPtr));
status = HAL_OK;
break;
@@ -1861,25 +1868,27 @@
*/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
{
+ uint32_t itsource = hcryp->Instance->CR;
+ uint32_t itflag = hcryp->Instance->SR;
/* Check if error occurred */
- if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
+ if ((itsource & CRYP_IT_ERRIE) == CRYP_IT_ERRIE)
{
/* If write Error occurred */
- if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
+ if ((itflag & CRYP_IT_WRERR) == CRYP_IT_WRERR)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
}
/* If read Error occurred */
- if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
+ if ((itflag & CRYP_IT_RDERR) == CRYP_IT_RDERR)
{
hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
}
}
- if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
+ if ((itflag & CRYP_IT_CCF) == CRYP_IT_CCF)
{
- if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
+ if ((itsource & CRYP_IT_CCFIE) == CRYP_IT_CCFIE)
{
/* Clear computation complete flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
@@ -2685,7 +2694,8 @@
/*Read the output block from the output FIFO */
for (count = 0U; count < 4U; count++)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer */
temp[count] = hcryp->Instance->DOUTR;
}
@@ -2896,7 +2906,8 @@
/* Clear CCF Flag */
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
@@ -2925,7 +2936,8 @@
if (hcryp->State == HAL_CRYP_STATE_BUSY)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
@@ -3251,7 +3263,8 @@
/*Read the output block from the output FIFO */
for (index = 0U; index < 4U; index++)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer */
temp[index] = hcryp->Instance->DOUTR;
}
for (index = 0U; index < lastwordsize; index++)
@@ -3920,7 +3933,8 @@
for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer */
temp[loopcounter] = hcryp->Instance->DOUTR;
}
for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
@@ -4414,7 +4428,8 @@
/***************************** Payload phase *******************************/
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer*/
for (i = 0U; i < 4U; i++)
{
temp[i] = hcryp->Instance->DOUTR;
@@ -4653,7 +4668,8 @@
/*Read the output block from the output FIFO */
for (index = 0U; index < 4U; index++)
{
- /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
+ /* Read the output block from the output FIFO and put them in temporary buffer
+ then get CrypOutBuff from temporary buffer */
temp[index] = hcryp->Instance->DOUTR;
}
for (index = 0U; index < lastwordsize; index++)
diff --git a/Src/stm32wbxx_hal_gpio.c b/Src/stm32wbxx_hal_gpio.c
index 90af8ea..564acc3 100644
--- a/Src/stm32wbxx_hal_gpio.c
+++ b/Src/stm32wbxx_hal_gpio.c
@@ -420,9 +420,9 @@
* accesses.
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WLxx family
* @param PinReset specifies the port bits to be reset
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) or zero.
* @param PinSet specifies the port bits to be set
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero.
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) or zero.
* @note Both PinReset and PinSet combinations shall not get any common bit, else
* assert would be triggered.
* @note At least one of the two parameters used to set or reset shall be different from zero.
@@ -469,7 +469,7 @@
* until the next reset.
* @param GPIOx where x can be (A..H) to select the GPIO peripheral for STM32WBxx family
* @param GPIO_Pin specifies the port bits to be locked.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
diff --git a/Src/stm32wbxx_hal_i2c.c b/Src/stm32wbxx_hal_i2c.c
index 05f58e6..de3805e 100644
--- a/Src/stm32wbxx_hal_i2c.c
+++ b/Src/stm32wbxx_hal_i2c.c
@@ -1385,6 +1385,8 @@
uint32_t Timeout)
{
uint32_t tickstart;
+ uint16_t tmpXferCount;
+ HAL_StatusTypeDef error;
if (hi2c->State == HAL_I2C_STATE_READY)
{
@@ -1478,31 +1480,48 @@
}
/* Wait until AF flag is set */
- if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
+ error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
+
+ if (error != HAL_OK)
{
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
- return HAL_ERROR;
+ /* Check that I2C transfer finished */
+ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
+ /* Mean XferCount == 0 */
+
+ tmpXferCount = hi2c->XferCount;
+ if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
+ {
+ /* Reset ErrorCode to NONE */
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ }
+ else
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ return HAL_ERROR;
+ }
}
-
- /* Flush TX register */
- I2C_Flush_TXDR(hi2c);
-
- /* Clear AF flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
- /* Wait until STOP flag is set */
- if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ else
{
- /* Disable Address Acknowledge */
- hi2c->Instance->CR2 |= I2C_CR2_NACK;
+ /* Flush TX register */
+ I2C_Flush_TXDR(hi2c);
- return HAL_ERROR;
+ /* Clear AF flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
+
+ /* Wait until STOP flag is set */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ {
+ /* Disable Address Acknowledge */
+ hi2c->Instance->CR2 |= I2C_CR2_NACK;
+
+ return HAL_ERROR;
+ }
+
+ /* Clear STOP flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- /* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
/* Wait until BUSY flag is reset */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
diff --git a/Src/stm32wbxx_hal_qspi.c b/Src/stm32wbxx_hal_qspi.c
index 58c87ae..c754086 100644
--- a/Src/stm32wbxx_hal_qspi.c
+++ b/Src/stm32wbxx_hal_qspi.c
@@ -2219,7 +2219,7 @@
* @param hqspi QSPI handle
* @retval HAL state
*/
-HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi)
{
/* Return QSPI handle state */
return hqspi->State;
@@ -2230,7 +2230,7 @@
* @param hqspi QSPI handle
* @retval QSPI Error Code
*/
-uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
+uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi)
{
return hqspi->ErrorCode;
}
@@ -2410,7 +2410,7 @@
* @param hqspi QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
-uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
+uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi)
{
return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
}
diff --git a/Src/stm32wbxx_hal_smbus.c b/Src/stm32wbxx_hal_smbus.c
index 84f9329..9751bdb 100644
--- a/Src/stm32wbxx_hal_smbus.c
+++ b/Src/stm32wbxx_hal_smbus.c
@@ -2619,8 +2619,11 @@
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
}
- /* Flush TX register */
- SMBUS_Flush_TXDR(hsmbus);
+ if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)
+ {
+ /* Flush TX register */
+ SMBUS_Flush_TXDR(hsmbus);
+ }
/* Store current volatile hsmbus->ErrorCode, misra rule */
tmperror = hsmbus->ErrorCode;
diff --git a/Src/stm32wbxx_hal_spi_ex.c b/Src/stm32wbxx_hal_spi_ex.c
index f51957d..f8a8a9f 100644
--- a/Src/stm32wbxx_hal_spi_ex.c
+++ b/Src/stm32wbxx_hal_spi_ex.c
@@ -76,7 +76,7 @@
* the configuration information for the specified SPI module.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi)
{
__IO uint32_t tmpreg;
uint8_t count = 0U;
