Release v1.12.0
diff --git a/Inc/Legacy/stm32_hal_legacy.h b/Inc/Legacy/stm32_hal_legacy.h
index 39d97e3..730762f 100644
--- a/Inc/Legacy/stm32_hal_legacy.h
+++ b/Inc/Legacy/stm32_hal_legacy.h
@@ -214,6 +214,11 @@
#endif
#endif
+
+#if defined(STM32U5)
+#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
+#endif
+
/**
* @}
*/
@@ -268,7 +273,7 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
-#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
@@ -530,6 +535,9 @@
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
+#define OB_USER_SRAM134_RST OB_USER_SRAM_RST
+#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
+#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
#endif /* STM32U5 */
/**
@@ -672,8 +680,6 @@
#if defined(STM32U5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
-#endif /* STM32U5 */
-#if defined(STM32U5)
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
#endif /* STM32U5 */
@@ -686,7 +692,9 @@
*/
#if defined(STM32U5)
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
+#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
#endif /* STM32U5 */
+
/**
* @}
*/
@@ -1005,7 +1013,7 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
@@ -2959,6 +2967,11 @@
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2
+#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2
+#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2
+#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
@@ -3586,7 +3599,7 @@
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
- defined (STM32WB_GEN2) || defined (STM32WBA) || defined (STM32C0)
+ defined (STM32C0)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
diff --git a/Inc/stm32_assert_template.h b/Inc/stm32_assert_template.h
index d9e5916..4896935 100644
--- a/Inc/stm32_assert_template.h
+++ b/Inc/stm32_assert_template.h
@@ -23,7 +23,7 @@
#define STM32_ASSERT_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
@@ -39,11 +39,11 @@
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
+void assert_failed(uint8_t *file, uint32_t line);
#else
- #define assert_param(expr) ((void)0U)
+#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
diff --git a/Inc/stm32wbxx_hal.h b/Inc/stm32wbxx_hal.h
index d556479..2c2375c 100644
--- a/Inc/stm32wbxx_hal.h
+++ b/Inc/stm32wbxx_hal.h
@@ -22,7 +22,7 @@
#define STM32WBxx_HAL_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -36,7 +36,7 @@
/** @defgroup HAL HAL
* @{
*/
-
+
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
@@ -51,7 +51,7 @@
/**
* @}
*/
-
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
@@ -69,11 +69,11 @@
#define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */
#if defined(LL_SYSCFG_REMAP_QUADSPI)
#define SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI /*!< QUADSPI memory mapped at 0x00000000 */
-#endif
+#endif /* LL_SYSCFG_REMAP_QUADSPI */
/**
* @}
*/
-
+
/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
* @{
*/
@@ -208,22 +208,22 @@
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
- */
+ */
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
-
+
/**
- * @}
- */
-
+ * @}
+ */
+
/** @defgroup Secure_IP_Write_Access Secure IP Write Access
* @{
*/
#if defined(LL_SYSCFG_SECURE_ACCESS_AES1)
#define HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */
-#endif
+#endif /* LL_SYSCFG_SECURE_ACCESS_AES1 */
#define HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */
#define HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA /*!< Enabling the security access of Public Key Accelerator */
#define HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG /*!< Enabling the security access of Random Number Generator */
@@ -257,57 +257,57 @@
#if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
-#endif
+#endif /* LL_DBGMCU_APB1_GRP1_TIM2_STOP */
#if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
-#endif
+#endif /* LL_DBGMCU_APB1_GRP1_RTC_STOP */
#if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
-#endif
+#endif /* LL_DBGMCU_APB1_GRP1_WWDG_STOP */
#if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
-#endif
+#endif /* LL_DBGMCU_APB1_GRP1_IWDG_STOP */
#if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
-#endif
+#endif /* LL_DBGMCU_APB1_GRP1_I2C1_STOP */
#if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
-#endif
+#endif /* LL_DBGMCU_APB1_GRP1_I2C3_STOP */
#if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
-#endif
+#endif /* LL_DBGMCU_APB1_GRP1_LPTIM1_STOP */
#if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
-#endif
+#endif /* LL_DBGMCU_APB1_GRP2_LPTIM2_STOP */
#if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
-#endif
+#endif /* LL_DBGMCU_APB2_GRP1_TIM1_STOP */
#if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
-#endif
+#endif /* LL_DBGMCU_APB2_GRP1_TIM16_STOP */
#if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
-#endif
+#endif /* LL_DBGMCU_APB2_GRP1_TIM17_STOP */
/**
* @}
@@ -319,52 +319,52 @@
#if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
#define __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP */
#if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
#define __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB1_GRP1_RTC_STOP */
#if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
#define __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP */
#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
#define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP */
#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
#define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP */
#if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP */
#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP */
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
#define __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP */
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
#define __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP */
#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
#define __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
#define __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
-#endif
+#endif /* LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP */
/**
* @}
@@ -394,7 +394,7 @@
/** @brief QUADSPI mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)
-#endif
+#endif /* LL_SYSCFG_REMAP_QUADSPI */
/**
* @brief Return the boot mode as configured by user.
@@ -415,17 +415,21 @@
*/
/* Legacy define */
#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
- LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\
- }while(0)
+#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) \
+ do { \
+ assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__))); \
+ LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__); \
+ } while(0)
/** @brief SRAM2 page 32 to 63 write protection enable macro
* @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63
* @note Write protection can only be disabled by a system reset
*/
-#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP2_PAGE((__SRAM2WRP__)));\
- LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);\
- }while(0)
+#define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) \
+ do { \
+ assert_param(IS_SYSCFG_SRAM2WRP2_PAGE((__SRAM2WRP__))); \
+ LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__); \
+ } while(0)
/** @brief SRAM2 page write protection unlock prior to erase
* @note Writing a wrong key reactivates the write protection
@@ -440,13 +444,17 @@
/** @brief Floating Point Unit interrupt enable/disable macros
* @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts
*/
-#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
- SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
- }while(0)
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) \
+ do { \
+ assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \
+ SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__)); \
+ } while(0)
-#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
- CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
- }while(0)
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) \
+ do { \
+ assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__))); \
+ CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__)); \
+ } while(0)
/** @brief SYSCFG Break ECC lock.
* Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input.
@@ -461,7 +469,8 @@
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)
/** @brief SYSCFG Break PVD lock.
- * Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
+ * Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0]
+ * in the PWR_CR2 register.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)
@@ -479,7 +488,8 @@
* @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U)
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & \
+ (__FLAG__))!= 0U) ? 1U : 0U)
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
*/
@@ -488,13 +498,17 @@
/** @brief Fast mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
*/
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
- LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \
- }while(0)
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \
+ do { \
+ assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
+ LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \
+ } while(0)
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
- LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \
- }while(0)
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \
+ do { \
+ assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
+ LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \
+ } while(0)
/**
* @}
@@ -503,7 +517,7 @@
/**
* @}
*/
-
+
/* Private macros ------------------------------------------------------------*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
@@ -513,12 +527,12 @@
* @{
*/
-#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
- (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
+ (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
#if defined(STM32WB15xx)
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
@@ -526,7 +540,7 @@
#else
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
#define IS_SYSCFG_SRAM2WRP2_PAGE(__PAGE__) IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)
-#endif
+#endif /* STM32WB15xx */
#if defined(VREFBUF)
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
@@ -536,23 +550,23 @@
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
-#endif
+#endif /* VREFBUF */
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
- (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#if defined(LL_SYSCFG_SECURE_ACCESS_AES1)
-#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1) == HAL_SYSCFG_SECURE_ACCESS_AES1) || \
- (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \
- (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \
- (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG))
+#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1) == HAL_SYSCFG_SECURE_ACCESS_AES1) || \
+ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \
+ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \
+ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG))
#else
-#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \
- (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \
- (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG))
-#endif
+#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \
+ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \
+ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG))
+#endif /* LL_SYSCFG_SECURE_ACCESS_AES1 */
/**
* @}
@@ -589,7 +603,7 @@
void HAL_MspInit(void);
void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
@@ -633,7 +647,7 @@
/**
* @}
*/
-
+
/* Exported variables ---------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
@@ -660,14 +674,14 @@
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
-#endif
+#endif /* VREFBUF */
void HAL_SYSCFG_EnableIOBooster(void);
void HAL_SYSCFG_DisableIOBooster(void);
#if defined(SYSCFG_CFGR1_ANASWVDD)
void HAL_SYSCFG_EnableIOVdd(void);
void HAL_SYSCFG_DisableIOVdd(void);
-#endif
+#endif /* SYSCFG_CFGR1_ANASWVDD */
void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess);
void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess);
diff --git a/Inc/stm32wbxx_hal_adc.h b/Inc/stm32wbxx_hal_adc.h
index ef6ff7d..a85c18a 100644
--- a/Inc/stm32wbxx_hal_adc.h
+++ b/Inc/stm32wbxx_hal_adc.h
@@ -43,7 +43,7 @@
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -69,7 +69,7 @@
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
} ADC_OversamplingTypeDef;
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Structure definition of ADC instance and ADC group regular.
@@ -134,13 +134,13 @@
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
This parameter can be set to ENABLE or DISABLE.
Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
@@ -157,13 +157,13 @@
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group regular number of discontinuous conversions" not available on ADC peripheral of this STM32WB device */
#else
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
@@ -190,7 +190,7 @@
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
@@ -208,18 +208,18 @@
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode.
This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
Note: ADC trigger frequency mode must be set to low frequency when
@@ -230,7 +230,7 @@
Note: When ADC trigger frequency mode is set to low frequency,
some rearm cycles are inserted before performing ADC conversion
start, inducing a delay of 2 ADC clock cycles. */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
} ADC_InitTypeDef;
@@ -267,7 +267,7 @@
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values. */
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
uint32_t SingleDiff; /*!< Select single-ended or differential input.
In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
@@ -291,7 +291,7 @@
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
} ADC_ChannelConfTypeDef;
/**
@@ -418,11 +418,11 @@
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */
#else
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
@@ -537,7 +537,7 @@
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Note: On STM32WB10xx, STM32WB15xx, STM32WB1Mxx devices, ADC group regular */
/* sequencer both modes "fully configurable" or "not fully configurable"*/
/* are available. */
@@ -589,7 +589,7 @@
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -626,7 +626,7 @@
/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */
@@ -655,12 +655,12 @@
#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME ADC instance - Sampling time common to a group of channels
* @{
*/
@@ -699,7 +699,7 @@
/**
* @}
*/
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
* @{
@@ -736,12 +736,12 @@
* @{
*/
#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */
#else
#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -760,7 +760,7 @@
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
@@ -793,7 +793,7 @@
/**
* @}
*/
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
@@ -813,7 +813,7 @@
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode
* @{
*/
@@ -822,7 +822,7 @@
/**
* @}
*/
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/** @defgroup ADC_Event_type ADC Event type
@@ -833,9 +833,9 @@
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -849,14 +849,14 @@
#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC end of calibration interrupt source */
#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */
#else
#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
@@ -875,14 +875,14 @@
#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC end of calibration flag */
#define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */
#else
#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
@@ -940,11 +940,11 @@
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (8UL)))
#else
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
@@ -1026,7 +1026,7 @@
* @param __REGTRIG__ programmed ADC regular conversions external trigger.
* @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
@@ -1044,7 +1044,7 @@
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the ADC regular conversions check for converted data availability.
@@ -1062,17 +1062,17 @@
#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \
((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the ADC conversions sampling time.
* @param __TIME__ ADC conversions sampling time.
* @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5) || \
((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_7CYCLES_5) || \
@@ -1090,19 +1090,19 @@
((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \
((RANK) == ADC_RANK_NONE) )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the ADC regular channel setting.
* @param RANK programmed ADC regular channel.
* @retval SET (RANK is valid) or RESET (RANK is invalid)
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \
((RANK) == ADC_REGULAR_RANK_2 ) || \
((RANK) == ADC_REGULAR_RANK_3 ) || \
@@ -1155,9 +1155,9 @@
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U /* Internal definition to differentiate sequencer setting fixed or configurable */
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
@@ -1823,7 +1823,7 @@
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
@@ -1840,8 +1840,8 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
/**
* @}
@@ -1851,8 +1851,8 @@
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
+uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
/**
* @}
diff --git a/Inc/stm32wbxx_hal_adc_ex.h b/Inc/stm32wbxx_hal_adc_ex.h
index 53e3b71..5d3b804 100644
--- a/Inc/stm32wbxx_hal_adc_ex.h
+++ b/Inc/stm32wbxx_hal_adc_ex.h
@@ -40,7 +40,7 @@
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -184,7 +184,7 @@
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADCEx_injected_external_trigger_source ADC group injected trigger source
@@ -218,9 +218,9 @@
* @{
*/
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
/**
* @}
*/
@@ -237,7 +237,7 @@
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADCEx_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
@@ -256,7 +256,7 @@
* @{
*/
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
@@ -332,7 +332,7 @@
*/
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -386,7 +386,7 @@
*/
#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Enable ADC overrun mode.
* @param _OVERRUN_MODE_ Overrun mode.
@@ -426,7 +426,7 @@
(ADC_CFGR1_CHSELRMOD) \
)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Configure the ADC DMA continuous request.
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
@@ -462,13 +462,13 @@
* @param __THRESHOLD__ Value to be shifted
* @retval None
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL))
#else
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
@@ -481,7 +481,7 @@
* @param __THRESHOLD__ Value to be shifted
* @retval None
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) != (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0)) ? \
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
@@ -493,14 +493,14 @@
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
((__THRESHOLD__) << 2UL) \
)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Clear Common Control Register.
* @param __HANDLE__ ADC handle.
* @retval None
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
ADC_CCR_PRESC | \
ADC_CCR_VBATEN | \
@@ -512,7 +512,7 @@
ADC_CCR_VBATEN | \
ADC_CCR_TSEN | \
ADC_CCR_VREFEN )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
@@ -536,7 +536,7 @@
*/
#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -612,12 +612,12 @@
* @param __SING_DIFF__ programmed channel setting.
* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) ((__SING_DIFF__) == ADC_SINGLE_ENDED)
#else
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the ADC offset management setting.
@@ -630,7 +630,7 @@
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -673,20 +673,20 @@
* @param __WATCHDOG__ programmed ADC analog watchdog setting.
* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1)
#else
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the ADC analog watchdog mode setting.
* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) )
@@ -700,10 +700,10 @@
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the ADC conversion (regular or injected or both).
@@ -719,7 +719,7 @@
* @param __EVENT__ ADC event.
* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
((__EVENT__) == ADC_AWD1_EVENT) || \
((__EVENT__) == ADC_AWD2_EVENT) || \
@@ -734,7 +734,7 @@
((__EVENT__) == ADC_JQOVF_EVENT) )
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -750,7 +750,7 @@
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the ADC oversampling shift.
@@ -775,7 +775,7 @@
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#else
/**
* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
@@ -784,7 +784,7 @@
*/
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Verify the DFSDM mode configuration.
@@ -823,11 +823,11 @@
/* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
-uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
uint32_t CalibrationFactor);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* Blocking mode: Polling */
@@ -840,15 +840,15 @@
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
#endif /* ADC_SUPPORT_2_5_MSPS */
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
@@ -858,7 +858,7 @@
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* ADC group regular conversions stop */
@@ -874,23 +874,23 @@
* @{
*/
/* Peripheral Control functions ***********************************************/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef* sConfigInjected);
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
#endif /* ADC_SUPPORT_2_5_MSPS */
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */
#else
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
diff --git a/Inc/stm32wbxx_hal_comp.h b/Inc/stm32wbxx_hal_comp.h
index 19f3928..a6676b2 100644
--- a/Inc/stm32wbxx_hal_comp.h
+++ b/Inc/stm32wbxx_hal_comp.h
@@ -708,7 +708,7 @@
* @{
*/
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp);
/* Callback in interrupt mode */
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
/**
@@ -719,8 +719,8 @@
/** @addtogroup COMP_Exported_Functions_Group4
* @{
*/
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
-uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
+HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp);
+uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp);
/**
* @}
*/
diff --git a/Inc/stm32wbxx_hal_conf_template.h b/Inc/stm32wbxx_hal_conf_template.h
index 25779f2..629786c 100644
--- a/Inc/stm32wbxx_hal_conf_template.h
+++ b/Inc/stm32wbxx_hal_conf_template.h
@@ -21,7 +21,7 @@
#define STM32WBxx_HAL_CONF_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
@@ -96,11 +96,11 @@
*/
#if !defined (HSE_VALUE)
- #define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
+#define HSE_VALUE (32000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
- #define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
+#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
@@ -108,7 +108,7 @@
* This value is the default MSI range value after Reset.
*/
#if !defined (MSI_VALUE)
- #define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
+#define MSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* MSI_VALUE */
/**
@@ -117,22 +117,22 @@
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
- #define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
+#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI1) value.
*/
-#if !defined (LSI1_VALUE)
- #define LSI1_VALUE (32000UL) /*!< LSI1 Typical Value in Hz*/
+#if !defined (LSI1_VALUE)
+#define LSI1_VALUE (32000UL) /*!< LSI1 Typical Value in Hz*/
#endif /* LSI1_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
/**
* @brief Internal Low Speed oscillator (LSI2) value.
*/
-#if !defined (LSI2_VALUE)
- #define LSI2_VALUE (32000UL) /*!< LSI2 Typical Value in Hz*/
+#if !defined (LSI2_VALUE)
+#define LSI2_VALUE (32000UL) /*!< LSI2 Typical Value in Hz*/
#endif /* LSI2_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature.*/
@@ -142,7 +142,11 @@
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
- #define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
+#if defined(STM32WB5Mxx)
+#define LSE_VALUE (32774UL) /*!< Value of the LSE oscillator in Hz */
+#else
+#define LSE_VALUE (32768UL) /*!< Value of the LSE oscillator in Hz */
+#endif /* STM32WB5Mxx */
#endif /* LSE_VALUE */
/**
@@ -150,20 +154,20 @@
* This value is the default HSI48 range value after Reset.
*/
#if !defined (HSI48_VALUE)
- #define HSI48_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/
+#define HSI48_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI48_VALUE */
-
+
#if !defined (LSE_STARTUP_TIMEOUT)
- #define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
+#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for SAI1 peripheral
- * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+ * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
* frequency.
*/
#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
- #define EXTERNAL_SAI1_CLOCK_VALUE (48000UL) /*!< Value of the SAI1 External clock source in Hz*/
+#define EXTERNAL_SAI1_CLOCK_VALUE (48000UL) /*!< Value of the SAI1 External clock source in Hz*/
#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
@@ -201,131 +205,131 @@
* @brief Include module's header file
*/
#ifdef HAL_DMA_MODULE_ENABLED
- #include "stm32wbxx_hal_dma.h"
+#include "stm32wbxx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32wbxx_hal_adc.h"
+#include "stm32wbxx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
- #include "stm32wbxx_hal_comp.h"
+#include "stm32wbxx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32wbxx_hal_cortex.h"
+#include "stm32wbxx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32wbxx_hal_crc.h"
+#include "stm32wbxx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32wbxx_hal_cryp.h"
+#include "stm32wbxx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
- #include "stm32wbxx_hal_exti.h"
+#include "stm32wbxx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
-
+
#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32wbxx_hal_flash.h"
+#include "stm32wbxx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32wbxx_hal_gpio.h"
+#include "stm32wbxx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_HSEM_MODULE_ENABLED
- #include "stm32wbxx_hal_hsem.h"
+#include "stm32wbxx_hal_hsem.h"
#endif /* HAL_HSEM_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32wbxx_hal_i2c.h"
+#include "stm32wbxx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_IPCC_MODULE_ENABLED
- #include "stm32wbxx_hal_ipcc.h"
+#include "stm32wbxx_hal_ipcc.h"
#endif /* HAL_IPCC_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32wbxx_hal_irda.h"
+#include "stm32wbxx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32wbxx_hal_iwdg.h"
+#include "stm32wbxx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32wbxx_hal_lcd.h"
+#include "stm32wbxx_hal_lcd.h"
#endif /* HAL_LCD_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32wbxx_hal_lptim.h"
+#include "stm32wbxx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32wbxx_hal_pcd.h"
+#include "stm32wbxx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PKA_MODULE_ENABLED
- #include "stm32wbxx_hal_pka.h"
+#include "stm32wbxx_hal_pka.h"
#endif /* HAL_PKA_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32wbxx_hal_pwr.h"
+#include "stm32wbxx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32wbxx_hal_qspi.h"
+#include "stm32wbxx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32wbxx_hal_rcc.h"
+#include "stm32wbxx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32wbxx_hal_rng.h"
+#include "stm32wbxx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
-
+
#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32wbxx_hal_rtc.h"
+#include "stm32wbxx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32wbxx_hal_sai.h"
+#include "stm32wbxx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32wbxx_hal_smartcard.h"
+#include "stm32wbxx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32wbxx_hal_smbus.h"
+#include "stm32wbxx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32wbxx_hal_spi.h"
+#include "stm32wbxx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32wbxx_hal_tim.h"
+#include "stm32wbxx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
- #include "stm32wbxx_hal_tsc.h"
+#include "stm32wbxx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32wbxx_hal_uart.h"
+#include "stm32wbxx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32wbxx_hal_usart.h"
+#include "stm32wbxx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32wbxx_hal_wwdg.h"
+#include "stm32wbxx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
@@ -338,11 +342,11 @@
* If expr is true, it returns no value.
* @retval None
*/
- #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
+void assert_failed(uint8_t *file, uint32_t line);
#else
- #define assert_param(expr) ((void)0U)
+#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
diff --git a/Inc/stm32wbxx_hal_def.h b/Inc/stm32wbxx_hal_def.h
index 5c48d6c..95ac1c5 100644
--- a/Inc/stm32wbxx_hal_def.h
+++ b/Inc/stm32wbxx_hal_def.h
@@ -22,7 +22,7 @@
#define __STM32WBxx_HAL_DEF
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -55,7 +55,7 @@
/* Exported macros -----------------------------------------------------------*/
#ifndef UNUSED
#define UNUSED(X) (void)(X) /* To avoid gcc/g++ warnings */
-#endif
+#endif /* UNUSED */
#define HAL_MAX_DELAY 0xFFFFFFFFU
@@ -63,18 +63,18 @@
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
- do{ \
- (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
- (__DMA_HANDLE__).Parent = (__HANDLE__); \
- } while(0)
+ do{ \
+ (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+ (__DMA_HANDLE__).Parent = (__HANDLE__); \
+ } while(0)
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
- * @note This macro can be used for the following purpose:
+ * @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
- * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
+ * to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
- * Otherwise, "State" field may have any random value and the first time the function
+ * Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
@@ -86,71 +86,71 @@
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1)
- /* Reserved for future use */
- #error " USE_RTOS should be 0 in the current HAL release "
+/* Reserved for future use */
+#error " USE_RTOS should be 0 in the current HAL release "
#else
- #define __HAL_LOCK(__HANDLE__) \
- do{ \
- if((__HANDLE__)->Lock == HAL_LOCKED) \
- { \
- return HAL_BUSY; \
- } \
- else \
- { \
- (__HANDLE__)->Lock = HAL_LOCKED; \
- } \
- }while (0)
+#define __HAL_LOCK(__HANDLE__) \
+ do { \
+ if((__HANDLE__)->Lock == HAL_LOCKED) \
+ { \
+ return HAL_BUSY; \
+ } \
+ else \
+ { \
+ (__HANDLE__)->Lock = HAL_LOCKED; \
+ } \
+ } while (0)
- #define __HAL_UNLOCK(__HANDLE__) \
- do{ \
- (__HANDLE__)->Lock = HAL_UNLOCKED; \
- }while (0)
+#define __HAL_UNLOCK(__HANDLE__) \
+ do { \
+ (__HANDLE__)->Lock = HAL_UNLOCKED; \
+ } while (0)
#endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
- #ifndef __weak
- #define __weak __attribute__((weak))
- #endif
- #ifndef __packed
- #define __packed __attribute__((packed))
- #endif
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif /* __packed */
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
- #ifndef __weak
- #define __weak __attribute__((weak))
- #endif /* __weak */
- #ifndef __packed
- #define __packed __attribute__((__packed__))
- #endif /* __packed */
+#ifndef __weak
+#define __weak __attribute__((weak))
+#endif /* __weak */
+#ifndef __packed
+#define __packed __attribute__((__packed__))
+#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
- #ifndef __ALIGN_BEGIN
- #define __ALIGN_BEGIN
- #endif
- #ifndef __ALIGN_END
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #endif
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__ ((aligned (4)))
+#endif /* __ALIGN_END */
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
- #ifndef __ALIGN_END
- #define __ALIGN_END __attribute__ ((aligned (4)))
- #endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
- #define __ALIGN_BEGIN
- #endif /* __ALIGN_BEGIN */
+#ifndef __ALIGN_END
+#define __ALIGN_END __attribute__ ((aligned (4)))
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#define __ALIGN_BEGIN
+#endif /* __ALIGN_BEGIN */
#else
- #ifndef __ALIGN_END
- #define __ALIGN_END
- #endif /* __ALIGN_END */
- #ifndef __ALIGN_BEGIN
- #if defined (__CC_ARM) /* ARM Compiler V5 */
- #define __ALIGN_BEGIN __align(4)
- #elif defined (__ICCARM__) /* IAR Compiler */
- #define __ALIGN_BEGIN
- #endif /* __CC_ARM */
- #endif /* __ALIGN_BEGIN */
+#ifndef __ALIGN_END
+#define __ALIGN_END
+#endif /* __ALIGN_END */
+#ifndef __ALIGN_BEGIN
+#if defined (__CC_ARM) /* ARM Compiler V5 */
+#define __ALIGN_BEGIN __align(4)
+#elif defined (__ICCARM__) /* IAR Compiler */
+#define __ALIGN_BEGIN
+#endif /* __CC_ARM */
+#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
@@ -183,16 +183,16 @@
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))
-#endif
+#endif /* __CC_ARM || ... */
-/**
+/**
* @brief __NOINLINE definition
- */
+ */
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
-#define __NOINLINE __attribute__ ( (noinline) )
+#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
@@ -200,7 +200,7 @@
*/
#define __NOINLINE _Pragma("optimize = no_inline")
-#endif
+#endif /* __CC_ARM || ... */
#ifdef __cplusplus
diff --git a/Inc/stm32wbxx_hal_exti.h b/Inc/stm32wbxx_hal_exti.h
index 16ea441..a586d2d 100644
--- a/Inc/stm32wbxx_hal_exti.h
+++ b/Inc/stm32wbxx_hal_exti.h
@@ -108,38 +108,38 @@
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x14u)
#else
#define EXTI_LINE_20 (EXTI_RESERVED | EXTI_REG1 | 0x14u)
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || ... */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x15u)
#else
#define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15u)
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
#else
#define EXTI_LINE_23 (EXTI_RESERVED | EXTI_REG1 | 0x17u)
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx) || defined(STM32WB1Mxx)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#else
#define EXTI_LINE_25 (EXTI_RESERVED | EXTI_REG1 | 0x19u)
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || ... */
#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
#else
#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx) || defined(STM32WB1Mxx)
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
#else
#define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu)
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || ... */
#define EXTI_LINE_32 (EXTI_RESERVED | EXTI_REG2 | 0x00u)
#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
@@ -155,14 +155,14 @@
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
#else
#define EXTI_LINE_43 (EXTI_RESERVED | EXTI_REG2 | 0x0Bu)
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx */
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu)
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du)
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB50xx) || defined (STM32WB35xx) || defined (STM32WB30xx)
#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu)
#else
#define EXTI_LINE_46 (EXTI_RESERVED | EXTI_REG2 | 0x0Eu)
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || ... */
#define EXTI_LINE_47 (EXTI_RESERVED | EXTI_REG2 | 0x0Fu)
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10u)
/**
@@ -199,7 +199,7 @@
#define EXTI_GPIOC 0x00000002u
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define EXTI_GPIOD 0x00000003u
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx */
#define EXTI_GPIOE 0x00000004u
#define EXTI_GPIOH 0x00000007u
/**
@@ -273,14 +273,14 @@
* @{
*/
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
- ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
- (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
- (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
- (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
- (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
+ ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
+ (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
+ (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
+ (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
- (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+ (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
@@ -301,7 +301,7 @@
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOH))
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
diff --git a/Inc/stm32wbxx_hal_pcd.h b/Inc/stm32wbxx_hal_pcd.h
index e6dbbfc..71778ab 100644
--- a/Inc/stm32wbxx_hal_pcd.h
+++ b/Inc/stm32wbxx_hal_pcd.h
@@ -101,8 +101,8 @@
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
- PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
- PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
+ PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
+ PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
@@ -190,12 +190,12 @@
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
+#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \
+ ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
- & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
&= (uint16_t)(~(__INTERRUPT__)))
@@ -428,8 +428,6 @@
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
-/* ENDPOINT transfer */
-#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -789,7 +787,7 @@
{ \
(wNBlocks)--; \
} \
- *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
+ *(pdwReg) |= (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
@@ -799,13 +797,15 @@
{ \
(wNBlocks)++; \
} \
- *(pdwReg) = (uint16_t)((wNBlocks) << 10); \
+ *(pdwReg) |= (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
\
+ *(pdwReg) &= 0x3FFU; \
+ \
if ((wCount) > 62U) \
{ \
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
@@ -814,7 +814,6 @@
{ \
if ((wCount) == 0U) \
{ \
- *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
*(pdwReg) |= USB_CNTRX_BLSIZE; \
} \
else \
diff --git a/Inc/stm32wbxx_hal_rcc.h b/Inc/stm32wbxx_hal_rcc.h
index f8e45ec..50b7509 100644
--- a/Inc/stm32wbxx_hal_rcc.h
+++ b/Inc/stm32wbxx_hal_rcc.h
@@ -3221,7 +3221,7 @@
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source
diff --git a/Inc/stm32wbxx_hal_rtc.h b/Inc/stm32wbxx_hal_rtc.h
index 9d16d6c..bf85b1a 100644
--- a/Inc/stm32wbxx_hal_rtc.h
+++ b/Inc/stm32wbxx_hal_rtc.h
@@ -167,7 +167,7 @@
typedef struct __RTC_HandleTypeDef
#else
typedef struct
-#endif
+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
{
RTC_TypeDef *Instance; /*!< Register base address */
@@ -212,11 +212,11 @@
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */
#if defined(RTC_TAMPER1_SUPPORT)
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
-#endif
+#endif /* RTC_TAMPER1_SUPPORT */
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
#if defined(RTC_TAMPER3_SUPPORT)
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
} HAL_RTC_CallbackIDTypeDef;
@@ -263,7 +263,7 @@
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
#if defined(RTC_OR_ALARMOUTTYPE)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
-#endif
+#endif /* RTC_OR_ALARMOUTTYPE */
/**
* @}
*/
@@ -396,7 +396,7 @@
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
-*/
+ */
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
@@ -444,7 +444,7 @@
#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */
#if defined(RTC_TAMPER1_SUPPORT)
#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */
-#endif
+#endif /* RTC_TAMPER1_SUPPORT */
#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */
/**
@@ -458,12 +458,12 @@
#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#if defined(RTC_TAMPER1_SUPPORT)
#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
-#endif
+#endif /* RTC_TAMPER1_SUPPORT */
#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#if defined(RTC_ISR_ITSF)
#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
-#endif
+#endif /* RTC_ISR_ITSF */
#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
@@ -506,10 +506,10 @@
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xCAU; \
- (__HANDLE__)->Instance->WPR = 0x53U; \
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
+ do { \
+ (__HANDLE__)->Instance->WPR = 0xCAU; \
+ (__HANDLE__)->Instance->WPR = 0x53U; \
} while(0U)
/**
@@ -517,9 +517,9 @@
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
- do{ \
- (__HANDLE__)->Instance->WPR = 0xFFU; \
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
+ do { \
+ (__HANDLE__)->Instance->WPR = 0xFFU; \
} while(0U)
/**
@@ -533,13 +533,13 @@
* @arg @ref RTC_STOREOPERATION_SET
* @retval None
*/
-#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \
- do { \
- __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
- SET_BIT(RTC->CR, RTC_CR_ADD1H); \
- MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
- __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
- } while(0);
+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \
+ do { \
+ __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
+ SET_BIT(RTC->CR, RTC_CR_ADD1H); \
+ MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
+ __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
+ } while(0U);
/**
* @brief Subtract 1 hour (winter time change).
@@ -552,13 +552,13 @@
* @arg @ref RTC_STOREOPERATION_SET
* @retval None
*/
-#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \
- do { \
- __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
- SET_BIT(RTC->CR, RTC_CR_SUB1H); \
- MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
- __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
- } while(0);
+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \
+ do { \
+ __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
+ SET_BIT(RTC->CR, RTC_CR_SUB1H); \
+ MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
+ __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
+ } while(0U);
/**
* @brief Enable the RTC ALARMA peripheral.
@@ -620,7 +620,7 @@
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR\
- )& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)
+ ) & ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U)
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
@@ -739,19 +739,21 @@
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
-#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
@@ -786,6 +788,12 @@
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
/*----------------------------*/
+/**
+ * @brief Check whether if the RTC Calendar is initialized.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @retval None
+ */
+#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ISR) & (RTC_ISR_INITS)) == RTC_ISR_INITS) ? 1U : 0U)
/**
* @}
@@ -892,7 +900,7 @@
#define RTC_TIMEOUT_VALUE 1000U
-#define RTC_EXTI_LINE_ALARM_EVENT (LL_EXTI_LINE_17) /*!< External interrupt line connected to the RTC Alarm event */
+#define RTC_EXTI_LINE_ALARM_EVENT (LL_EXTI_LINE_17) /*!< External interrupt line connected to the RTC Alarm event */
/**
* @}
@@ -918,7 +926,7 @@
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
#else
#define IS_RTC_OUTPUT_TYPE(TYPE) ((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN)
-#endif
+#endif /* RTC_OUTPUT_TYPE_PUSHPULL */
#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
((REMAP) == RTC_OUTPUT_REMAP_POS1))
diff --git a/Inc/stm32wbxx_hal_rtc_ex.h b/Inc/stm32wbxx_hal_rtc_ex.h
index db55244..f660fb0 100644
--- a/Inc/stm32wbxx_hal_rtc_ex.h
+++ b/Inc/stm32wbxx_hal_rtc_ex.h
@@ -47,19 +47,19 @@
typedef struct
{
uint32_t Tamper; /*!< Specifies the Tamper Pin.
- This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */
uint32_t Interrupt; /*!< Specifies the Tamper Interrupt.
- This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
- This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */
uint32_t NoErase; /*!< Specifies the Tamper no erase mode.
- This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */
uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking.
- This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */
+ This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */
uint32_t Filter; /*!< Specifies the RTC Filter Tamper.
This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
@@ -222,7 +222,7 @@
#define RTC_TAMPERFILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4
consecutive samples at the active level */
#define RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8
- consecutive samples at the active leve. */
+ consecutive samples at the active level */
/**
* @}
@@ -231,7 +231,7 @@
/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions
* @{
*/
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled
+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000U) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 32768 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 16384 */
@@ -246,8 +246,8 @@
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2)) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 512 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1 | \
- RTC_TAMPCR_TAMPFREQ_2)) /*!< Each of the tamper inputs are sampled
-with a frequency = RTCCLK / 256 */
+ RTC_TAMPCR_TAMPFREQ_2)) /*!< Each of the tamper inputs are sampled
+ with a frequency = RTCCLK / 256 */
/**
* @}
@@ -256,7 +256,7 @@
/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions
* @{
*/
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before
+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before
sampling during 1 RTCCLK cycle */
#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
sampling during 2 RTCCLK cycles */
@@ -273,7 +273,7 @@
* @{
*/
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */
+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */
/**
* @}
@@ -282,7 +282,7 @@
/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTCEx Tamper Pull UP Definitions
* @{
*/
-#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling */
+#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling */
#define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */
/**
@@ -305,7 +305,7 @@
/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
* @{
*/
-#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation
+#define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 32s, else 2exp20 RTCCLK pulses */
#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation
period is 16s, else 2exp19 RTCCLK pulses */
@@ -322,7 +322,7 @@
#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
during a X -second window = Y - CALM[8:0]
with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U) /*!< The number of RTCCLK pulses subbstited
+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000U) /*!< The number of RTCCLK pulses subbstited
during a 32-second window = CALM[8:0] */
/**
@@ -349,10 +349,10 @@
*/
/** @defgroup RTCEx_Interrupts_Definitions RTCEx Interrupts Definitions
* @{
-*/
+ */
#if defined(RTC_TAMPER3_SUPPORT)
-#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt */
-#endif
+#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt */
+#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
*/
@@ -362,7 +362,7 @@
*/
#if defined(RTC_TAMPER3_SUPPORT)
#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
*/
@@ -376,7 +376,7 @@
* @{
*/
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
+/* ---------------------------------WAKEUPTIMER-------------------------------*/
/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
* @{
*/
@@ -541,20 +541,22 @@
* @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.
* This parameter can be:
* @retval None
*/
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
* @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not of core 1.
@@ -799,7 +801,7 @@
#else
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__)\
== RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U))
-#endif
+#endif /* RTC_TAMPER1_SUPPORT || RTC_TAMPER3_SUPPORT */
/**************************************************************************************************/
@@ -893,7 +895,7 @@
*/
#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__)\
| RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-#endif
+#endif /* RTC_INTERNALTS_SUPPORT */
/**************************************************************************************************/
/**
@@ -986,20 +988,22 @@
* @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
- } while(0U)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \
+ } while(0U)
/**
* @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.
* This parameter can be:
* @retval None.
*/
-#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \
- __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
- } while(0U)
+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() \
+ do { \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \
+ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \
+ } while(0U)
/**
* @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not of core 1.
@@ -1106,7 +1110,7 @@
#if defined(RTC_INTERNALTS_SUPPORT)
HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
-#endif
+#endif /* RTC_INTERNALTS_SUPPORT */
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
@@ -1220,7 +1224,7 @@
#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP2E))
#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER2_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
-#endif
+#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT (EXTI_IMR1_IM18) /*!< External interrupt line 18 Connected to the RTC Tamper and Time Stamp events */
#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT (EXTI_IMR1_IM19) /*!< External interrupt line 19 Connected to the RTC Wakeup event */
@@ -1256,9 +1260,9 @@
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
- ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
+ ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))
#define IS_RTC_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
diff --git a/Inc/stm32wbxx_hal_tim_ex.h b/Inc/stm32wbxx_hal_tim_ex.h
index dd7c879..194bc42 100644
--- a/Inc/stm32wbxx_hal_tim_ex.h
+++ b/Inc/stm32wbxx_hal_tim_ex.h
@@ -85,59 +85,59 @@
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
-#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< TIM1_ETR is not connected to I/O */
-#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_GPIO 0x00000000U /*!< TIM1_ETR is not connected to I/O */
+#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR_ETR_ADC1_RMP_0 /*!< TIM1_ETR is connected to ADC1 AWD1 */
#if defined(ADC_SUPPORT_5_MSPS)
-#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR_ETR_ADC1_RMP_1 /*!< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1) /*!< TIM1_ETR is connected to ADC1 AWD3 */
#endif
#if defined(COMP1)
-#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
+#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */
#endif /* COMP1 */
#if defined(COMP2)
-#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
+#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */
#endif /* COMP2 */
-#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 Input capture 1 is connected to I/0 */
-#define TIM_TIM1_TI1_COMP1 TIM1_OR_TI1_RMP /* !< TIM1 Input capture 1is connected to COMP1 OUT */
+#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1 Input capture 1 is connected to I/0 */
+#define TIM_TIM1_TI1_COMP1 TIM1_OR_TI1_RMP /*!< TIM1 Input capture 1is connected to COMP1 OUT */
-#define TIM_TIM2_ITR_NC 0x00000000U /* !< TIM2 Internal trigger ITR is not connected */
+#define TIM_TIM2_ITR_NC 0x00000000U /*!< TIM2 Internal trigger ITR is not connected */
#if defined(USB)
-#define TIM_TIM2_ITR_USB TIM2_OR_ITR1_RMP /* !< TIM2 Internal trigger ITR is connected to USBFS SOF */
+#define TIM_TIM2_ITR_USB TIM2_OR_ITR1_RMP /*!< TIM2 Internal trigger ITR is connected to USBFS SOF */
#endif /* USB */
-#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2 External trigger ETR is connected to I/O */
-#define TIM_TIM2_ETR_LSE TIM2_OR_ETR_RMP /* !< TIM2 External trigger ETR is connected to LSE */
+#define TIM_TIM2_ETR_GPIO 0x00000000U /*!< TIM2 External trigger ETR is connected to I/O */
+#define TIM_TIM2_ETR_LSE TIM2_OR_ETR_RMP /*!< TIM2 External trigger ETR is connected to LSE */
#if defined(COMP1)
-#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
+#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */
#endif /* COMP1 */
#if defined(COMP2)
-#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
+#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */
#endif /* COMP2 */
-#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to I/O */
+#define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2_TI4 is connected to I/O */
#if defined(COMP1)
-#define TIM_TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_0 /* !< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_0 /*!< TIM2_TI4 is connected to COMP1 OUT */
#endif /* COMP1 */
#if defined(COMP2)
-#define TIM_TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_1 /* !< TIM2_TI4 is connected to COMP1 OUT */
+#define TIM_TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_1 /*!< TIM2_TI4 is connected to COMP1 OUT */
#endif /* COMP2 */
#if defined(COMP1) && defined(COMP2)
-#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */
+#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1) /*!< TIM2_TI4 is connected to COMP1 and COMP2 OUT */
#endif /* COMP1 && COMP2 */
#if defined(TIM16)
-#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */
-#define TIM_TIM16_TI1_LSI TIM16_OR_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */
-#define TIM_TIM16_TI1_LSE TIM16_OR_TI1_RMP_1 /* !< TIM16_TI1 is connected to LSE Clock */
-#define TIM_TIM16_TI1_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_TI1_RMP_1) /* !< TIM16_TI1 is connected to RTC */
+#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16_TI1 is connected to I/O */
+#define TIM_TIM16_TI1_LSI TIM16_OR_TI1_RMP_0 /*!< TIM16_TI1 is connected to LSI Clock */
+#define TIM_TIM16_TI1_LSE TIM16_OR_TI1_RMP_1 /*!< TIM16_TI1 is connected to LSE Clock */
+#define TIM_TIM16_TI1_RTC (TIM16_OR_TI1_RMP_0 | TIM16_OR_TI1_RMP_1) /*!< TIM16_TI1 is connected to RTC */
#endif /* TIM16 */
#if defined(TIM17)
-#define TIM_TIM17_TI1_GPIO 0x00000000U /* !< TIM17_TI1 is connected to I/O */
-#define TIM_TIM17_TI1_MSI TIM17_OR_TI1_RMP_0 /* !< TIM17_TI1 is connected to MSI */
-#define TIM_TIM17_TI1_HSE TIM17_OR_TI1_RMP_1 /* !< TIM17_TI1 is connected to HSE/32 */
-#define TIM_TIM17_TI1_MCO (TIM17_OR_TI1_RMP_0 | TIM17_OR_TI1_RMP_1) /* !< TIM17_TI1 is connected to MCO */
+#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17_TI1 is connected to I/O */
+#define TIM_TIM17_TI1_MSI TIM17_OR_TI1_RMP_0 /*!< TIM17_TI1 is connected to MSI */
+#define TIM_TIM17_TI1_HSE TIM17_OR_TI1_RMP_1 /*!< TIM17_TI1 is connected to HSE/32 */
+#define TIM_TIM17_TI1_MCO (TIM17_OR_TI1_RMP_0 | TIM17_OR_TI1_RMP_1) /*!< TIM17_TI1 is connected to MCO */
#endif /* TIM17 */
/**
* @}
@@ -155,12 +155,12 @@
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{
*/
-#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
+#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */
#if defined(COMP1)
-#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */
#endif /* COMP1 */
#if defined(COMP2)
-#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */
#endif /* COMP2 */
/**
* @}
diff --git a/Inc/stm32wbxx_hal_uart.h b/Inc/stm32wbxx_hal_uart.h
index 9344225..a4b25fe 100644
--- a/Inc/stm32wbxx_hal_uart.h
+++ b/Inc/stm32wbxx_hal_uart.h
@@ -196,7 +196,7 @@
/**
* @brief HAL UART Reception type definition
* @note HAL UART Reception type value aims to identify which type of Reception is ongoing.
- * It is expected to admit following values :
+ * This parameter can be a value of @ref UART_Reception_Type_Values :
* HAL_UART_RECEPTION_STANDARD = 0x00U,
* HAL_UART_RECEPTION_TOIDLE = 0x01U,
* HAL_UART_RECEPTION_TORTO = 0x02U,
@@ -205,6 +205,17 @@
typedef uint32_t HAL_UART_RxTypeTypeDef;
/**
+ * @brief HAL UART Rx Event type definition
+ * @note HAL UART Rx Event type value aims to identify which type of Event has occurred
+ * leading to call of the RxEvent callback.
+ * This parameter can be a value of @ref UART_RxEvent_Type_Values :
+ * HAL_UART_RXEVENT_TC = 0x00U,
+ * HAL_UART_RXEVENT_HT = 0x01U,
+ * HAL_UART_RXEVENT_IDLE = 0x02U,
+ */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
+/**
* @brief UART handle Structure definition
*/
typedef struct __UART_HandleTypeDef
@@ -238,6 +249,8 @@
__IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */
+ __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */
+
void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
@@ -806,7 +819,7 @@
* @}
*/
-/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values
+/** @defgroup UART_Reception_Type_Values UART Reception type values
* @{
*/
#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */
@@ -817,6 +830,16 @@
* @}
*/
+/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values
+ * @{
+ */
+#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */
+#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */
+/**
+ * @}
+ */
+
/**
* @}
*/
diff --git a/Inc/stm32wbxx_hal_uart_ex.h b/Inc/stm32wbxx_hal_uart_ex.h
index 986c712..e80ffe8 100644
--- a/Inc/stm32wbxx_hal_uart_ex.h
+++ b/Inc/stm32wbxx_hal_uart_ex.h
@@ -177,6 +177,8 @@
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
+
/**
* @}
diff --git a/Inc/stm32wbxx_ll_adc.h b/Inc/stm32wbxx_ll_adc.h
index 9342e62..f39779f 100644
--- a/Inc/stm32wbxx_ll_adc.h
+++ b/Inc/stm32wbxx_ll_adc.h
@@ -52,7 +52,7 @@
/* Internal register offset for ADC group regular sequencer configuration */
/* (offset placed into a spare area of literal definition) */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* No register ADC_SQRx on this ADC peripheral version */
#else
#define ADC_SQR1_REGOFFSET (0x00000000UL)
@@ -67,7 +67,7 @@
/* Definition of ADC group regular sequencer bits information to be inserted */
/* into ADC group regular sequencer ranks literals definition. */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Value equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
@@ -190,13 +190,13 @@
/* - channel sampling time defined by SMPRx register offset */
/* and SMPx bits positions into SMPRx register */
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
#else
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#endif
#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Value equivalent to ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, if set to mode "fully configurable", can contain channels with a restricted channel number. Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
#endif
#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
@@ -242,7 +242,7 @@
/* Definition of channels ID bitfield information to be inserted into */
/* channels literals definition. */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
@@ -307,7 +307,7 @@
#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Internal mask for ADC channel sampling time: */
/* To select into literals LL_ADC_SAMPLINGTIME_x */
/* the relevant bits for: */
@@ -358,7 +358,7 @@
#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
#else
@@ -388,7 +388,7 @@
#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
/* ADC registers bits positions */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Value equivalent to bitfield "ADC_CFGR1_RES" position in register */
#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Value equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
#define ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to bitfield "ADC_TR_HT" position in register */
@@ -426,7 +426,7 @@
/* ADC registers bits groups */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
#else
#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
@@ -521,7 +521,7 @@
*/
typedef struct
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
@note On this STM32 series, this parameter has some clock ratio constraints:
@@ -609,7 +609,7 @@
} LL_ADC_REG_InitTypeDef;
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -677,7 +677,7 @@
* @{
*/
#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */
#else
#endif /* ADC_SUPPORT_2_5_MSPS */
@@ -691,7 +691,7 @@
#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
@@ -703,7 +703,7 @@
* @{
*/
#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */
#else
#endif /* ADC_SUPPORT_2_5_MSPS */
@@ -717,7 +717,7 @@
#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */
#endif /* ADC_SUPPORT_2_5_MSPS */
/**
@@ -738,7 +738,7 @@
/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
@@ -775,7 +775,7 @@
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
* @{
*/
@@ -812,7 +812,7 @@
* @{
*/
#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */
#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
@@ -832,7 +832,7 @@
* @}
*/
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels
* @{
*/
@@ -867,7 +867,7 @@
* @{
*/
#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
#endif /* !ADC_SUPPORT_2_5_MSPS */
@@ -878,7 +878,7 @@
/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
@@ -996,7 +996,7 @@
* @}
*/
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility
* @{
*/
@@ -1041,7 +1041,7 @@
* @}
*/
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
* @{
*/
@@ -1056,7 +1056,7 @@
* @{
*/
#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
#else
#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
@@ -1075,7 +1075,7 @@
/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
@@ -1106,7 +1106,7 @@
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
@@ -1187,7 +1187,7 @@
/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */
#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */
@@ -1213,7 +1213,7 @@
/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_SINGLE_ENDED (0x00000000UL) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
#else
#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
@@ -1228,7 +1228,7 @@
* @{
*/
#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */
#else
#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
@@ -1241,7 +1241,7 @@
/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
@@ -1361,7 +1361,7 @@
/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */
#else
@@ -1379,7 +1379,7 @@
* @{
*/
#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
#else
#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
@@ -1601,7 +1601,7 @@
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
@@ -1764,7 +1764,7 @@
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Helper macro to define ADC analog watchdog parameter:
* define a single channel to monitor with analog watchdog
@@ -2356,7 +2356,7 @@
* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
* @retval ADC register address
*/
-__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
{
/* Prevent unused argument(s) compilation warning */
(void)(Register);
@@ -2415,7 +2415,7 @@
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
#else
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
@@ -2447,9 +2447,9 @@
*
* (*) Value available on all STM32 devices except: STM32W10xxx, STM32W15xxx.
*/
-__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
#else
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
@@ -2586,7 +2586,7 @@
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
-__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));
}
@@ -2599,7 +2599,7 @@
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Set ADC instance clock source and prescaler.
* @note On this STM32 series, setting of this feature is conditioned to
@@ -2653,7 +2653,7 @@
}
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Set ADC calibration factor in the mode single-ended
* or differential (for devices with differential mode available).
@@ -2729,7 +2729,7 @@
}
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Get ADC calibration factor in the mode single-ended
* or differential (for devices with differential mode available).
@@ -2743,7 +2743,7 @@
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00 and Max_Data=0x7F
*/
-__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
}
@@ -2764,7 +2764,7 @@
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval Value between Min_Data=0x00 and Max_Data=0x7F
*/
-__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
{
/* Retrieve bits with position in register depending on parameter */
/* "SingleDiff". */
@@ -2792,7 +2792,7 @@
*/
__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
@@ -2811,9 +2811,9 @@
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
*/
-__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
@@ -2837,7 +2837,7 @@
*/
__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
@@ -2854,9 +2854,9 @@
* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
* @arg @ref LL_ADC_DATA_ALIGN_LEFT
*/
-__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
@@ -2920,7 +2920,7 @@
*/
__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
@@ -2977,16 +2977,16 @@
*
* (1) On STM32WB series, parameter available only on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
*/
-__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
#endif /* ADC_SUPPORT_2_5_MSPS */
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Set ADC trigger frequency mode.
* @note ADC trigger frequency mode must be set to low frequency when
@@ -3030,7 +3030,7 @@
}
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Set sampling time common to a group of channels.
* @note Unit: ADC clock cycles.
@@ -3120,7 +3120,7 @@
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC offset" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -3258,7 +3258,7 @@
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
-__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
@@ -3284,7 +3284,7 @@
* @arg @ref LL_ADC_OFFSET_4
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
@@ -3343,7 +3343,7 @@
* @arg @ref LL_ADC_OFFSET_DISABLE
* @arg @ref LL_ADC_OFFSET_ENABLE
*/
-__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
@@ -3403,7 +3403,7 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
@@ -3442,9 +3442,9 @@
* (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
* (2) On STM32WB series, parameter available only devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
__IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
@@ -3484,9 +3484,9 @@
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
#else
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
@@ -3510,7 +3510,7 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
@@ -3527,16 +3527,16 @@
* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
#endif /* ADC_SUPPORT_2_5_MSPS */
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Set ADC group regular sequencer configuration flexibility.
* @note On this STM32 series, ADC group regular sequencer both modes
@@ -3670,7 +3670,7 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
SET_BIT(ADCx->CHSELR, SequencerNbRanks);
#else
MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
@@ -3737,9 +3737,9 @@
*
* (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
__IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
uint32_t RankIndex;
@@ -3831,7 +3831,7 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
@@ -3858,9 +3858,9 @@
*
* (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
@@ -3961,7 +3961,7 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Set bits with content of parameter "Channel" with bits position */
/* in register depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
@@ -4068,9 +4068,9 @@
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t) ((READ_BIT(ADCx->CHSELR,
ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
@@ -4086,7 +4086,7 @@
#endif /* ADC_SUPPORT_2_5_MSPS */
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Set ADC group regular sequence: channel on rank corresponding to
* channel number.
@@ -4464,7 +4464,7 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
@@ -4483,9 +4483,9 @@
* @arg @ref LL_ADC_REG_CONV_SINGLE
* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
@@ -4527,7 +4527,7 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
@@ -4562,9 +4562,9 @@
* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
@@ -4594,7 +4594,7 @@
*/
__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
#else
MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
@@ -4610,9 +4610,9 @@
* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
@@ -4623,7 +4623,7 @@
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
@@ -4688,7 +4688,7 @@
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
{
__IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
@@ -4715,7 +4715,7 @@
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
}
@@ -4750,7 +4750,7 @@
* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
}
@@ -4797,7 +4797,7 @@
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
}
@@ -4830,7 +4830,7 @@
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
}
@@ -4955,7 +4955,7 @@
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
{
return (uint32_t)((READ_BIT(ADCx->JSQR,
(ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
@@ -5007,7 +5007,7 @@
* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
}
@@ -5068,7 +5068,7 @@
* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
}
@@ -5277,7 +5277,7 @@
* @{
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Set sampling time of the selected ADC channel
* Unit: ADC clock cycles.
@@ -5450,7 +5450,7 @@
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->SMPR,
@@ -5471,7 +5471,7 @@
}
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Get sampling time of the selected ADC channel
* Unit: ADC clock cycles.
@@ -5533,7 +5533,7 @@
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
*/
-__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
{
__IO uint32_t smpr = READ_REG(ADCx->SMPR);
@@ -5614,9 +5614,9 @@
* @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
*/
-__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
__IO uint32_t smpr = READ_REG(ADCx->SMPR);
/* Retrieve sampling time bit corresponding to the selected channel */
@@ -5638,7 +5638,7 @@
}
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC channel differential mode" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -5739,7 +5739,7 @@
* @arg @ref LL_ADC_CHANNEL_15
* @retval 0: channel in single-ended mode, else: channel in differential mode
*/
-__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
{
return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
}
@@ -5876,7 +5876,7 @@
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Prevent unused argument(s) compilation warning */
(void)(AWDy);
@@ -6021,9 +6021,9 @@
* (0) On STM32WB, parameter available only on analog watchdog number: AWD1.
* (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
*/
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Prevent unused argument(s) compilation warning */
(void)(AWDy);
@@ -6171,7 +6171,7 @@
/* "AWDy". */
/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
/* containing other bits reserved for other purpose. */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Prevent unused argument(s) compilation warning */
(void)(AWDy);
@@ -6252,7 +6252,7 @@
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Prevent unused argument(s) compilation warning */
(void)(AWDy);
@@ -6299,9 +6299,9 @@
* @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Prevent unused argument(s) compilation warning */
(void)(AWDy);
@@ -6323,7 +6323,7 @@
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC oversampling" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
@@ -6359,7 +6359,7 @@
*/
__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
#else
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
@@ -6388,9 +6388,9 @@
*
* (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
*/
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
@@ -6421,7 +6421,7 @@
*/
__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
#else
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
@@ -6442,9 +6442,9 @@
* @arg @ref LL_ADC_OVS_REG_CONT
* @arg @ref LL_ADC_OVS_REG_DISCONT
*/
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
#else
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
@@ -6505,7 +6505,7 @@
* @arg @ref LL_ADC_OVS_RATIO_128
* @arg @ref LL_ADC_OVS_RATIO_256
*/
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
}
@@ -6526,7 +6526,7 @@
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
*/
-__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
}
@@ -6593,7 +6593,7 @@
* @param ADCx ADC instance
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
*/
-__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
}
@@ -6643,7 +6643,7 @@
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
-__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
}
@@ -6703,7 +6703,7 @@
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
}
@@ -6714,12 +6714,12 @@
* @param ADCx ADC instance
* @retval 0: no ADC disable command on going.
*/
-__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
@@ -6735,6 +6735,9 @@
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
+ * @note In case of usage of feature auto power-off:
+ * This mode must be disabled during calibration
+ * Refer to function @ref LL_ADC_SetLowPowerMode().
* @rmtoll CR ADCAL LL_ADC_StartCalibration\n
* CR ADCALDIF LL_ADC_StartCalibration
* @param ADCx ADC instance
@@ -6790,7 +6793,7 @@
* @param ADCx ADC instance
* @retval 0: calibration complete, 1: calibration in progress.
*/
-__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
}
@@ -6857,7 +6860,7 @@
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
}
@@ -6868,7 +6871,7 @@
* @param ADCx ADC instance
* @retval 0: no command of conversion stop is on going on ADC group regular.
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
}
@@ -6882,7 +6885,7 @@
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
-__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
@@ -6897,7 +6900,7 @@
* @param ADCx ADC instance
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
{
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
@@ -6912,7 +6915,7 @@
* @param ADCx ADC instance
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
-__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
{
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
@@ -6927,7 +6930,7 @@
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
{
return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
@@ -6942,7 +6945,7 @@
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/
-__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
{
return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
@@ -6951,7 +6954,7 @@
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
@@ -7012,7 +7015,7 @@
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
}
@@ -7023,7 +7026,7 @@
* @param ADCx ADC instance
* @retval 0: no command of conversion stop is on going on ADC group injected.
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
}
@@ -7045,7 +7048,7 @@
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
-__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
@@ -7072,7 +7075,7 @@
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
-__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
@@ -7099,7 +7102,7 @@
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
-__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
@@ -7126,7 +7129,7 @@
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
-__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
@@ -7153,7 +7156,7 @@
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/
-__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
@@ -7180,12 +7183,12 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Get flag ADC channel configuration ready.
* @note Duration of ADC channel configuration ready: CCRDY handshake
@@ -7195,7 +7198,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
}
@@ -7208,7 +7211,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
}
@@ -7219,7 +7222,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
}
@@ -7230,7 +7233,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
}
@@ -7241,12 +7244,12 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -7255,7 +7258,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
}
@@ -7266,7 +7269,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
}
@@ -7277,7 +7280,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
}
@@ -7289,7 +7292,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
}
@@ -7300,7 +7303,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
}
@@ -7311,24 +7314,24 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Get flag ADC end of calibration.
* @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
}
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @brief Clear flag ADC ready.
* @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
@@ -7343,7 +7346,7 @@
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Clear flag ADC channel configuration ready.
* @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY
@@ -7401,7 +7404,7 @@
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -7471,7 +7474,7 @@
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Clear flag ADC end of calibration.
* @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL
@@ -7503,7 +7506,7 @@
SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Enable interruption ADC channel configuration ready.
* @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY
@@ -7561,7 +7564,7 @@
SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -7631,7 +7634,7 @@
SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Enable interruption ADC end of calibration.
* @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL
@@ -7655,7 +7658,7 @@
CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Disable interruption ADC channel configuration ready.
* @rmtoll IER ADRDYIE LL_ADC_DisableIT_CCRDY
@@ -7713,7 +7716,7 @@
CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -7783,7 +7786,7 @@
CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Disable interruption ADC end of calibration.
* @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL
@@ -7803,19 +7806,19 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Get state of interruption ADC channel configuration ready.
* @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_CCRDY
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
}
@@ -7829,7 +7832,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
}
@@ -7841,7 +7844,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
}
@@ -7853,7 +7856,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
}
@@ -7865,12 +7868,12 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -7880,7 +7883,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
}
@@ -7892,7 +7895,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
}
@@ -7904,7 +7907,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
}
@@ -7917,7 +7920,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
}
@@ -7929,7 +7932,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
}
@@ -7941,12 +7944,12 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
}
-#if defined(ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/**
* @brief Get state of interruption ADC end of calibration
* (0: interrupt disabled, 1: interrupt enabled).
@@ -7954,7 +7957,7 @@
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx)
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
}
@@ -7971,7 +7974,7 @@
/* Initialization of some features of ADC common parameters and multimode */
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
/* De-initialization of ADC instance, ADC group regular and ADC group injected */
@@ -7979,18 +7982,18 @@
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
/* Initialization of some features of ADC instance */
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *ADC_InitStruct);
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
/* Initialization of some features of ADC instance and ADC group regular */
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* Initialization of some features of ADC instance and ADC group injected */
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
#endif /* ADC_SUPPORT_2_5_MSPS */
diff --git a/Inc/stm32wbxx_ll_comp.h b/Inc/stm32wbxx_ll_comp.h
index a6e532a..f15795e 100644
--- a/Inc/stm32wbxx_ll_comp.h
+++ b/Inc/stm32wbxx_ll_comp.h
@@ -329,7 +329,7 @@
* @arg @ref LL_COMP_WINDOWMODE_DISABLE
* @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
*/
-__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)
+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef *COMPxy_COMMON)
{
return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WINMODE));
}
@@ -367,7 +367,7 @@
* @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED
* @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER
*/
-__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_PWRMODE));
}
@@ -461,7 +461,7 @@
*
* (*) Parameter not available on all devices.
*/
-__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
}
@@ -524,7 +524,7 @@
* @arg @ref LL_COMP_INPUT_MINUS_IO4
* @arg @ref LL_COMP_INPUT_MINUS_IO5
*/
-__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMESEL | COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
}
@@ -555,7 +555,7 @@
* @arg @ref LL_COMP_HYSTERESIS_MEDIUM
* @arg @ref LL_COMP_HYSTERESIS_HIGH
*/
-__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
}
@@ -590,7 +590,7 @@
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
*/
-__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
}
@@ -633,7 +633,7 @@
* (1) Parameter availability depending on timer availability
* on the selected device.
*/
-__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
}
@@ -678,7 +678,7 @@
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
}
@@ -705,7 +705,7 @@
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
-__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
}
@@ -730,7 +730,7 @@
* @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
* @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
*/
-__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
>> LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS);
@@ -746,7 +746,7 @@
*/
ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct);
void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
/**
diff --git a/Inc/stm32wbxx_ll_exti.h b/Inc/stm32wbxx_ll_exti.h
index f42d557..9bb9d70 100644
--- a/Inc/stm32wbxx_ll_exti.h
+++ b/Inc/stm32wbxx_ll_exti.h
@@ -108,26 +108,26 @@
#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx) || defined(STM32WB1Mxx)
#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || ... */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */
#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */
#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx) || defined(STM32WB1Mxx)
#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || ... */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */
#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */
#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx) || defined (STM32WB15xx) || defined(STM32WB1Mxx)
#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || ... */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB35xx)
#define LL_EXTI_LINE_ALL_0_31 (LL_EXTI_LINE_0 | LL_EXTI_LINE_1 | LL_EXTI_LINE_2 | \
@@ -159,7 +159,7 @@
LL_EXTI_LINE_15 | LL_EXTI_LINE_16 | LL_EXTI_LINE_17 | \
LL_EXTI_LINE_18 | LL_EXTI_LINE_19 | LL_EXTI_LINE_22 | \
LL_EXTI_LINE_24 | LL_EXTI_LINE_29 | LL_EXTI_LINE_30) /*!< All Extended line not reserved*/
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx */
#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
@@ -171,12 +171,12 @@
#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
#define LL_EXTI_LINE_43 EXTI_IMR2_IM43 /*!< Extended line 43 */
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx */
#define LL_EXTI_LINE_44 EXTI_IMR2_IM44 /*!< Extended line 44 */
#define LL_EXTI_LINE_45 EXTI_IMR2_IM45 /*!< Extended line 45 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx) || defined (STM32WB50xx) || defined (STM32WB35xx) || defined (STM32WB30xx)
#define LL_EXTI_LINE_46 EXTI_IMR2_IM46 /*!< Extended line 46 */
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || ... */
#define LL_EXTI_LINE_48 EXTI_IMR2_IM48 /*!< Extended line 48 */
#if defined (STM32WB55xx) || defined (STM32WB5Mxx)
@@ -195,7 +195,7 @@
LL_EXTI_LINE_38 | LL_EXTI_LINE_39 | LL_EXTI_LINE_40 | \
LL_EXTI_LINE_41 | LL_EXTI_LINE_42 | LL_EXTI_LINE_44 | \
LL_EXTI_LINE_45 | LL_EXTI_LINE_48) /*!< All Extended line not reserved*/
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx */
#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
@@ -275,8 +275,8 @@
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
+ * @{
+ */
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
* @{
*/
diff --git a/Inc/stm32wbxx_ll_lptim.h b/Inc/stm32wbxx_ll_lptim.h
index 9467889..75cccc5 100644
--- a/Inc/stm32wbxx_ll_lptim.h
+++ b/Inc/stm32wbxx_ll_lptim.h
@@ -344,6 +344,19 @@
* @{
*/
+/** Legacy definitions for compatibility purpose
+@cond 0
+ */
+#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM
+#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1
+#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2
+#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O
+#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O
+#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM
+/**
+@endcond
+ */
+
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
* @{
@@ -1064,13 +1077,14 @@
* @{
*/
+
/**
* @brief Clear the compare match flag (CMPMCF)
- * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
+ * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
-__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
}
@@ -1088,11 +1102,11 @@
/**
* @brief Clear the autoreload match flag (ARRMCF)
- * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
+ * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
-__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
}
diff --git a/Inc/stm32wbxx_ll_rcc.h b/Inc/stm32wbxx_ll_rcc.h
index c86857d..feb73d8 100644
--- a/Inc/stm32wbxx_ll_rcc.h
+++ b/Inc/stm32wbxx_ll_rcc.h
@@ -113,7 +113,11 @@
#endif /* HSI_VALUE */
#if !defined (LSE_VALUE)
+#if defined(STM32WB5Mxx)
+#define LSE_VALUE 32774U /*!< Value of the LSE oscillator in Hz */
+#else
#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
+#endif /* STM32WB5Mxx */
#endif /* LSE_VALUE */
#if !defined (LSI_VALUE)
diff --git a/Inc/stm32wbxx_ll_rtc.h b/Inc/stm32wbxx_ll_rtc.h
index e542b9b..0a59502 100644
--- a/Inc/stm32wbxx_ll_rtc.h
+++ b/Inc/stm32wbxx_ll_rtc.h
@@ -235,13 +235,13 @@
#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF
#if defined(RTC_TAMPER3_SUPPORT)
#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
#if defined(RTC_TAMPER2_SUPPORT)
#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F
-#endif
+#endif /* RTC_TAMPER2_SUPPORT */
#if defined(RTC_TAMPER1_SUPPORT)
#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F
-#endif
+#endif /* RTC_TAMPER1_SUPPORT */
#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF
#define LL_RTC_ISR_TSF RTC_ISR_TSF
#define LL_RTC_ISR_WUTF RTC_ISR_WUTF
@@ -268,13 +268,13 @@
#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
#if defined(RTC_TAMPER3_SUPPORT)
#define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
#if defined(RTC_TAMPER2_SUPPORT)
#define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE
-#endif
+#endif /* RTC_TAMPER2_SUPPORT */
#if defined(RTC_TAMPER1_SUPPORT)
#define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE
-#endif
+#endif /* RTC_TAMPER1_SUPPORT */
#define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE
/**
* @}
@@ -342,7 +342,7 @@
/**
* @}
*/
-#endif
+#endif /* RTC_OR_ALARMOUTTYPE */
/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
* @{
@@ -365,8 +365,8 @@
/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND
* @{
*/
-#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
-#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
+#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
+#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
/**
* @}
*/
@@ -418,8 +418,8 @@
/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
* @{
*/
-#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
-#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
+#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp event */
/**
* @}
*/
@@ -440,9 +440,7 @@
#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */
#endif /* RTC_TAMPER1_SUPPORT */
#if defined(RTC_TAMPER2_SUPPORT)
-#if defined(RTC_TAMPER2_SUPPORT)
#define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */
-#endif
#endif /* RTC_TAMPER2_SUPPORT */
#if defined(RTC_TAMPER3_SUPPORT)
#define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */
@@ -487,7 +485,7 @@
/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
* @{
*/
-#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
@@ -500,7 +498,7 @@
/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
* @{
*/
-#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */
#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */
#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */
@@ -513,7 +511,7 @@
/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
* @{
*/
-#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
@@ -861,7 +859,7 @@
{
return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));
}
-#endif
+#endif /* RTC_OR_ALARMOUTTYPE */
/**
* @brief Enable initialization mode
@@ -1250,8 +1248,8 @@
{
uint32_t temp;
- temp = Format12_24 | \
- (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
+ temp = Format12_24 | \
+ (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
(((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
@@ -1590,7 +1588,7 @@
{
uint32_t temp;
- temp = (WeekDay << RTC_DR_WDU_Pos) | \
+ temp = (WeekDay << RTC_DR_WDU_Pos) | \
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
(((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
(((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
@@ -1931,8 +1929,8 @@
{
uint32_t temp;
- temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
- (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
(((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST
@@ -2311,8 +2309,8 @@
{
uint32_t temp;
- temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
- (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
+ temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
+ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
(((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST
diff --git a/Inc/stm32wbxx_ll_system.h b/Inc/stm32wbxx_ll_system.h
index 168e4f2..1a7afcb 100644
--- a/Inc/stm32wbxx_ll_system.h
+++ b/Inc/stm32wbxx_ll_system.h
@@ -59,8 +59,8 @@
* @{
*/
/**
- * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
- */
+ * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values
+ */
#define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x1FFF75F0UL)) /*!< Address of VREFBUF trimming value for VRS=0,
VREF_SC0 in STM32WB datasheet */
#define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x1FFF7530UL)) /*!< Address of VREFBUF trimming value for VRS=1,
@@ -78,14 +78,14 @@
*/
/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
-* @{
-*/
+ * @{
+ */
#define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
#if defined(QUADSPI)
#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
-#endif
+#endif /* QUADSPI */
/**
* @}
*/
@@ -100,7 +100,7 @@
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(I2C3)
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
-#endif
+#endif /* I2C3 */
/**
* @}
*/
@@ -144,15 +144,16 @@
/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
* @{
*/
-#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
- with Break Input of TIM1/16/17 */
-#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
- with TIM1/16/17 Break Input
- and also the PVDE and PLS bits of the Power Control Interface */
-#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
- with Break Input of TIM1/16/17 */
-#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
- with Break Input of TIM1/16/17 */
+#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
+ with Break Input of TIM1/16/17 */
+#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
+ with TIM1/16/17 Break Input
+ and also the PVDE
+ and PLS bits of the Power Control Interface */
+#define LL_SYSCFG_TIMBREAK_SRAM2_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM2_PARITY error signal
+ with Break Input of TIM1/16/17 */
+#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
+ with Break Input of TIM1/16/17 */
/**
* @}
*/
@@ -226,7 +227,7 @@
#define LL_SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2B Write protection page 61 */
#define LL_SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2B Write protection page 62 */
#define LL_SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2B Write protection page 63 */
-#endif
+#endif /* SYSCFG_SWPR2_PAGE36 */
/**
* @}
*/
@@ -237,10 +238,10 @@
#define LL_SYSCFG_GRP1_TIM1 SYSCFG_IMR1_TIM1IM /*!< Enabling of interrupt from Timer 1 to CPU1 */
#if defined(TIM16)
#define LL_SYSCFG_GRP1_TIM16 SYSCFG_IMR1_TIM16IM /*!< Enabling of interrupt from Timer 16 to CPU1 */
-#endif
+#endif /* TIM16 */
#if defined(TIM17)
#define LL_SYSCFG_GRP1_TIM17 SYSCFG_IMR1_TIM17IM /*!< Enabling of interrupt from Timer 17 to CPU1 */
-#endif
+#endif /* TIM17 */
#define LL_SYSCFG_GRP1_EXTI5 SYSCFG_IMR1_EXTI5IM /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1 */
#define LL_SYSCFG_GRP1_EXTI6 SYSCFG_IMR1_EXTI6IM /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1 */
@@ -256,7 +257,7 @@
#if defined(SYSCFG_IMR2_PVM1IM)
#define LL_SYSCFG_GRP2_PVM1 SYSCFG_IMR2_PVM1IM /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU1 */
-#endif
+#endif /* SYSCFG_IMR2_PVM1IM */
#define LL_SYSCFG_GRP2_PVM3 SYSCFG_IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */
#define LL_SYSCFG_GRP2_PVD SYSCFG_IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU1 */
/**
@@ -267,7 +268,7 @@
* @{
*/
#define LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers
- and LSE Clock Security System to CPU2 */
+ and LSE Clock Security System to CPU2 */
#define LL_C2_SYSCFG_GRP1_RTCWKUP SYSCFG_C2IMR1_RTCWKUPIM /*!< Enabling of interrupt from RTC Wakeup to CPU2 */
#define LL_C2_SYSCFG_GRP1_RTCALARM SYSCFG_C2IMR1_RTCALARMIM /*!< Enabling of interrupt from RTC Alarms to CPU2 */
#define LL_C2_SYSCFG_GRP1_RCC SYSCFG_C2IMR1_RCCIM /*!< Enabling of interrupt from RCC to CPU2 */
@@ -276,10 +277,10 @@
#define LL_C2_SYSCFG_GRP1_RNG SYSCFG_C2IMR1_RNGIM /*!< Enabling of interrupt from Random Number Generator to CPU2 */
#if defined(AES1)
#define LL_C2_SYSCFG_GRP1_AES1 SYSCFG_C2IMR1_AES1IM /*!< Enabling of interrupt from Advanced Encryption Standard 1 to CPU2 */
-#endif
+#endif /* AES1 */
#if defined(COMP1)
#define LL_C2_SYSCFG_GRP1_COMP SYSCFG_C2IMR1_COMPIM /*!< Enabling of interrupt from Comparator to CPU2 */
-#endif
+#endif /* COMP1 */
#define LL_C2_SYSCFG_GRP1_ADC SYSCFG_C2IMR1_ADCIM /*!< Enabling of interrupt from Analog Digital Converter to CPU2 */
#define LL_C2_SYSCFG_GRP1_EXTI0 SYSCFG_C2IMR1_EXTI0IM /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2 */
@@ -315,18 +316,18 @@
#define LL_C2_SYSCFG_GRP2_DMA2CH5 SYSCFG_C2IMR2_DMA2CH5IM /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2 */
#define LL_C2_SYSCFG_GRP2_DMA2CH6 SYSCFG_C2IMR2_DMA2CH6IM /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2 */
#define LL_C2_SYSCFG_GRP2_DMA2CH7 SYSCFG_C2IMR2_DMA2CH7IM /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2 */
-#endif
+#endif /* DMA2 */
#define LL_C2_SYSCFG_GRP2_DMAMUX1 SYSCFG_C2IMR2_DMAMUX1IM /*!< Enabling of interrupt from DMAMUX1 to CPU2 */
#if defined(SYSCFG_C2IMR2_PVM1IM)
#define LL_C2_SYSCFG_GRP2_PVM1 SYSCFG_C2IMR2_PVM1IM /*!< Enabling of interrupt from Power Voltage Monitoring 1 to CPU2 */
-#endif
+#endif /* SYSCFG_C2IMR2_PVM1IM */
#define LL_C2_SYSCFG_GRP2_PVM3 SYSCFG_C2IMR2_PVM3IM /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */
#define LL_C2_SYSCFG_GRP2_PVD SYSCFG_C2IMR2_PVDIM /*!< Enabling of interrupt from Power Voltage Detector to CPU2 */
#define LL_C2_SYSCFG_GRP2_TSC SYSCFG_C2IMR2_TSCIM /*!< Enabling of interrupt from Touch Sensing Controller to CPU2 */
#if defined(LCD)
#define LL_C2_SYSCFG_GRP2_LCD SYSCFG_C2IMR2_LCDIM /*!< Enabling of interrupt from Liquid Crystal Display to CPU2 */
-#endif
+#endif /* LCD */
/**
* @}
*/
@@ -336,7 +337,7 @@
*/
#if defined(AES1)
#define LL_SYSCFG_SECURE_ACCESS_AES1 SYSCFG_SIPCR_SAES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */
-#endif
+#endif /* AES1 */
#define LL_SYSCFG_SECURE_ACCESS_AES2 SYSCFG_SIPCR_SAES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */
#define LL_SYSCFG_SECURE_ACCESS_PKA SYSCFG_SIPCR_SPKA /*!< Enabling the security access of Public Key Accelerator */
#define LL_SYSCFG_SECURE_ACCESS_RNG SYSCFG_SIPCR_SRNG /*!< Enabling the security access of Random Number Generator */
@@ -354,7 +355,7 @@
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */
#if defined(I2C3)
#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */
-#endif
+#endif /* I2C3 */
#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */
/**
* @}
@@ -369,7 +370,7 @@
#define LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_C2APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen */
#if defined(I2C3)
#define LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_C2APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen */
-#endif
+#endif /* I2C3 */
#define LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted */
/**
* @}
@@ -386,7 +387,7 @@
/** @defgroup SYSTEM_LL_EC_C2_APB1_GRP2_STOP_IP DBGMCU CPU2 APB1 GRP2 STOP IP
* @{
*/
-#define LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */
+#define LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted */
/**
* @}
*/
@@ -397,10 +398,10 @@
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */
#if defined(TIM16)
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */
-#endif
+#endif /* TIM16 */
#if defined(TIM17)
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */
-#endif
+#endif /* TIM17 */
/**
* @}
*/
@@ -408,13 +409,13 @@
/** @defgroup SYSTEM_LL_EC_C2_APB2_GRP1_STOP_IP DBGMCU CPU2 APB2 GRP1 STOP IP
* @{
*/
-#define LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */
+#define LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_C2APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted */
#if defined(TIM16)
-#define LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */
-#endif
+#define LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_C2APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted */
+#endif /* TIM16 */
#if defined(TIM17)
-#define LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */
-#endif
+#define LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_C2APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted */
+#endif /* TIM17 */
/**
* @}
*/
@@ -548,7 +549,7 @@
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD);
}
-#endif
+#endif /* SYSCFG_CFGR1_ANASWVDD */
/**
* @brief Enable the I2C fast mode plus driving capability.
@@ -766,6 +767,7 @@
return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)) ? 1UL : 0UL);
}
+
/**
* @brief Configure source input for the EXTI external interrupt.
* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
@@ -837,7 +839,7 @@
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
{
- return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x0000000FUL) );
+ return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x0000000FUL));
}
/**
@@ -1940,7 +1942,7 @@
* @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
* @note Each VrefBuf voltage scale is calibrated in production for each device,
* data stored in flash memory.
- * Functions @ref LL_VREFBUF_SC0_GetCalibration and
+ * Functions @ref LL_VREFBUF_SC0_GetCalibration and
* @ref LL_VREFBUF_SC0_GetCalibration can be used to retrieve
* these calibration data.
* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
@@ -2244,7 +2246,7 @@
*/
__STATIC_INLINE uint32_t LL_FLASH_GetSTCompanyID(void)
{
- return (uint32_t)(((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U ) & 0x00FFFFFFU);
+ return (uint32_t)(((READ_REG(*((uint32_t *)UID64_BASE + 1U))) >> 8U) & 0x00FFFFFFU);
}
/**
* @}
diff --git a/Inc/stm32wbxx_ll_tim.h b/Inc/stm32wbxx_ll_tim.h
index 024c863..1a4ff44 100644
--- a/Inc/stm32wbxx_ll_tim.h
+++ b/Inc/stm32wbxx_ll_tim.h
@@ -1219,9 +1219,9 @@
/** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap
* @{
*/
-#define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR_RMP_MASK /* !< No internal trigger on TIM2_ITR1 */
+#define LL_TIM_TIM2_ITR1_RMP_NONE TIM2_OR_RMP_MASK /*!< No internal trigger on TIM2_ITR1 */
#if defined(USB)
-#define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR_ITR1_RMP) /* !< TIM2_ITR1 is connected to USB SOF */
+#define LL_TIM_TIM2_ITR1_RMP_USB_SOF (TIM2_OR_ITR1_RMP) /*!< TIM2_ITR1 is connected to USB SOF */
#endif /* USB */
/**
* @}
@@ -1327,10 +1327,6 @@
* @}
*/
-/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
- * @{
- */
-
/**
* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
diff --git a/Inc/stm32wbxx_ll_usb.h b/Inc/stm32wbxx_ll_usb.h
index 673db74..34afb78 100644
--- a/Inc/stm32wbxx_ll_usb.h
+++ b/Inc/stm32wbxx_ll_usb.h
@@ -42,15 +42,14 @@
* @brief USB Mode definition
*/
-
-
typedef enum
{
- USB_DEVICE_MODE = 0
+ USB_DEVICE_MODE = 0
} USB_ModeTypeDef;
+
/**
- * @brief USB Initialization Structure definition
+ * @brief USB Instance Initialization Structure definition
*/
typedef struct
{
@@ -69,71 +68,63 @@
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
- uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
+ uint32_t low_power_enable; /*!< Enable or disable the low Power Mode. */
- uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
+ uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
-
- uint32_t dma_enable; /*!< dma_enable state unused, DMA not supported by FS instance */
} USB_CfgTypeDef;
typedef struct
{
- uint8_t num; /*!< Endpoint number
- This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
+ uint8_t num; /*!< Endpoint number
+ This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
- uint8_t is_in; /*!< Endpoint direction
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_in; /*!< Endpoint direction
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t is_stall; /*!< Endpoint stall condition
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t is_stall; /*!< Endpoint stall condition
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint8_t type; /*!< Endpoint type
- This parameter can be any value of @ref USB_EP_Type */
+ uint8_t type; /*!< Endpoint type
+ This parameter can be any value of @ref USB_LL_EP_Type */
- uint8_t data_pid_start; /*!< Initial data PID
- This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
+ uint8_t data_pid_start; /*!< Initial data PID
+ This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
- uint16_t pmaadress; /*!< PMA Address
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t pmaaddr0; /*!< PMA Address0
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+ uint16_t pmaadress; /*!< PMA Address
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t pmaaddr1; /*!< PMA Address1
- This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
+ uint16_t pmaaddr0; /*!< PMA Address0
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint8_t doublebuffer; /*!< Double buffer enable
- This parameter can be 0 or 1 */
+ uint16_t pmaaddr1; /*!< PMA Address1
+ This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
- uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
- only by USB OTG FS peripheral
- This parameter is added to ensure compatibility across USB peripherals */
+ uint8_t doublebuffer; /*!< Double buffer enable
+ This parameter can be 0 or 1 */
- uint32_t maxpacket; /*!< Endpoint Max packet size
- This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
+ uint32_t maxpacket; /*!< Endpoint Max packet size
+ This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
- uint32_t xfer_len; /*!< Current transfer length */
+ uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
- uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
+ uint32_t xfer_len; /*!< Current transfer length */
- uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
+ uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
- uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
+ uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
+ uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
} USB_EPTypeDef;
-
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
-
-
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
@@ -165,18 +156,21 @@
* @}
*/
+
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 1U
-#define EP_ADDR_MSK 0x7U
-
#ifndef USB_EP_RX_STRX
#define USB_EP_RX_STRX (0x3U << 12)
#endif /* USB_EP_RX_STRX */
+#define EP_ADDR_MSK 0x7U
+
#ifndef USE_USB_DOUBLE_BUFFER
#define USE_USB_DOUBLE_BUFFER 1U
#endif /* USE_USB_DOUBLE_BUFFER */
+
+
/**
* @}
*/
diff --git a/Release_Notes.html b/Release_Notes.html
index acc8dff..2680d83 100644
--- a/Release_Notes.html
+++ b/Release_Notes.html
@@ -40,16 +40,97 @@
<div class="col-sm-12 col-lg-8">
<h1 id="update-history">Update History</h1>
<div class="collapse">
-<input type="checkbox" id="collapse-section13" checked aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.11.0 / 01-June-2022</label>
+<input type="checkbox" id="collapse-section14" checked aria-hidden="true"> <label for="collapse-section14" aria-hidden="true">V1.12.0 / 09-November-2022</label>
<div>
<h2 id="main-changes">Main Changes</h2>
<ul>
<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
-<li>Correct English spelling errors and typos</li>
+<li>Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (IRDA, LPTIM, SMARTCARD, TIM, UART, USART)</li>
</ul>
<h2 id="contents">Contents</h2>
<h3 id="hal-drivers-updates"><strong>HAL Drivers</strong> updates</h3>
<ul>
+<li><strong>HAL ADC</strong> driver
+<ul>
+<li>Disable AutoPowerOff when performing calibration</li>
+<li>Fix calibration issue due to delay between ADC enable and disable</li>
+<li>Add Bitfield CFGR1_CHSELRMOD cleaning in HAL_ADC_Init and HAL_ADC_DeInit functions, needed for specific cases with reconfiguration on the fly</li>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers</li>
+</ul></li>
+<li><strong>HAL CRC</strong> driver
+<ul>
+<li>Add filter in HAL_CRCEx_Polynomial_Set() function to exclude even polynomials</li>
+</ul></li>
+<li><strong>HAL EXTI</strong> driver
+<ul>
+<li>Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine()</li>
+</ul></li>
+<li><strong>HAL RCC</strong> driver
+<ul>
+<li>Optimize HAL_RCC_GetOscConfig function</li>
+</ul></li>
+<li><strong>HAL RTC</strong> driver
+<ul>
+<li>Improve HAL_RTC_Init function to avoid initialization if already done</li>
+<li>HAL code quality enhancement</li>
+</ul></li>
+<li><strong>HAL SAI</strong> driver
+<ul>
+<li>HAL code quality enhancement</li>
+</ul></li>
+<li><strong>HAL UART</strong> driver
+<ul>
+<li>New API HAL_UARTEx_GetRxEventType to retrieve the type of event that has led the RxEventCallback execution</li>
+<li>Remove HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs to fix a concurrent access issue</li>
+<li>Disable the Receiver Timeout Interrupt when data reception is completed</li>
+</ul></li>
+<li><strong>HAL USART</strong> driver
+<ul>
+<li>Remove HAL_LOCK/HAL_UNLOCK calls in HAL_USART_RegisterCallback & HAL_USART_UnregisterCallback</li>
+</ul></li>
+<li><strong>HAL USB</strong> driver
+<ul>
+<li>Add a mask for USB RX bytes count</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<ul>
+<li><strong>LL ADC</strong> driver
+<ul>
+<li>HAL code quality enhancement for MISRA-C Rule-8.13 by adding const qualifiers</li>
+</ul></li>
+<li><strong>LL LPTIM</strong> driver
+<ul>
+<li>Enhance code quality by renaming all functions LL_LPTIM_ClearFLAG_Xxxxx with LL_LPTIM_ClearFlag_Xxxxx</li>
+</ul></li>
+<li><strong>LL RCC</strong> driver
+<ul>
+<li>Add specific LSE_VALUE to 32774Hz for STM32WB5Mxx device</li>
+</ul></li>
+<li><strong>LL TIM</strong> driver
+<ul>
+<li>Remove useless check on IS_TIM_ADVANCED_INSTANCE() within LL_TIM_BDTR_Init() to fix Break Filter configuration problem with specific TIM instances</li>
+</ul></li>
+</ul>
+<p><br />
+</p>
+<h2 id="backward-compatibility">Backward Compatibility</h2>
+<p>This release is compatible with the previous versions.</p>
+</div>
+</div>
+<div class="collapse">
+<input type="checkbox" id="collapse-section13" aria-hidden="true"> <label for="collapse-section13" aria-hidden="true">V1.11.0 / 01-June-2022</label>
+<div>
+<h2 id="main-changes-1">Main Changes</h2>
+<ul>
+<li>Maintenance release of HAL and Low Layer drivers to include latest corrections</li>
+<li>Correct English spelling errors and typos</li>
+</ul>
+<h2 id="contents-1">Contents</h2>
+<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<ul>
<li><strong>HAL EXTI</strong> driver
<ul>
<li>Fix build error with -Werror=unused-paramerter</li>
@@ -124,7 +205,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updatess"><strong>LL Drivers</strong> updatess</h3>
+<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL I2C</strong> driver
<ul>
@@ -160,19 +241,19 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility">Backward Compatibility</h2>
+<h2 id="backward-compatibility-1">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section12" aria-hidden="true"> <label for="collapse-section12" aria-hidden="true">V1.10.1 / 27-March-2022</label>
<div>
-<h2 id="main-changes-1">Main Changes</h2>
+<h2 id="main-changes-2">Main Changes</h2>
<ul>
<li>Patch release of <strong>HAL and Low Layer</strong> drivers</li>
</ul>
-<h2 id="contents-1">Contents</h2>
-<h3 id="hal-drivers-updates-1"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-2">Contents</h2>
+<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL COMP</strong> driver
<ul>
@@ -181,7 +262,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL COMP</strong> driver
<ul>
@@ -190,21 +271,21 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-1">Backward Compatibility</h2>
+<h2 id="backward-compatibility-2">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section11" aria-hidden="true"> <label for="collapse-section11" aria-hidden="true">V1.10.0 / 12-November-2021</label>
<div>
-<h2 id="main-changes-2">Main Changes</h2>
+<h2 id="main-changes-3">Main Changes</h2>
<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
<li>All source files: update disclaimer to add reference to the new license agreement</li>
<li>Correct English spelling errors and typos</li>
</ul>
-<h2 id="contents-2">Contents</h2>
-<h3 id="hal-drivers-updates-2"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-3">Contents</h2>
+<h3 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL ADC</strong> driver
<ul>
@@ -275,7 +356,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-1"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-3"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL ADC</strong> driver
<ul>
@@ -290,14 +371,14 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-2">Backward Compatibility</h2>
+<h2 id="backward-compatibility-3">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section10" aria-hidden="true"> <label for="collapse-section10" aria-hidden="true">V1.9.0 / 24-June-2021</label>
<div>
-<h2 id="main-changes-3">Main Changes</h2>
+<h2 id="main-changes-4">Main Changes</h2>
<ul>
<li>Maintenance release of <strong>HAL and Low Layer</strong> drivers to include latest corrections</li>
<li>Update of HAL SMBUS driver to introduce fast mode and fast mode plus
@@ -311,8 +392,8 @@
</ul>
<p><br />
</p>
-<h2 id="contents-3">Contents</h2>
-<h3 id="hal-drivers-updates-3"><strong>HAL Drivers</strong> updates</h3>
+<h2 id="contents-4">Contents</h2>
+<h3 id="hal-drivers-updates-4"><strong>HAL Drivers</strong> updates</h3>
<ul>
<li><strong>HAL CORTEX</strong> driver
<ul>
@@ -388,7 +469,7 @@
</ul>
<p><br />
</p>
-<h3 id="ll-drivers-updates-2"><strong>LL Drivers</strong> updates</h3>
+<h3 id="ll-drivers-updates-4"><strong>LL Drivers</strong> updates</h3>
<ul>
<li><strong>LL DMA</strong> driver
<ul>
@@ -415,14 +496,14 @@
</ul>
<p><br />
</p>
-<h2 id="backward-compatibility-3">Backward Compatibility</h2>
+<h2 id="backward-compatibility-4">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section9" aria-hidden="true"> <label for="collapse-section9" aria-hidden="true">v1.8.0 / 12-February-2021</label>
<div>
-<h2 id="main-changes-4">Main Changes</h2>
+<h2 id="main-changes-5">Main Changes</h2>
<h3 id="add-support-for-stm32wb15xx-and-stm32wb10xx">Add support for STM32WB15xx and STM32WB10xx</h3>
<table>
<thead>
@@ -558,14 +639,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-4">Backward Compatibility</h2>
+<h2 id="backward-compatibility-5">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true">v1.7.0 / 30-October-2020</label>
<div>
-<h2 id="main-changes-5">Main Changes</h2>
+<h2 id="main-changes-6">Main Changes</h2>
<h3 id="maitenance-release">Maitenance release</h3>
<p>All peripheral</p>
<table>
@@ -638,14 +719,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-5">Backward Compatibility</h2>
+<h2 id="backward-compatibility-6">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true">v1.6.0 / 05-June-2020</label>
<div>
-<h2 id="main-changes-6">Main Changes</h2>
+<h2 id="main-changes-7">Main Changes</h2>
<h3 id="maitenance-release-1">Maitenance release</h3>
<p>All peripheral</p>
<table>
@@ -750,14 +831,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-6">Backward Compatibility</h2>
+<h2 id="backward-compatibility-7">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true">v1.5.0 / 12-February-2020</label>
<div>
-<h2 id="main-changes-7">Main Changes</h2>
+<h2 id="main-changes-8">Main Changes</h2>
<h3 id="introduction-of-stm32wb5m-stm32wb35xx-and-stm32wb30xx-product">Introduction of STM32WB5M, STM32WB35xx and STM32WB30xx product</h3>
<p>This release introduce the support of STM32WB5Mxx, STM32WB35xx product and its value line STM32WB30xx.</p>
<p>Added features:</p>
@@ -802,14 +883,14 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-7">Backward Compatibility</h2>
+<h2 id="backward-compatibility-8">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
</div>
</div>
<div class="collapse">
<input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true">v1.4.0 / 15-December-2019</label>
<div>
-<h2 id="main-changes-8">Main Changes</h2>
+<h2 id="main-changes-9">Main Changes</h2>
<h3 id="maitenance-release-2">Maitenance release</h3>
<table>
<thead>
@@ -853,7 +934,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-8">Backward Compatibility</h2>
+<h2 id="backward-compatibility-9">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -863,7 +944,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.3.0 / 11-September-2019</label>
<div>
-<h2 id="main-changes-9">Main Changes</h2>
+<h2 id="main-changes-10">Main Changes</h2>
<h3 id="maitenance-release-3">Maitenance release</h3>
<table>
<thead>
@@ -935,7 +1016,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-9">Backward Compatibility</h2>
+<h2 id="backward-compatibility-10">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-1">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -945,7 +1026,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
<div>
-<h2 id="main-changes-10">Main Changes</h2>
+<h2 id="main-changes-11">Main Changes</h2>
<h3 id="stm32wb50xx-introduction-and-maintenance-release">STM32WB50xx introduction and maintenance release</h3>
<p>First release for STM32WBxx HAL drivers introducing <strong>stm32wb50xx</strong> devices.</p>
<table>
@@ -1014,7 +1095,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-10">Backward Compatibility</h2>
+<h2 id="backward-compatibility-11">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-2">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1024,7 +1105,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
<div>
-<h2 id="main-changes-11">Main Changes</h2>
+<h2 id="main-changes-12">Main Changes</h2>
<h3 id="maintenance-release">Maintenance release</h3>
<p>Maintenance release of HAL and Low layers drivers supporting STM32WB55xx devices.</p>
<table>
@@ -1078,7 +1159,7 @@
</tr>
</tbody>
</table>
-<h2 id="backward-compatibility-11">Backward Compatibility</h2>
+<h2 id="backward-compatibility-12">Backward Compatibility</h2>
<p>This release is compatible with the previous versions.</p>
<h2 id="dependencies-3">Dependencies</h2>
<p>This software release is compatible with:</p>
@@ -1088,7 +1169,7 @@
<div class="collapse">
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
<div>
-<h2 id="main-changes-12">Main Changes</h2>
+<h2 id="main-changes-13">Main Changes</h2>
<h3 id="first-release">First release</h3>
<p>First official release of HAL (Hardware Abstraction Layer) and LL (Low layers) drivers to support STM32WB55xx.</p>
</div>
diff --git a/Src/stm32wbxx_hal.c b/Src/stm32wbxx_hal.c
index 8de2970..c321a66 100644
--- a/Src/stm32wbxx_hal.c
+++ b/Src/stm32wbxx_hal.c
@@ -52,20 +52,20 @@
* @{
*/
/**
- * @brief STM32WBxx HAL Driver version number
+ * @brief STM32WBxx HAL Driver version number
*/
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
-#define __STM32WBxx_HAL_VERSION_SUB1 (0x0BU) /*!< [23:16] sub1 version */
+#define __STM32WBxx_HAL_VERSION_SUB1 (0x0CU) /*!< [23:16] sub1 version */
#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
- |(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\
- |(__STM32WBxx_HAL_VERSION_SUB2 << 8U )\
- |(__STM32WBxx_HAL_VERSION_RC))
+ |(__STM32WBxx_HAL_VERSION_SUB1 << 16U)\
+ |(__STM32WBxx_HAL_VERSION_SUB2 << 8U )\
+ |(__STM32WBxx_HAL_VERSION_RC))
#if defined(VREFBUF)
#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
-#endif
+#endif /* VREFBUF */
/**
* @}
@@ -91,8 +91,8 @@
*/
/** @addtogroup HAL_Exported_Functions_Group1
- * @brief HAL Initialization and Configuration functions
- *
+ * @brief HAL Initialization and Configuration functions
+ *
@verbatim
===============================================================================
##### HAL Initialization and Configuration functions #####
@@ -148,11 +148,11 @@
/* - Instruction cache enabled */
/* - Data cache enabled */
#if (INSTRUCTION_CACHE_ENABLE == 0U)
- __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE == 0U)
- __HAL_FLASH_DATA_CACHE_DISABLE();
+ __HAL_FLASH_DATA_CACHE_DISABLE();
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
@@ -161,7 +161,7 @@
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
+
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
@@ -193,7 +193,7 @@
__HAL_RCC_APB3_FORCE_RESET();
__HAL_RCC_APB3_RELEASE_RESET();
-
+
__HAL_RCC_AHB1_FORCE_RESET();
__HAL_RCC_AHB1_RELEASE_RESET();
@@ -215,7 +215,7 @@
* @retval None
*/
__weak void HAL_MspInit(void)
-{
+{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
@@ -226,7 +226,7 @@
* @retval None
*/
__weak void HAL_MspDeInit(void)
-{
+{
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
@@ -255,7 +255,7 @@
if ((uint32_t)uwTickFreq != 0U)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
- if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/ (1000U / (uint32_t)uwTickFreq)) == 0U)
+ if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000U / (uint32_t)uwTickFreq)) == 0U)
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
@@ -269,7 +269,7 @@
}
}
else
- {
+ {
status = HAL_ERROR;
}
}
@@ -287,8 +287,8 @@
*/
/** @addtogroup HAL_Exported_Functions_Group2
- * @brief HAL Control functions
- *
+ * @brief HAL Control functions
+ *
@verbatim
===============================================================================
##### HAL Control functions #####
@@ -312,7 +312,7 @@
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other
+ * @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
@@ -383,8 +383,8 @@
}
/**
- * @brief This function provides minimum delay (in milliseconds) based
- * on variable incremented.
+ * @brief This function provides minimum delay (in milliseconds) based
+ * on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
@@ -393,22 +393,22 @@
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
- __weak void HAL_Delay(uint32_t Delay)
+__weak void HAL_Delay(uint32_t Delay)
+{
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
{
- uint32_t tickstart = HAL_GetTick();
- uint32_t wait = Delay;
-
- /* Add a freq to guarantee minimum wait */
- if (wait < HAL_MAX_DELAY)
- {
- wait += (uint32_t)(uwTickFreq);
- }
-
- while ((HAL_GetTick() - tickstart) < wait)
- {
- }
+ wait += (uint32_t)(uwTickFreq);
}
+ while ((HAL_GetTick() - tickstart) < wait)
+ {
+ }
+}
+
/**
* @brief Suspend Tick increment.
@@ -423,7 +423,7 @@
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
- CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
+ CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
@@ -439,7 +439,7 @@
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
- SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
+ SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
@@ -448,7 +448,7 @@
*/
uint32_t HAL_GetHalVersion(void)
{
- return __STM32WBxx_HAL_VERSION;
+ return __STM32WBxx_HAL_VERSION;
}
/**
@@ -457,7 +457,7 @@
*/
uint32_t HAL_GetREVID(void)
{
- return(LL_DBGMCU_GetRevisionID());
+ return (LL_DBGMCU_GetRevisionID());
}
/**
@@ -466,7 +466,7 @@
*/
uint32_t HAL_GetDEVID(void)
{
- return(LL_DBGMCU_GetDeviceID());
+ return (LL_DBGMCU_GetDeviceID());
}
/**
@@ -475,7 +475,7 @@
*/
uint32_t HAL_GetUIDw0(void)
{
- return(READ_REG(*((uint32_t *)UID_BASE)));
+ return (READ_REG(*((uint32_t *)UID_BASE)));
}
/**
@@ -484,7 +484,7 @@
*/
uint32_t HAL_GetUIDw1(void)
{
- return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+ return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
}
/**
@@ -493,7 +493,7 @@
*/
uint32_t HAL_GetUIDw2(void)
{
- return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+ return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
}
/**
@@ -501,8 +501,8 @@
*/
/** @addtogroup HAL_Exported_Functions_Group3
- * @brief HAL Debug functions
- *
+ * @brief HAL Debug functions
+ *
@verbatim
===============================================================================
##### HAL Debug functions #####
@@ -575,8 +575,8 @@
*/
/** @defgroup HAL_Exported_Functions_Group4 HAL System Configuration functions
- * @brief HAL System Configuration functions
- *
+ * @brief HAL System Configuration functions
+ *
@verbatim
===============================================================================
##### HAL system configuration functions #####
@@ -633,9 +633,9 @@
* @brief Configure the internal voltage reference buffer voltage scale.
* @param VoltageScaling specifies the output voltage to achieve
* This parameter can be one of the following values:
- * @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE0 : VREF_OUT1 around 2.048 V.
+ * @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE0 : VREF_OUT1 around 2.048 V.
* This requires VDDA equal to or higher than 2.4 V.
- * @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE1 : VREF_OUT1 around 2.5 V.
+ * @arg @ref SYSCFG_VREFBUF_VOLTAGE_SCALE1 : VREF_OUT1 around 2.5 V.
* This requires VDDA equal to or higher than 2.8 V.
* @note Retrieve the TrimmingValue from factory located at
* VREFBUF_SC0_CAL_ADDR or VREFBUF_SC1_CAL_ADDR addresses.
@@ -647,17 +647,17 @@
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
-
+
LL_VREFBUF_SetVoltageScaling(VoltageScaling);
-
+
/* Restrieve Calibration data and store them into trimming field */
if (VoltageScaling == SYSCFG_VREFBUF_VOLTAGE_SCALE0)
{
- TrimmingValue = ((uint32_t) *VREFBUF_SC0_CAL_ADDR) & 0x3FU;
+ TrimmingValue = ((uint32_t) * VREFBUF_SC0_CAL_ADDR) & 0x3FU;
}
else
{
- TrimmingValue = ((uint32_t) *VREFBUF_SC1_CAL_ADDR) & 0x3FU;
+ TrimmingValue = ((uint32_t) * VREFBUF_SC1_CAL_ADDR) & 0x3FU;
}
assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
@@ -685,7 +685,7 @@
* @brief Tune the Internal Voltage Reference buffer (VREFBUF).
* @note Each VrefBuf voltage scale is calibrated in production for each device,
* data stored in flash memory.
- * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and
+ * Function @ref HAL_SYSCFG_VREFBUF_VoltageScalingConfig retrieves and
* applies this calibration data as trimming value at each scale change.
* Therefore, optionally, function @ref HAL_SYSCFG_VREFBUF_TrimmingConfig
* can be used in a second time to fine tune the trimming.
@@ -697,7 +697,7 @@
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
-
+
LL_VREFBUF_SetTrimming(TrimmingValue);
}
@@ -709,16 +709,16 @@
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
{
uint32_t tickstart;
-
+
LL_VREFBUF_Enable();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait for VRR bit */
- while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)
+ while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0U)
{
- if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
diff --git a/Src/stm32wbxx_hal_adc.c b/Src/stm32wbxx_hal_adc.c
index 4910e34..ca3ed33 100644
--- a/Src/stm32wbxx_hal_adc.c
+++ b/Src/stm32wbxx_hal_adc.c
@@ -340,10 +340,10 @@
/* Unit: cycles of CPU clock. */
#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Register CHSELR bits corresponding to ranks 2 to 8 . */
#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
@@ -401,12 +401,12 @@
uint32_t tmpCFGR = 0UL;
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index = 0UL;
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
uint32_t tmpCFGR2 = 0UL;
#else
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Check ADC handle */
if (hadc == NULL)
@@ -427,7 +427,7 @@
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
@@ -471,10 +471,10 @@
hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
@@ -499,7 +499,7 @@
}
/* - Exit from deep power-down mode and ADC voltage regulator enable */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "deep power-down" not available on ADC peripheral of this STM32WB device */
#else
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
@@ -511,7 +511,7 @@
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
{
@@ -557,7 +557,7 @@
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
@@ -630,7 +630,7 @@
hadc->Init.DataAlign |
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) );
-
+
/* Update setting of discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
{
@@ -666,17 +666,18 @@
/* Update ADC configuration register with previous settings */
MODIFY_REG(hadc->Instance->CFGR1,
- ADC_CFGR1_DISCEN |
- ADC_CFGR1_AUTOFF |
- ADC_CFGR1_WAIT |
- ADC_CFGR1_CONT |
- ADC_CFGR1_OVRMOD |
- ADC_CFGR1_EXTSEL |
- ADC_CFGR1_EXTEN |
- ADC_CFGR1_ALIGN |
- ADC_CFGR1_SCANDIR |
- ADC_CFGR1_DMACFG ,
- tmpCFGR );
+ ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF |
+ ADC_CFGR1_CHSELRMOD |
+ ADC_CFGR1_WAIT |
+ ADC_CFGR1_CONT |
+ ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTSEL |
+ ADC_CFGR1_EXTEN |
+ ADC_CFGR1_ALIGN |
+ ADC_CFGR1_SCANDIR |
+ ADC_CFGR1_DMACFG,
+ tmpCFGR);
/* Channel sampling time configuration */
LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
@@ -716,7 +717,7 @@
(hadc->ADCGroupRegularSequencerRanks))
);
}
-
+
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core peripheral clocking. */
/* Check through register CFGR1 (excluding analog watchdog configuration: */
@@ -727,7 +728,7 @@
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
-
+
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_BUSY_INTERNAL,
@@ -739,10 +740,10 @@
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
-
+
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
-
+
tmp_hal_status = HAL_ERROR;
}
@@ -933,13 +934,13 @@
SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
/* Stop potential conversion on going */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
#else
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* Disable ADC peripheral if conversions are effectively stopped */
@@ -972,34 +973,35 @@
/* system RCC hard reset. */
/* ========== Reset ADC registers ========== */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Reset register IER */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 |
ADC_IT_AWD1 | ADC_IT_OVR |
ADC_IT_EOS | ADC_IT_EOC |
ADC_IT_EOSMP | ADC_IT_RDY ) );
-
+
/* Reset register ISR */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 |
ADC_FLAG_AWD1 | ADC_FLAG_OVR |
ADC_FLAG_EOS | ADC_FLAG_EOC |
ADC_FLAG_EOSMP | ADC_FLAG_RDY ) );
-
+
/* Reset register CR */
/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
/* "read-set": no direct reset applicable. */
/* Reset register CFGR1 */
- hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
- ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
- ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
- ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN );
+ hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
+ ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |
+ ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES |
+ ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN |
+ ADC_CFGR1_CHSELRMOD);
/* Reset register CFGR2 */
/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
/* already done above. */
hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
-
+
/* Reset register SMPR */
hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
@@ -1015,25 +1017,25 @@
#else
/* Reset register IER */
__HAL_ADC_DISABLE_IT(hadc, (
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
ADC_IT_EOCAL | ADC_IT_CCRDY |
#else
ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
ADC_IT_JEOS | ADC_IT_JEOC | ADC_IT_JQOVF |
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
ADC_IT_EOS | ADC_IT_EOC | ADC_IT_OVR |
ADC_IT_EOSMP | ADC_IT_RDY));
/* Reset register ISR */
__HAL_ADC_CLEAR_FLAG(hadc, (
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
ADC_FLAG_EOCAL | ADC_FLAG_CCRDY |
#else
ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
ADC_FLAG_JEOS | ADC_FLAG_JEOC | ADC_FLAG_JQOVF |
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
ADC_FLAG_EOS | ADC_FLAG_EOC | ADC_FLAG_OVR |
ADC_FLAG_EOSMP | ADC_FLAG_RDY));
@@ -1159,7 +1161,7 @@
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Reset HAL ADC handle variable */
hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
#else
@@ -1382,7 +1384,7 @@
hadc->ErrorCallback = HAL_ADC_ErrorCallback;
break;
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
@@ -1392,7 +1394,7 @@
case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
break;
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
@@ -1517,7 +1519,7 @@
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
#else
@@ -1584,7 +1586,7 @@
/* Process locked */
__HAL_LOCK(hadc);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* 1. Stop potential conversion on going, on ADC group regular */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
#else
@@ -1602,7 +1604,7 @@
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_READY);
@@ -1661,11 +1663,11 @@
/* several ranks and polling for end of each conversion. */
/* For code simplicity sake, this particular case is generalized to */
/* ADC configured in DMA mode and and polling for end of each conversion. */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if(READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN) != 0UL)
#else
if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
@@ -1736,11 +1738,11 @@
/* Clear end of conversion EOC flag of regular group if low power feature */
/* "LowPowerAutoWait " is disabled, to not interfere with this feature */
/* until data register is read using function HAL_ADC_GetValue(). */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if (READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_WAIT) == 0UL)
#else
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_AUTDLY) == 0UL)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
@@ -1857,7 +1859,7 @@
break;
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* Injected context queue overflow event */
@@ -1872,7 +1874,7 @@
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
break;
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Overrun event */
default: /* Case ADC_OVR_EVENT */
@@ -1947,7 +1949,7 @@
HAL_ADC_STATE_REG_BUSY);
/* Set ADC error code */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
#else
@@ -2037,7 +2039,7 @@
/* Process locked */
__HAL_LOCK(hadc);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* 1. Stop potential conversion on going, on ADC group regular */
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
#else
@@ -2059,7 +2061,7 @@
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_READY);
@@ -2114,7 +2116,7 @@
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
HAL_ADC_STATE_REG_BUSY);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
#else
@@ -2160,11 +2162,11 @@
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
/* Enable ADC DMA mode */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
SET_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
#else
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Start the DMA channel */
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
@@ -2212,7 +2214,7 @@
__HAL_LOCK(hadc);
/* 1. Stop potential ADC group regular conversion on going */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
#else
tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
@@ -2222,11 +2224,11 @@
if (tmp_hal_status == HAL_OK)
{
/* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
#else
CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Disable the DMA channel (in case of DMA in circular mode or stop */
/* while DMA transfer is on going) */
@@ -2261,7 +2263,7 @@
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_READY);
@@ -2300,7 +2302,7 @@
* @param hadc ADC handle
* @retval ADC group regular conversion data
*/
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
+uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -2322,11 +2324,11 @@
uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
uint32_t tmp_isr = hadc->Instance->ISR;
uint32_t tmp_ier = hadc->Instance->IER;
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
uint32_t tmp_adc_inj_is_trigger_source_sw_start;
uint32_t tmp_adc_reg_is_trigger_source_sw_start;
uint32_t tmp_cfgr;
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -2370,11 +2372,11 @@
if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
{
/* Carry on if continuous mode is disabled */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if (READ_BIT (hadc->Instance->CFGR1, ADC_CFGR1_CONT) != ADC_CFGR1_CONT)
#else
if (READ_BIT (hadc->Instance->CFGR, ADC_CFGR_CONT) != ADC_CFGR_CONT)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
/* If End of Sequence is reached, disable interrupts */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
@@ -2428,7 +2430,7 @@
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
@@ -2611,7 +2613,7 @@
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/* ========== Check Injected context queue overflow flag ========== */
@@ -2740,9 +2742,9 @@
* @param sConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
@@ -2922,10 +2924,10 @@
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0;
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -2967,7 +2969,7 @@
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
#else
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
@@ -3138,15 +3140,15 @@
* @param AnalogWDGConfig Structure of ADC analog watchdog configuration
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpAWDHighThresholdShifted;
uint32_t tmpAWDLowThresholdShifted;
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -3154,19 +3156,19 @@
assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
#else
if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
(AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
}
/* Verify thresholds range */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Verify if thresholds are within the selected ADC resolution */
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
@@ -3195,7 +3197,7 @@
/* conversion on going on ADC groups regular and injected: */
/* - Analog watchdog channels */
/* - Analog watchdog thresholds */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
#else
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
@@ -3218,7 +3220,7 @@
LL_ADC_GROUP_REGULAR));
break;
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
@@ -3236,7 +3238,7 @@
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
break;
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
case ADC_ANALOGWATCHDOG_ALL_INJEC:
@@ -3281,7 +3283,7 @@
LL_ADC_DisableIT_AWD1(hadc->Instance);
}
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC analog watchdog 2 and 3" not available on ADC peripheral of this STM32WB device */
#else
/* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
@@ -3290,10 +3292,10 @@
switch (AnalogWDGConfig->WatchdogMode)
{
case ADC_ANALOGWATCHDOG_SINGLE_REG:
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
/* Update AWD by bitfield to keep the possibility to monitor */
/* several channels by successive calls of this function. */
if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
@@ -3307,15 +3309,15 @@
break;
case ADC_ANALOGWATCHDOG_ALL_REG:
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
case ADC_ANALOGWATCHDOG_ALL_INJEC:
case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
-#endif
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#endif /* !ADC_SUPPORT_2_5_MSPS */
+#if defined(ADC_SUPPORT_2_5_MSPS)
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
#else
LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
break;
default: /* ADC_ANALOGWATCHDOG_NONE */
@@ -3426,7 +3428,7 @@
* @param hadc ADC handle
* @retval ADC handle state (bitfield on 32 bits)
*/
-uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
+uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -3440,7 +3442,7 @@
* @param hadc ADC handle
* @retval ADC error code (bitfield on 32 bits)
*/
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
+uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
{
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
@@ -3474,7 +3476,7 @@
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
UNUSED(ConversionGroup);
uint32_t tickstart;
@@ -3659,11 +3661,11 @@
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
{
/* Check if conditions to enable the ADC are fulfilled */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
#else
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -3691,7 +3693,7 @@
}
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* If low power mode AutoPowerOff is enabled, power-on/off phases are */
/* performed automatically by hardware and flag ADC ready is not set. */
if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
@@ -3753,11 +3755,11 @@
)
{
/* Check if conditions to disable the ADC are fulfilled */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
#else
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
@@ -3821,7 +3823,7 @@
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
/* Is it the end of the regular sequence ? */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if( (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
&& (hadc->Init.ContinuousConvMode == DISABLE)
)
diff --git a/Src/stm32wbxx_hal_adc_ex.c b/Src/stm32wbxx_hal_adc_ex.c
index 60a7d2e..1c313ef 100644
--- a/Src/stm32wbxx_hal_adc_ex.c
+++ b/Src/stm32wbxx_hal_adc_ex.c
@@ -71,6 +71,7 @@
/* Calibration time max = 116 / fADC (refer to datasheet) */
/* = 158 379 CPU cycles */
#define ADC_CALIBRATION_TIMEOUT (158379UL) /*!< ADC calibration time-out value (unit: CPU cycles) */
+#define ADC_DISABLE_TIMEOUT (2UL)
/**
* @}
@@ -124,11 +125,15 @@
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
UNUSED(SingleDiff);
uint32_t calibration_index;
uint32_t calibration_factor_accumulated = 0;
+ uint32_t backup_setting_cfgr1;
+ uint32_t tickstart;
+ uint32_t adc_clk_async_presc;
+ __IO uint32_t delay_cpu_cycles;
#endif /* ADC_SUPPORT_2_5_MSPS */
HAL_StatusTypeDef tmp_hal_status;
@@ -150,7 +155,7 @@
if (tmp_hal_status == HAL_OK)
{
/* Set ADC state */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
@@ -161,7 +166,18 @@
#endif /* ADC_SUPPORT_2_5_MSPS */
/* Start ADC calibration in mode single-ended or differential */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
+ /* Manage settings impacting calibration */
+ /* - Disable ADC mode auto power-off */
+ /* - Disable ADC DMA transfer request during calibration */
+ /* Note: Specificity of this STM32 series: Calibration factor is */
+ /* available in data register and also transferred by DMA. */
+ /* To not insert ADC calibration factor among ADC conversion data */
+ /* in array variable, DMA transfer must be disabled during */
+ /* calibration. */
+ backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
+ CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
+
/* ADC calibration procedure */
/* Note: Perform an averaging of 8 calibrations for optimized accuracy */
for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++)
@@ -190,15 +206,61 @@
return HAL_ERROR;
}
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance);
}
/* Compute average */
calibration_factor_accumulated /= calibration_index;
- /* Apply calibration factor */
+ /* Apply calibration factor (requires ADC enable and disable process) */
LL_ADC_Enable(hadc->Instance);
+
+ /* Case of ADC clocked at low frequency: Delay required between ADC enable and disable actions */
+ if(LL_ADC_GetClock(hadc->Instance) == LL_ADC_CLOCK_ASYNC)
+ {
+ adc_clk_async_presc = LL_ADC_GetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+ if(adc_clk_async_presc >= LL_ADC_CLOCK_ASYNC_DIV16)
+ {
+ /* Delay loop initialization and execution */
+ /* Delay depends on ADC clock prescaler: Compute ADC clock asynchronous prescaler to decimal format */
+ delay_cpu_cycles = (1U << ((adc_clk_async_presc >> ADC_CCR_PRESC_Pos) - 3U));
+ /* Divide variable by 2 to compensate partially CPU processing cycles */
+ delay_cpu_cycles >>= 1U;
+
+ while(delay_cpu_cycles != 0)
+ {
+ delay_cpu_cycles--;
+ }
+ }
+ }
+
LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated);
LL_ADC_Disable(hadc->Instance);
+
+ /* Wait for ADC effectively disabled before changing configuration */
+ /* Get tick count */
+ tickstart = HAL_GetTick();
+
+ while (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ {
+ if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+ {
+ /* New check to avoid false timeout detection in case of preemption */
+ if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+ {
+ /* Update ADC state machine to error */
+ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+ /* Set ADC error code to ADC peripheral internal error */
+ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+ return HAL_ERROR;
+ }
+ }
+ }
+
+ /* Restore configuration after calibration */
+ SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1);
#endif /* ADC_SUPPORT_2_5_MSPS */
/* Set ADC state */
@@ -231,22 +293,22 @@
* (1) On STM32WB series, parameter not available on devices: STM32WB10xx, STM32WB15xx, STM32WB1Mxx.
* @retval Calibration value.
*/
-uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
UNUSED(SingleDiff);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Return the selected ADC calibration value */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
return LL_ADC_GetCalibrationFactor(hadc->Instance);
#else
return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
/**
@@ -263,13 +325,13 @@
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
{
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
UNUSED(SingleDiff);
-#endif
-
+#endif /* ADC_SUPPORT_2_5_MSPS */
+
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_adc_is_conversion_on_going_regular;
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
uint32_t tmp_adc_is_conversion_on_going_injected;
@@ -286,7 +348,7 @@
/* Verification of hardware constraints before modifying the calibration */
/* factors register: ADC must be enabled, no conversion on going. */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
@@ -294,7 +356,7 @@
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
@@ -302,11 +364,11 @@
)
{
/* Set the selected ADC calibration value */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
LL_ADC_SetCalibrationFactor(hadc->Instance, CalibrationFactor);
#else
LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
else
{
@@ -326,7 +388,7 @@
return tmp_hal_status;
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -780,7 +842,7 @@
}
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -811,7 +873,7 @@
* @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
* @retval ADC group injected conversion data
*/
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
{
uint32_t tmp_jdr;
@@ -922,7 +984,7 @@
*/
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -1125,7 +1187,7 @@
* @}
*/
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
@@ -1179,7 +1241,7 @@
* injected group.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected)
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, const ADC_InjectionConfTypeDef *sConfigInjected)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpOffsetShifted;
@@ -1593,7 +1655,7 @@
}
#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -1705,7 +1767,7 @@
return tmp_hal_status;
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature " ADC deep power-down" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -1744,7 +1806,7 @@
return tmp_hal_status;
}
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
diff --git a/Src/stm32wbxx_hal_comp.c b/Src/stm32wbxx_hal_comp.c
index 2a2e823..d344a07 100644
--- a/Src/stm32wbxx_hal_comp.c
+++ b/Src/stm32wbxx_hal_comp.c
@@ -908,7 +908,7 @@
* @arg COMP_OUTPUT_LEVEL_HIGH
*
*/
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
+uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp)
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
@@ -956,7 +956,7 @@
* @param hcomp COMP handle
* @retval HAL state
*/
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
+HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp)
{
/* Check the COMP handle allocation */
if(hcomp == NULL)
@@ -976,7 +976,7 @@
* @param hcomp COMP handle
* @retval COMP error code
*/
-uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
+uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp)
{
/* Check the parameters */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
diff --git a/Src/stm32wbxx_hal_crc_ex.c b/Src/stm32wbxx_hal_crc_ex.c
index 9835203..25a4c13 100644
--- a/Src/stm32wbxx_hal_crc_ex.c
+++ b/Src/stm32wbxx_hal_crc_ex.c
@@ -94,44 +94,53 @@
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
- /* check polynomial definition vs polynomial size:
- * polynomial length must be aligned with polynomial
- * definition. HAL_ERROR is reported if Pol degree is
- * larger than that indicated by PolyLength.
- * Look for MSB position: msb will contain the degree of
- * the second to the largest polynomial member. E.g., for
- * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
- while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ /* Ensure that the generating polynomial is odd */
+ if ((Pol & (uint32_t)(0x1U)) == 0U)
{
+ status = HAL_ERROR;
}
-
- switch (PolyLength)
+ else
{
- case CRC_POLYLENGTH_7B:
- if (msb >= HAL_CRC_LENGTH_7B)
- {
- status = HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_8B:
- if (msb >= HAL_CRC_LENGTH_8B)
- {
- status = HAL_ERROR;
- }
- break;
- case CRC_POLYLENGTH_16B:
- if (msb >= HAL_CRC_LENGTH_16B)
- {
- status = HAL_ERROR;
- }
- break;
+ /* check polynomial definition vs polynomial size:
+ * polynomial length must be aligned with polynomial
+ * definition. HAL_ERROR is reported if Pol degree is
+ * larger than that indicated by PolyLength.
+ * Look for MSB position: msb will contain the degree of
+ * the second to the largest polynomial member. E.g., for
+ * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
+ while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U))
+ {
+ }
- case CRC_POLYLENGTH_32B:
- /* no polynomial definition vs. polynomial length issue possible */
- break;
- default:
- status = HAL_ERROR;
- break;
+ switch (PolyLength)
+ {
+
+ case CRC_POLYLENGTH_7B:
+ if (msb >= HAL_CRC_LENGTH_7B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_8B:
+ if (msb >= HAL_CRC_LENGTH_8B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+ case CRC_POLYLENGTH_16B:
+ if (msb >= HAL_CRC_LENGTH_16B)
+ {
+ status = HAL_ERROR;
+ }
+ break;
+
+ case CRC_POLYLENGTH_32B:
+ /* no polynomial definition vs. polynomial length issue possible */
+ break;
+ default:
+ status = HAL_ERROR;
+ break;
+ }
}
if (status == HAL_OK)
{
diff --git a/Src/stm32wbxx_hal_exti.c b/Src/stm32wbxx_hal_exti.c
index 24bc66a..ec29590 100644
--- a/Src/stm32wbxx_hal_exti.c
+++ b/Src/stm32wbxx_hal_exti.c
@@ -105,8 +105,8 @@
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
-#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
-#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
+#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
+#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
/**
* @}
*/
@@ -121,8 +121,8 @@
*/
/** @addtogroup EXTI_Exported_Functions_Group1
- * @brief Configuration functions
- *
+ * @brief Configuration functions
+ *
@verbatim
===============================================================================
##### Configuration functions #####
@@ -235,7 +235,7 @@
/* The event mode cannot be configured if the line does not support it */
assert_param(((pExtiConfig->Line & EXTI_EVENT) == EXTI_EVENT) || ((pExtiConfig->Mode & EXTI_MODE_EVENT) != EXTI_MODE_EVENT));
-
+
/* Configure event mode : read current mode */
regaddr = (&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
@@ -280,7 +280,7 @@
/* Check the parameter */
assert_param(IS_EXTI_LINE(hexti->Line));
- /* Store handle line number to configiguration structure */
+ /* Store handle line number to configuration structure */
pExtiConfig->Line = hexti->Line;
/* compute line register offset and line mask */
@@ -344,7 +344,7 @@
assert_param(IS_EXTI_GPIO_PIN(linepos));
regval = SYSCFG->EXTICR[linepos >> 2u];
- pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
+ pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0;
}
}
@@ -423,7 +423,8 @@
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
+ void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
@@ -474,8 +475,8 @@
*/
/** @addtogroup EXTI_Exported_Functions_Group2
- * @brief EXTI IO functions.
- *
+ * @brief EXTI IO functions.
+ *
@verbatim
===============================================================================
##### IO operation functions #####
diff --git a/Src/stm32wbxx_hal_irda.c b/Src/stm32wbxx_hal_irda.c
index bcce365..a638cdf 100644
--- a/Src/stm32wbxx_hal_irda.c
+++ b/Src/stm32wbxx_hal_irda.c
@@ -463,6 +463,8 @@
/**
* @brief Register a User IRDA Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+ * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -491,8 +493,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hirda);
if (hirda->gState == HAL_IRDA_STATE_READY)
{
@@ -577,15 +577,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hirda);
-
return status;
}
/**
* @brief Unregister an IRDA callback
* IRDA callback is redirected to the weak predefined callback
+ * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET
+ * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID
* @param hirda irda handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -605,9 +604,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hirda);
-
if (HAL_IRDA_STATE_READY == hirda->gState)
{
switch (CallbackID)
@@ -693,9 +689,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hirda);
-
return status;
}
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
diff --git a/Src/stm32wbxx_hal_lptim.c b/Src/stm32wbxx_hal_lptim.c
index ddb1821..2372f9f 100644
--- a/Src/stm32wbxx_hal_lptim.c
+++ b/Src/stm32wbxx_hal_lptim.c
@@ -2108,9 +2108,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hlptim);
-
if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
@@ -2181,9 +2178,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hlptim);
-
return status;
}
@@ -2209,9 +2203,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hlptim);
-
if (hlptim->State == HAL_LPTIM_STATE_READY)
{
switch (CallbackID)
@@ -2293,9 +2284,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hlptim);
-
return status;
}
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
diff --git a/Src/stm32wbxx_hal_msp_template.c b/Src/stm32wbxx_hal_msp_template.c
index 0634897..2728028 100644
--- a/Src/stm32wbxx_hal_msp_template.c
+++ b/Src/stm32wbxx_hal_msp_template.c
@@ -4,7 +4,7 @@
* @author MCD Application Team
* @brief This file contains the HAL System and Peripheral (PPP) MSP initialization
* and de-initialization functions.
- * It should be copied to the application folder and renamed into 'stm32wbxx_hal_msp.c'.
+ * It should be copied to the application folder and renamed into 'stm32wbxx_hal_msp.c'.
******************************************************************************
* @attention
*
@@ -16,7 +16,7 @@
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_hal.h"
@@ -65,7 +65,7 @@
/**
* @brief Initializes the PPP MSP.
- * @note This functiona is called from HAL_PPP_Init() function to perform
+ * @note This functiona is called from HAL_PPP_Init() function to perform
* peripheral(PPP) system level initialization (GPIOs, clock, DMA, interrupt)
* @retval None
*/
@@ -76,7 +76,7 @@
/**
* @brief DeInitializes the PPP MSP.
- * @note This functiona is called from HAL_PPP_DeInit() function to perform
+ * @note This functiona is called from HAL_PPP_DeInit() function to perform
* peripheral(PPP) system level de-initialization (GPIOs, clock, DMA, interrupt)
* @retval None
*/
diff --git a/Src/stm32wbxx_hal_pcd.c b/Src/stm32wbxx_hal_pcd.c
index f822688..8eba857 100644
--- a/Src/stm32wbxx_hal_pcd.c
+++ b/Src/stm32wbxx_hal_pcd.c
@@ -37,7 +37,7 @@
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
(##) Enable the PCD/USB Low Level interface clock using
- (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device only FS peripheral
+ (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
@@ -169,9 +169,6 @@
hpcd->State = HAL_PCD_STATE_BUSY;
- /* DMA Not supported for FS instance, Force to Zero */
- hpcd->Init.dma_enable = 0U;
-
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@@ -181,7 +178,6 @@
/* Init ep structure */
hpcd->IN_ep[i].is_in = 1U;
hpcd->IN_ep[i].num = i;
- hpcd->IN_ep[i].tx_fifo_num = i;
/* Control until ep is activated */
hpcd->IN_ep[i].type = EP_TYPE_CTRL;
hpcd->IN_ep[i].maxpacket = 0U;
@@ -297,7 +293,7 @@
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
- * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @param pCallback pointer to the Callback function
@@ -411,7 +407,7 @@
* @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID
* @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID
* @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID
- * @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID
+ * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID
* @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID
* @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID
* @retval HAL status
@@ -1411,11 +1407,6 @@
ep->maxpacket = ep_mps;
ep->type = ep_type;
- if (ep->is_in != 0U)
- {
- /* Assign a Tx FIFO */
- ep->tx_fifo_num = ep->num;
- }
/* Set initial data PID. */
if (ep_type == EP_TYPE_BULK)
{
@@ -1449,7 +1440,7 @@
ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];
ep->is_in = 0U;
}
- ep->num = ep_addr & EP_ADDR_MSK;
+ ep->num = ep_addr & EP_ADDR_MSK;
__HAL_LOCK(hpcd);
(void)USB_DeactivateEndpoint(hpcd->Instance, ep);
@@ -1479,14 +1470,7 @@
ep->is_in = 0U;
ep->num = ep_addr & EP_ADDR_MSK;
- if ((ep_addr & EP_ADDR_MSK) == 0U)
- {
- (void)USB_EP0StartXfer(hpcd->Instance, ep);
- }
- else
- {
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
return HAL_OK;
}
@@ -1524,14 +1508,7 @@
ep->is_in = 1U;
ep->num = ep_addr & EP_ADDR_MSK;
- if ((ep_addr & EP_ADDR_MSK) == 0U)
- {
- (void)USB_EP0StartXfer(hpcd->Instance, ep);
- }
- else
- {
- (void)USB_EPStartXfer(hpcd->Instance, ep);
- }
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
return HAL_OK;
}
@@ -1903,7 +1880,7 @@
}
else
{
- (void) USB_EPStartXfer(hpcd->Instance, ep);
+ (void)USB_EPStartXfer(hpcd->Instance, ep);
}
}
diff --git a/Src/stm32wbxx_hal_rcc.c b/Src/stm32wbxx_hal_rcc.c
index bfbd46e..382baff 100644
--- a/Src/stm32wbxx_hal_rcc.c
+++ b/Src/stm32wbxx_hal_rcc.c
@@ -1298,7 +1298,7 @@
* @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
- * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
+ * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI1 LSI1 clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI2 LSI2 clock selected as MCO source
@@ -1526,6 +1526,10 @@
*/
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
+ uint32_t regvalue;
+ uint32_t regICSRvalue;
+ uint32_t regPLLCFGRvalue;
+
/* Check the parameters */
assert_param(RCC_OscInitStruct != (void *)NULL);
@@ -1537,93 +1541,52 @@
RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
#endif /* RCC_HSI48_SUPPORT */
+ /* Get register values */
+ regvalue = RCC->CR; /* Control register */
+ regICSRvalue = RCC->ICSCR; /* Get Internal Clock Sources Calibration register */
+ regPLLCFGRvalue = RCC->PLLCFGR; /* Get PLL Configuration register */
+
/* Get the HSE configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_ON;
- }
- else
- {
- RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
- }
+ RCC_OscInitStruct->HSEState = (regvalue & RCC_CR_HSEON);
/* Get the MSI configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_MSION) == RCC_CR_MSION)
- {
- RCC_OscInitStruct->MSIState = RCC_MSI_ON;
- }
- else
- {
- RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
- }
- RCC_OscInitStruct->MSICalibrationValue = LL_RCC_MSI_GetCalibTrimming();
- RCC_OscInitStruct->MSIClockRange = LL_RCC_MSI_GetRange();
+ RCC_OscInitStruct->MSIState = (regvalue & RCC_CR_MSION);
+ RCC_OscInitStruct->MSICalibrationValue = (regICSRvalue & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos;
+ RCC_OscInitStruct->MSIClockRange = (regvalue & RCC_CR_MSIRANGE);
/* Get the HSI configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_ON;
- }
- else
- {
- RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
- }
-
- RCC_OscInitStruct->HSICalibrationValue = LL_RCC_HSI_GetCalibTrimming();
-
- /* Get the LSE configuration -----------------------------------------------*/
- if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
- }
- else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_ON;
- }
- else
- {
- RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
- }
-
- /* Get the LSI configuration -----------------------------------------------*/
- const uint32_t temp_lsi1on = (RCC->CSR & RCC_CSR_LSI1ON);
- const uint32_t temp_lsi2on = (RCC->CSR & RCC_CSR_LSI2ON);
- if ((temp_lsi1on == RCC_CSR_LSI1ON) || (temp_lsi2on == RCC_CSR_LSI2ON))
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_ON;
- }
- else
- {
- RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
- }
-
-#if defined(RCC_HSI48_SUPPORT)
- /* Get the HSI48 configuration ---------------------------------------------*/
- if ((RCC->CRRCR & RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON)
- {
- RCC_OscInitStruct->HSI48State = RCC_HSI48_ON;
- }
- else
- {
- RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF;
- }
-#endif /* RCC_HSI48_SUPPORT */
+ RCC_OscInitStruct->HSIState = (regvalue & RCC_CR_HSION);
+ RCC_OscInitStruct->HSICalibrationValue = ((regICSRvalue & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
/* Get the PLL configuration -----------------------------------------------*/
- if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
- }
- else
- {
- RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
- }
- RCC_OscInitStruct->PLL.PLLSource = LL_RCC_PLL_GetMainSource();
- RCC_OscInitStruct->PLL.PLLM = LL_RCC_PLL_GetDivider();
- RCC_OscInitStruct->PLL.PLLN = LL_RCC_PLL_GetN();
- RCC_OscInitStruct->PLL.PLLP = LL_RCC_PLL_GetP();
- RCC_OscInitStruct->PLL.PLLQ = LL_RCC_PLL_GetQ();
- RCC_OscInitStruct->PLL.PLLR = LL_RCC_PLL_GetR();
+ RCC_OscInitStruct->PLL.PLLState = ((regvalue & RCC_CR_PLLON) >> RCC_CR_PLLON_Pos) + 1U;
+ RCC_OscInitStruct->PLL.PLLSource = (regPLLCFGRvalue & RCC_PLLCFGR_PLLSRC);
+ RCC_OscInitStruct->PLL.PLLM = (regPLLCFGRvalue & RCC_PLLCFGR_PLLM);
+ RCC_OscInitStruct->PLL.PLLN = ((regPLLCFGRvalue & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ RCC_OscInitStruct->PLL.PLLP = (regPLLCFGRvalue & RCC_PLLCFGR_PLLP);
+ RCC_OscInitStruct->PLL.PLLQ = (regPLLCFGRvalue & RCC_PLLCFGR_PLLQ);
+ RCC_OscInitStruct->PLL.PLLR = (regPLLCFGRvalue & RCC_PLLCFGR_PLLR);
+
+ /* Get Backup Domain register */
+ regvalue = RCC->BDCR;
+
+ /* Get the LSE configuration -----------------------------------------------*/
+ RCC_OscInitStruct->LSEState = (regvalue & RCC_LSE_BYPASS);
+
+ /* Get Control/Status register */
+ regvalue = RCC->CSR;
+
+ /* Get the LSI configuration -----------------------------------------------*/
+ RCC_OscInitStruct->LSIState = ((regvalue & RCC_LSI_ON) > 0U)?RCC_LSI_ON:0U;
+
+#if defined(RCC_HSI48_SUPPORT)
+ /* Get Control/Status register */
+ regvalue = RCC->CRRCR;
+
+ /* Get the HSI48 configuration ---------------------------------------------*/
+ RCC_OscInitStruct->HSI48State = (regvalue & RCC_CRRCR_HSI48ON);
+#endif /* RCC_HSI48_SUPPORT */
+
}
/**
diff --git a/Src/stm32wbxx_hal_rtc.c b/Src/stm32wbxx_hal_rtc.c
index 69fcea2..4bc2faa 100644
--- a/Src/stm32wbxx_hal_rtc.c
+++ b/Src/stm32wbxx_hal_rtc.c
@@ -229,6 +229,8 @@
*/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
+ HAL_StatusTypeDef status;
+
/* Check the RTC peripheral state */
if (hrtc == NULL)
{
@@ -257,11 +259,11 @@
hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
#if defined(RTC_TAMPER1_SUPPORT)
hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
-#endif
+#endif /* RTC_TAMPER1_SUPPORT */
hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
#if defined(RTC_TAMPER3_SUPPORT)
hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
if (hrtc->MspInitCallback == NULL)
{
@@ -289,66 +291,82 @@
/* Set RTC state */
hrtc->State = HAL_RTC_STATE_BUSY;
- /* Disable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode(hrtc) != HAL_OK)
+ /* Check if the calendar has been not initialized */
+ if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U)
{
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+ /* Disable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_ERROR;
+ /* Set Initialization mode */
+ if (RTC_EnterInitMode(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
- return HAL_ERROR;
+ /* Set RTC state */
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ status = HAL_ERROR;
+ }
+ else
+ {
+ /* Clear RTC_CR FMT, OSEL and POL Bits */
+ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
+ /* Set RTC_CR register */
+ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
+
+ /* Configure the RTC PRER */
+ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
+ hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
+
+ /* Exit Initialization mode */
+ hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
+
+#if defined(RTC_OR_ALARMOUTTYPE)
+ hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
+#else
+ hrtc->Instance->OR &= (uint32_t)~(RTC_OR_OUT_RMP);
+#endif /* RTC_OR_ALARMOUTTYPE */
+ hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
+ {
+ if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hrtc);
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ /* Set RTC state */
+ status = HAL_OK;
+ }
}
else
{
- /* Clear RTC_CR FMT, OSEL and POL Bits */
- hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
- /* Set RTC_CR register */
- hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-
- /* Configure the RTC PRER */
- hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
- hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
-
- /* Exit Initialization mode */
- hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
-
-#if defined(RTC_OR_ALARMOUTTYPE)
- hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP);
-#else
- hrtc->Instance->OR &= (uint32_t)~(RTC_OR_OUT_RMP);
-#endif
- hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap);
-
- /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U)
- {
- if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
- {
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_ERROR;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hrtc);
-
- return HAL_ERROR;
- }
- }
-
- /* Enable the write protection for RTC registers */
- __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- /* Set RTC state */
- hrtc->State = HAL_RTC_STATE_READY;
-
- return HAL_OK;
+ /* Calendar is already initialized */
+ /* Set flag to OK */
+ status = HAL_OK;
}
+
+ if (status == HAL_OK)
+ {
+ /* Change RTC state */
+ hrtc->State = HAL_RTC_STATE_READY;
+ }
+
+ return status;
}
/**
@@ -525,7 +543,7 @@
case HAL_RTC_TAMPER1_EVENT_CB_ID :
hrtc->Tamper1EventCallback = pCallback;
break;
-#endif
+#endif /* RTC_TAMPER1_SUPPORT */
case HAL_RTC_TAMPER2_EVENT_CB_ID :
hrtc->Tamper2EventCallback = pCallback;
@@ -535,7 +553,7 @@
case HAL_RTC_TAMPER3_EVENT_CB_ID :
hrtc->Tamper3EventCallback = pCallback;
break;
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = pCallback;
@@ -613,15 +631,15 @@
switch (CallbackID)
{
case HAL_RTC_ALARM_A_EVENT_CB_ID :
- hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
+ hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */
break;
case HAL_RTC_ALARM_B_EVENT_CB_ID :
- hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
+ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
break;
case HAL_RTC_TIMESTAMP_EVENT_CB_ID :
- hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
+ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
break;
case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID :
@@ -630,19 +648,19 @@
#if defined(RTC_TAMPER1_SUPPORT)
case HAL_RTC_TAMPER1_EVENT_CB_ID :
- hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
+ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
break;
-#endif
+#endif /* RTC_TAMPER1_SUPPORT */
case HAL_RTC_TAMPER2_EVENT_CB_ID :
- hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
+ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
break;
#if defined(RTC_TAMPER3_SUPPORT)
case HAL_RTC_TAMPER3_EVENT_CB_ID :
- hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
+ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
break;
-#endif
+#endif /* RTC_TAMPER3_SUPPORT */
case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = HAL_RTC_MspInit;
@@ -1156,7 +1174,8 @@
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
uint32_t tickstart;
- uint32_t tmpreg, subsecondtmpreg;
+ uint32_t tmpreg;
+ uint32_t subsecondtmpreg;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -1337,7 +1356,8 @@
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
uint32_t tickstart;
- uint32_t tmpreg, subsecondtmpreg;
+ uint32_t tmpreg;
+ uint32_t subsecondtmpreg;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -1612,7 +1632,8 @@
*/
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
{
- uint32_t tmpreg, subsecondtmpreg;
+ uint32_t tmpreg;
+ uint32_t subsecondtmpreg;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -1737,7 +1758,6 @@
*/
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
-
uint32_t tickstart = HAL_GetTick();
while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U)
diff --git a/Src/stm32wbxx_hal_rtc_ex.c b/Src/stm32wbxx_hal_rtc_ex.c
index 3b9b9cd..705b657 100644
--- a/Src/stm32wbxx_hal_rtc_ex.c
+++ b/Src/stm32wbxx_hal_rtc_ex.c
@@ -121,28 +121,28 @@
* @{
*/
#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\
- (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
- (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\
+#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS | (uint32_t)RTC_TAMPCR_TAMPFREQ | \
+ (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH | \
+ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | \
(uint32_t)RTC_TAMPCR_TAMP1IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
(uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF |\
(uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
#elif defined(RTC_TAMPER1_SUPPORT)
-#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\
- (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
- (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\
+#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS | (uint32_t)RTC_TAMPCR_TAMPFREQ | \
+ (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH | \
+ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | \
(uint32_t)RTC_TAMPCR_TAMP1IE | (uint32_t)RTC_TAMPCR_TAMP1NOERASE | (uint32_t)RTC_TAMPCR_TAMP1MF |\
(uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
#elif defined(RTC_TAMPER3_SUPPORT)
-#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\
- (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
- (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\
+#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS | (uint32_t)RTC_TAMPCR_TAMPFREQ | \
+ (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH | \
+ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | \
(uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF |\
(uint32_t)RTC_TAMPCR_TAMP3IE | (uint32_t)RTC_TAMPCR_TAMP3NOERASE | (uint32_t)RTC_TAMPCR_TAMP3MF)
#else
-#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS |\
- (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\
- (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE |\
+#define RTC_TAMPCR_MASK ((uint32_t)RTC_TAMPCR_TAMPTS | (uint32_t)RTC_TAMPCR_TAMPFREQ | \
+ (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH | \
+ (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | \
(uint32_t)RTC_TAMPCR_TAMP2IE | (uint32_t)RTC_TAMPCR_TAMP2NOERASE | (uint32_t)RTC_TAMPCR_TAMP2MF)
#endif /* RTC_TAMPER1_SUPPORT && RTC_TAMPER3_SUPPORT */
/**
@@ -406,7 +406,7 @@
return HAL_OK;
}
-#endif
+#endif /* RTC_INTERNALTS_SUPPORT */
/**
* @brief Get the RTC TimeStamp value.
@@ -422,7 +422,8 @@
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
RTC_DateTypeDef *sTimeStampDate, uint32_t Format)
{
- uint32_t tmptime, tmpdate;
+ uint32_t tmptime;
+ uint32_t tmpdate;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -461,7 +462,7 @@
/* Clear the TIMESTAMP Flags */
#if defined(RTC_INTERNALTS_SUPPORT)
__HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF);
-#endif
+#endif /* RTC_INTERNALTS_SUPPORT */
__HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
@@ -546,7 +547,8 @@
/* Configure the RTC_TAMPCR register */
tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase | \
(uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | \
- (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection);
+ (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | \
+ (uint32_t)sTamper->TimeStampOnTamperDetection);
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
@@ -637,10 +639,10 @@
}
/* Configure the RTC_TAMPCR register */
- tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase | \
- (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency
- | \
- (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection);
+ tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | \
+ (uint32_t)sTamper->NoErase | (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | \
+ (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \
+ (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection);
hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_MASK);
@@ -1487,7 +1489,8 @@
}
/* Configure the Smooth calibration settings */
- hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue);
+ hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | \
+ (uint32_t)SmoothCalibMinusPulsesValue);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
diff --git a/Src/stm32wbxx_hal_sai.c b/Src/stm32wbxx_hal_sai.c
index be186eb..33b9b86 100644
--- a/Src/stm32wbxx_hal_sai.c
+++ b/Src/stm32wbxx_hal_sai.c
@@ -246,6 +246,8 @@
*/
#define SAI_DEFAULT_TIMEOUT 4U
#define SAI_LONG_TIMEOUT 1000U
+#define SAI_SPDIF_FRAME_LENGTH 64U
+#define SAI_AC97_FRAME_LENGTH 256U
/**
* @}
*/
@@ -498,12 +500,12 @@
if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
{
/* For SPDIF protocol, frame length is set by hardware to 64 */
- tmpframelength = 64U;
+ tmpframelength = SAI_SPDIF_FRAME_LENGTH;
}
else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL)
{
/* For AC97 protocol, frame length is set by hardware to 256 */
- tmpframelength = 256U;
+ tmpframelength = SAI_AC97_FRAME_LENGTH;
}
else
{
diff --git a/Src/stm32wbxx_hal_smartcard.c b/Src/stm32wbxx_hal_smartcard.c
index c46b9cf..58b5e49 100644
--- a/Src/stm32wbxx_hal_smartcard.c
+++ b/Src/stm32wbxx_hal_smartcard.c
@@ -468,6 +468,9 @@
/**
* @brief Register a User SMARTCARD Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init()
+ * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+ * and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsmartcard smartcard handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -497,8 +500,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(hsmartcard);
if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
{
@@ -584,15 +585,15 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmartcard);
-
return status;
}
/**
* @brief Unregister an SMARTCARD callback
* SMARTCARD callback is redirected to the weak predefined callback
+ * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init()
+ * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID
+ * and HAL_SMARTCARD_MSPDEINIT_CB_ID
* @param hsmartcard smartcard handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -613,9 +614,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(hsmartcard);
-
if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState)
{
switch (CallbackID)
@@ -701,9 +699,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(hsmartcard);
-
return status;
}
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
diff --git a/Src/stm32wbxx_hal_tim.c b/Src/stm32wbxx_hal_tim.c
index af22f8b..3309aa9 100644
--- a/Src/stm32wbxx_hal_tim.c
+++ b/Src/stm32wbxx_hal_tim.c
@@ -6005,8 +6005,6 @@
{
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(htim);
if (htim->State == HAL_TIM_STATE_READY)
{
@@ -6202,9 +6200,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
return status;
}
@@ -6248,9 +6243,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(htim);
-
if (htim->State == HAL_TIM_STATE_READY)
{
switch (CallbackID)
@@ -6487,9 +6479,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(htim);
-
return status;
}
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
diff --git a/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c b/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c
index dd740b4..a7db6b3 100644
--- a/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c
+++ b/Src/stm32wbxx_hal_timebase_rtc_alarm_template.c
@@ -1,13 +1,13 @@
/**
******************************************************************************
- * @file stm32wbxx_hal_timebase_rtc_alarm_template.c
+ * @file stm32wbxx_hal_timebase_rtc_alarm_template.c
* @author MCD Application Team
* @brief HAL time base based on the hardware RTC_ALARM Template.
*
* This file override the native HAL time base functions (defined as weak)
* to use the RTC ALARM for time base generation:
* + Initializes the RTC peripheral to increment the seconds registers each 1ms
- * + The alarm is configured to assert an interrupt when the RTC reaches 1ms
+ * + The alarm is configured to assert an interrupt when the RTC reaches 1ms
* + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
* + HSE (default), LSE or LSI can be selected as RTC clock source
******************************************************************************
@@ -29,13 +29,13 @@
This file must be copied to the application folder and modified as follows:
(#) Rename it to 'stm32wbxx_hal_timebase_rtc_alarm.c'
(#) Add this file and the RTC HAL drivers to your project and uncomment
- HAL_RTC_MODULE_ENABLED define in stm32wbxx_hal_conf.h
+ HAL_RTC_MODULE_ENABLED define in stm32wbxx_hal_conf.h
[..]
(@) HAL RTC alarm and HAL RTC wakeup drivers can't be used with low power modes:
The wake up capability of the RTC may be intrusive in case of prior low power mode
configuration requiring different wake up sources.
- Application/Example behavior is no more guaranteed
+ Application/Example behavior is no more guaranteed
(@) The stm32wbxx_hal_timebase_tim use is recommended for the Applications/Examples
requiring low power modes
@@ -51,12 +51,12 @@
/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
* @{
- */
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
precision.
@@ -68,12 +68,12 @@
/* #define RTC_CLOCK_SOURCE_LSI */
#ifdef RTC_CLOCK_SOURCE_HSE
- #define RTC_ASYNCH_PREDIV 99U
- #define RTC_SYNCH_PREDIV 9U
- #define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U)))
+#define RTC_ASYNCH_PREDIV 99U
+#define RTC_SYNCH_PREDIV 9U
+#define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U)))
#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */
- #define RTC_ASYNCH_PREDIV 0U
- #define RTC_SYNCH_PREDIV 31U
+#define RTC_ASYNCH_PREDIV 0U
+#define RTC_SYNCH_PREDIV 31U
#endif /* RTC_CLOCK_SOURCE_HSE */
/* Private macro -------------------------------------------------------------*/
@@ -86,15 +86,15 @@
/* Private functions ---------------------------------------------------------*/
/**
- * @brief This function configures the RTC_ALARMA as a time base source.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
+ * @brief This function configures the RTC_ALARMA as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
__IO uint32_t counter = 0U;
@@ -124,22 +124,22 @@
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
{
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
{
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
/* The time base should be 1ms
- Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
- HSE as RTC clock
+ Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
+ HSE as RTC clock
Time base = ((99 + 1) * (9 + 1)) / 1MHz
= 1ms
- LSE as RTC clock
+ LSE as RTC clock
Time base = ((31 + 1) * (0 + 1)) / 32.768KHz
= ~1ms
- LSI as RTC clock
+ LSI as RTC clock
Time base = ((31 + 1) * (0 + 1)) / 32KHz
= 1ms
*/
@@ -166,9 +166,9 @@
counter = 0U;
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == 0U)
+ while (__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == 0U)
{
- if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
+ if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */
{
return HAL_ERROR;
}
@@ -186,14 +186,14 @@
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
/* Check if the Initialization mode is set */
- if((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ if ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
/* Set the Initialization mode */
hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
counter = 0U;
- while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ while ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
- if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
+ if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */
{
return HAL_ERROR;
}
@@ -264,9 +264,9 @@
/* Set the Initialization mode */
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
- while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+ while ((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
- if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
+ if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */
{
break;
}
diff --git a/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c b/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c
index 698ee41..60ac51d 100644
--- a/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c
+++ b/Src/stm32wbxx_hal_timebase_rtc_wakeup_template.c
@@ -1,14 +1,14 @@
/**
******************************************************************************
- * @file stm32wbxx_hal_timebase_rtc_wakeup_template.c
+ * @file stm32wbxx_hal_timebase_rtc_wakeup_template.c
* @author MCD Application Team
* @brief HAL time base based on the hardware RTC_WAKEUP Template.
- *
+ *
* This file overrides the native HAL time base functions (defined as weak)
* to use the RTC WAKEUP for the time base generation:
* + Initializes the RTC peripheral and configures the wakeup timer to be
* incremented each 1ms
- * + The wakeup feature is configured to assert an interrupt each 1ms
+ * + The wakeup feature is configured to assert an interrupt each 1ms
* + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
* + HSE (default), LSE or LSI can be selected as RTC clock source
******************************************************************************
@@ -30,13 +30,13 @@
This file must be copied to the application folder and modified as follows:
(#) Rename it to 'stm32wbxx_hal_timebase_rtc_wakeup.c'
(#) Add this file and the RTC HAL drivers to your project and uncomment
- HAL_RTC_MODULE_ENABLED define in stm32wbxx_hal_conf.h
+ HAL_RTC_MODULE_ENABLED define in stm32wbxx_hal_conf.h
[..]
(@) HAL RTC alarm and HAL RTC wakeup drivers can't be used with low power modes:
The wake up capability of the RTC may be intrusive in case of prior low power mode
configuration requiring different wake up sources.
- Application/Example behavior is no more guaranteed
+ Application/Example behavior is no more guaranteed
(@) The stm32wbxx_hal_timebase_tim use is recommended for the Applications/Examples
requiring low power modes
@@ -52,12 +52,12 @@
/** @defgroup HAL_TimeBase_RTC_WakeUp_Template HAL TimeBase RTC WakeUp Template
* @{
- */
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
precision.
@@ -69,12 +69,12 @@
/* #define RTC_CLOCK_SOURCE_LSI */
#ifdef RTC_CLOCK_SOURCE_HSE
- #define RTC_ASYNCH_PREDIV 99U
- #define RTC_SYNCH_PREDIV 9U
- #define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U)))
+#define RTC_ASYNCH_PREDIV 99U
+#define RTC_SYNCH_PREDIV 9U
+#define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U)))
#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */
- #define RTC_ASYNCH_PREDIV 0U
- #define RTC_SYNCH_PREDIV 31U
+#define RTC_ASYNCH_PREDIV 0U
+#define RTC_SYNCH_PREDIV 31U
#endif /* RTC_CLOCK_SOURCE_HSE */
/* Private macro -------------------------------------------------------------*/
@@ -88,19 +88,19 @@
/* Private functions ---------------------------------------------------------*/
/**
- * @brief This function configures the RTC_WKUP as a time base source.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
- * Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
+ * @brief This function configures the RTC_WKUP as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
+ * Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
= 1ms
- * Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1)
+ * Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1)
= 1 ms
* @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
__IO uint32_t counter = 0U;
@@ -130,22 +130,22 @@
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
- {
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
+ {
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
- if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
{
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
- /* The time base should be 1ms
- Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
- HSE as RTC clock
+ /* The time base should be 1ms
+ Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
+ HSE as RTC clock
Time base = ((99 + 1) * (9 + 1)) / 1Mhz
= 1ms
- LSE as RTC clock
+ LSE as RTC clock
Time base = ((31 + 1) * (0 + 1)) / 32.768Khz
= ~1ms
- LSI as RTC clock
+ LSI as RTC clock
Time base = ((31 + 1) * (0 + 1)) / 32Khz
= 1ms
*/
@@ -167,13 +167,13 @@
/* Disable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
- /* In case of interrupt mode is used, the interrupt source must disabled */
- __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT);
+ /* In case of interrupt mode is used, the interrupt source must disabled */
+ __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
/* Wait till RTC WUTWF flag is set */
- while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == 0U)
+ while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == 0U)
{
- if(counter++ == (SystemCoreClock /48U))
+ if (counter++ == (SystemCoreClock / 48U))
{
return HAL_ERROR;
}
@@ -200,7 +200,7 @@
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* Configure the Interrupt in the RTC_CR register */
- __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
+ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
/* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
@@ -209,7 +209,7 @@
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
- HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
+ HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
return HAL_OK;
}
}
diff --git a/Src/stm32wbxx_hal_timebase_tim_template.c b/Src/stm32wbxx_hal_timebase_tim_template.c
index 99c8904..cb285fd 100644
--- a/Src/stm32wbxx_hal_timebase_tim_template.c
+++ b/Src/stm32wbxx_hal_timebase_tim_template.c
@@ -1,14 +1,14 @@
/**
******************************************************************************
- * @file stm32wbxx_hal_timebase_tim_template.c
+ * @file stm32wbxx_hal_timebase_tim_template.c
* @author MCD Application Team
* @brief HAL time base based on the hardware TIM Template.
- *
+ *
* This file overrides the native HAL time base functions (defined as weak)
* the TIM time base:
* + Initializes the TIM peripheral generate a Period elapsed Event each 1ms
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
- *
+ *
******************************************************************************
* @attention
*
@@ -31,7 +31,7 @@
/** @addtogroup HAL_TimeBase_TIM
* @{
- */
+ */
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -44,52 +44,53 @@
/* Private functions ---------------------------------------------------------*/
/**
- * @brief This function configures the TIM2 as a time base source.
- * The time source is configured to have 1ms time base with a dedicated
- * Tick interrupt priority.
+ * @brief This function configures the TIM2 as a time base source.
+ * The time source is configured to have 1ms time base with a dedicated
+ * Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
- * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
+ * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
RCC_ClkInitTypeDef clkconfig;
- uint32_t uwTimclock, uwAPB1Prescaler;
+ uint32_t uwTimclock;
+ uint32_t uwAPB1Prescaler;
uint32_t uwPrescalerValue;
uint32_t pFLatency;
-
- /*Configure the TIM2 IRQ priority */
- HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority ,0U);
-
+
+ /* Configure the TIM2 IRQ priority */
+ HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority, 0U);
+
/* Enable the TIM2 global Interrupt */
HAL_NVIC_EnableIRQ(TIM2_IRQn);
-
+
/* Enable TIM2 clock */
__HAL_RCC_TIM2_CLK_ENABLE();
-
+
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
-
+
/* Get APB1 prescaler */
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
-
+
/* Compute TIM2 clock */
- if (uwAPB1Prescaler == RCC_HCLK_DIV1)
+ if (uwAPB1Prescaler == RCC_HCLK_DIV1)
{
uwTimclock = HAL_RCC_GetPCLK1Freq();
}
else
{
- uwTimclock = 2U*HAL_RCC_GetPCLK1Freq();
+ uwTimclock = 2U * HAL_RCC_GetPCLK1Freq();
}
-
+
/* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */
- uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
-
+ uwPrescalerValue = (uint32_t)((uwTimclock / 1000000U) - 1U);
+
/* Initialize TIM2 */
TimHandle.Instance = TIM2;
-
+
/* Initialize TIMx peripheral as follow:
+ Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
@@ -100,12 +101,12 @@
TimHandle.Init.Prescaler = uwPrescalerValue;
TimHandle.Init.ClockDivision = 0U;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
- if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
+ if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&TimHandle);
}
-
+
/* Return function status */
return HAL_ERROR;
}
diff --git a/Src/stm32wbxx_hal_uart.c b/Src/stm32wbxx_hal_uart.c
index 7eb6b77..4f71c04 100644
--- a/Src/stm32wbxx_hal_uart.c
+++ b/Src/stm32wbxx_hal_uart.c
@@ -197,9 +197,6 @@
*/
/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
-
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup UART_Private_Functions
* @{
@@ -229,6 +226,16 @@
* @}
*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
+ * @{
+ */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+ * @}
+ */
+
+/* Exported Constants --------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UART_Exported_Functions UART Exported Functions
@@ -661,6 +668,7 @@
huart->gState = HAL_UART_STATE_RESET;
huart->RxState = HAL_UART_STATE_RESET;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -701,6 +709,9 @@
/**
* @brief Register a User UART Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -732,8 +743,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_READY)
{
switch (CallbackID)
@@ -823,14 +832,15 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
/**
* @brief Unregister an UART Callback
* UART callaback is redirected to the weak predefined callback
+ * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+ * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
+ * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
* @param huart uart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -853,8 +863,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- __HAL_LOCK(huart);
-
if (HAL_UART_STATE_READY == huart->gState)
{
switch (CallbackID)
@@ -946,8 +954,6 @@
status = HAL_ERROR;
}
- __HAL_UNLOCK(huart);
-
return status;
}
@@ -1083,7 +1089,8 @@
(+) HAL_UART_AbortTransmitCpltCallback()
(+) HAL_UART_AbortReceiveCpltCallback()
- (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:
+ (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+ reception services:
(+) HAL_UARTEx_RxEventCallback()
(#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
@@ -1136,8 +1143,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->gState = HAL_UART_STATE_BUSY_TX;
@@ -1159,8 +1164,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
while (huart->TxXferCount > 0U)
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
@@ -1226,8 +1229,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1254,8 +1255,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* as long as data have to be received */
while (huart->RxXferCount > 0U)
{
@@ -1307,8 +1306,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1330,8 +1327,6 @@
huart->TxISR = UART_TxISR_8BIT_FIFOEN;
}
- __HAL_UNLOCK(huart);
-
/* Enable the TX FIFO threshold interrupt */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
}
@@ -1347,8 +1342,6 @@
huart->TxISR = UART_TxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the Transmit Data Register Empty interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
}
@@ -1381,8 +1374,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1390,7 +1381,7 @@
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
- if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
@@ -1398,14 +1389,14 @@
}
#else
/* Check that USART RTOEN bit is set */
- if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
#endif
- return(UART_Start_Receive_IT(huart, pData, Size));
+ return (UART_Start_Receive_IT(huart, pData, Size));
}
else
{
@@ -1433,8 +1424,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
huart->pTxBuffPtr = pData;
huart->TxXferSize = Size;
huart->TxXferCount = Size;
@@ -1462,8 +1451,6 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->gState to ready */
huart->gState = HAL_UART_STATE_READY;
@@ -1473,8 +1460,6 @@
/* Clear the TC flag in the ICR register */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
- __HAL_UNLOCK(huart);
-
/* Enable the DMA transfer for transmit request by setting the DMAT bit
in the UART CR3 register */
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
@@ -1509,8 +1494,6 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
/* Set Reception type to Standard reception */
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
@@ -1518,7 +1501,7 @@
if (!(IS_LPUART_INSTANCE(huart->Instance)))
{
/* Check that USART RTOEN bit is set */
- if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
@@ -1526,14 +1509,14 @@
}
#else
/* Check that USART RTOEN bit is set */
- if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
{
/* Enable the UART Receiver Timeout Interrupt */
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
}
#endif
- return(UART_Start_Receive_DMA(huart, pData, Size));
+ return (UART_Start_Receive_DMA(huart, pData, Size));
}
else
{
@@ -1551,8 +1534,6 @@
const HAL_UART_StateTypeDef gstate = huart->gState;
const HAL_UART_StateTypeDef rxstate = huart->RxState;
- __HAL_LOCK(huart);
-
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
(gstate == HAL_UART_STATE_BUSY_TX))
{
@@ -1570,8 +1551,6 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
@@ -1582,8 +1561,6 @@
*/
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
{
- __HAL_LOCK(huart);
-
if (huart->gState == HAL_UART_STATE_BUSY_TX)
{
/* Enable the UART DMA Tx request */
@@ -1596,7 +1573,7 @@
/* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
if (huart->Init.Parity != UART_PARITY_NONE)
- {
+ {
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
}
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
@@ -1605,8 +1582,6 @@
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
}
- __HAL_UNLOCK(huart);
-
return HAL_OK;
}
@@ -1703,9 +1678,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1728,9 +1704,10 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -1797,9 +1774,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
@@ -1861,9 +1839,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
@@ -1962,7 +1941,7 @@
}
}
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
/* Disable DMA Tx at UART level */
@@ -1986,9 +1965,10 @@
}
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2074,9 +2054,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
- /* Disable the UART DMA Tx request if enabled */
+ /* Abort the UART DMA Tx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
{
+ /* Disable the UART DMA Tx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
/* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
@@ -2170,9 +2151,10 @@
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
}
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
@@ -2351,9 +2333,10 @@
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
UART_EndRxTransfer(huart);
- /* Disable the UART DMA Rx request if enabled */
+ /* Abort the UART DMA Rx channel if enabled */
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
{
+ /* Disable the UART DMA Rx request if enabled */
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* Abort the UART DMA Rx channel */
@@ -2415,9 +2398,9 @@
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
- if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- &&((isrflags & USART_ISR_IDLE) != 0U)
- &&((cr1its & USART_ISR_IDLE) != 0U))
+ if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ && ((isrflags & USART_ISR_IDLE) != 0U)
+ && ((cr1its & USART_ISR_IDLE) != 0U))
{
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
@@ -2429,8 +2412,8 @@
(DMA cplt callback will be called).
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
- if ( (nb_remaining_rx_data > 0U)
- &&(nb_remaining_rx_data < huart->RxXferSize))
+ if ((nb_remaining_rx_data > 0U)
+ && (nb_remaining_rx_data < huart->RxXferSize))
{
/* Reception is not complete */
huart->RxXferCount = nb_remaining_rx_data;
@@ -2455,13 +2438,18 @@
/* Last bytes received, so no need as the abort is immediate */
(void)HAL_DMA_Abort(huart->hdmarx);
}
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
}
@@ -2471,8 +2459,8 @@
/* Check received length : If all expected data are received, do nothing.
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
- if ( (huart->RxXferCount > 0U)
- &&(nb_rx_data > 0U) )
+ if ((huart->RxXferCount > 0U)
+ && (nb_rx_data > 0U))
{
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
@@ -2488,13 +2476,18 @@
huart->RxISR = NULL;
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Idle Event */
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxEventCallback(huart, nb_rx_data);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
return;
}
@@ -3288,7 +3281,7 @@
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
{
- huart->Instance->BRR = usartdiv;
+ huart->Instance->BRR = (uint16_t)usartdiv;
}
else
{
@@ -3423,6 +3416,7 @@
huart->gState = HAL_UART_STATE_READY;
huart->RxState = HAL_UART_STATE_READY;
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
__HAL_UNLOCK(huart);
@@ -3532,8 +3526,6 @@
huart->RxISR = UART_RxISR_8BIT_FIFOEN;
}
- __HAL_UNLOCK(huart);
-
/* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
{
@@ -3553,8 +3545,6 @@
huart->RxISR = UART_RxISR_8BIT;
}
- __HAL_UNLOCK(huart);
-
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
{
@@ -3563,7 +3553,7 @@
else
{
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
- }
+ }
}
return HAL_OK;
}
@@ -3607,15 +3597,12 @@
/* Set error code to DMA */
huart->ErrorCode = HAL_UART_ERROR_DMA;
- __HAL_UNLOCK(huart);
-
/* Restore huart->RxState to ready */
huart->RxState = HAL_UART_STATE_READY;
return HAL_ERROR;
}
}
- __HAL_UNLOCK(huart);
/* Enable the UART Parity Error Interrupt */
if (huart->Init.Parity != UART_PARITY_NONE)
@@ -3760,6 +3747,10 @@
}
}
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -3794,16 +3785,20 @@
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+ In this case, Rx Event type is Half Transfer */
+ huart->RxEventType = HAL_UART_RXEVENT_HT;
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : use Rx Event callback */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
{
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
- huart->RxEventCallback(huart, huart->RxXferSize/2U);
+ huart->RxEventCallback(huart, huart->RxXferSize / 2U);
#else
/*Call legacy weak Rx Event callback*/
- HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U);
+ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
else
@@ -4254,6 +4249,28 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+#if defined(LPUART1)
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+#else
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+#endif /* LPUART1 */
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4269,13 +4286,14 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4333,6 +4351,28 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+#if defined(LPUART1)
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+#else
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+#endif /* LPUART1 */
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4348,13 +4388,14 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4463,6 +4504,28 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+#if defined(LPUART1)
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+#else
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+#endif /* LPUART1 */
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4478,13 +4541,14 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
@@ -4613,6 +4677,28 @@
/* Clear RxISR function pointer */
huart->RxISR = NULL;
+ /* Initialize type of RxEvent to Transfer Complete */
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+#if defined(LPUART1)
+ if (!(IS_LPUART_INSTANCE(huart->Instance)))
+ {
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+ }
+#else
+ /* Check that USART RTOEN bit is set */
+ if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+ {
+ /* Enable the UART Receiver Timeout Interrupt */
+ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+ }
+#endif /* LPUART1 */
+
/* Check current reception Mode :
If Reception till IDLE event has been selected : */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
@@ -4628,13 +4714,14 @@
/* Clear IDLE Flag */
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
}
+
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx Event callback*/
huart->RxEventCallback(huart, huart->RxXferSize);
#else
/*Call legacy weak Rx Event callback*/
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
else
{
diff --git a/Src/stm32wbxx_hal_uart_ex.c b/Src/stm32wbxx_hal_uart_ex.c
index dad1f88..020bc8f 100644
--- a/Src/stm32wbxx_hal_uart_ex.c
+++ b/Src/stm32wbxx_hal_uart_ex.c
@@ -726,11 +726,10 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
huart->ErrorCode = HAL_UART_ERROR_NONE;
huart->RxState = HAL_UART_STATE_BUSY_RX;
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
@@ -754,8 +753,6 @@
pdata16bits = NULL;
}
- __HAL_UNLOCK(huart);
-
/* Initialize output number of received elements */
*RxLen = 0U;
@@ -772,6 +769,7 @@
/* If Set, and data has already been received, this means Idle Event is valid : End reception */
if (*RxLen > 0U)
{
+ huart->RxEventType = HAL_UART_RXEVENT_IDLE;
huart->RxState = HAL_UART_STATE_READY;
return HAL_OK;
@@ -851,10 +849,9 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_IT(huart, pData, Size);
@@ -917,10 +914,9 @@
return HAL_ERROR;
}
- __HAL_LOCK(huart);
-
/* Set Reception type to reception till IDLE Event*/
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ huart->RxEventType = HAL_UART_RXEVENT_TC;
status = UART_Start_Receive_DMA(huart, pData, Size);
@@ -951,6 +947,36 @@
}
/**
+ * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+ * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
+ * of reception process is provided to application through calls of Rx Event callback (either default one
+ * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
+ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
+ * to Rx Event callback execution.
+ * @note This function is expected to be called within the user implementation of Rx Event Callback,
+ * in order to provide the accurate value :
+ * In Interrupt Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one)
+ * In DMA Mode :
+ * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+ * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
+ * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+ * received data is lower than expected one).
+ * In DMA mode, RxEvent callback could be called several times;
+ * When DMA is configured in Normal Mode, HT event does not stop Reception process;
+ * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
+ * @param huart UART handle.
+ * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
+ */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
+{
+ /* Return Rx Event type value, as stored in UART handle */
+ return (huart->RxEventType);
+}
+
+/**
* @}
*/
diff --git a/Src/stm32wbxx_hal_usart.c b/Src/stm32wbxx_hal_usart.c
index 8912c77..1133d89 100644
--- a/Src/stm32wbxx_hal_usart.c
+++ b/Src/stm32wbxx_hal_usart.c
@@ -405,6 +405,8 @@
/**
* @brief Register a User USART Callback
* To be used instead of the weak predefined callback
+ * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+ * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
* @param husart usart handle
* @param CallbackID ID of the callback to be registered
* This parameter can be one of the following values:
@@ -434,8 +436,6 @@
return HAL_ERROR;
}
- /* Process locked */
- __HAL_LOCK(husart);
if (husart->State == HAL_USART_STATE_READY)
{
@@ -524,15 +524,14 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(husart);
-
return status;
}
/**
* @brief Unregister an USART Callback
* USART callaback is redirected to the weak predefined callback
+ * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET
+ * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID
* @param husart usart handle
* @param CallbackID ID of the callback to be unregistered
* This parameter can be one of the following values:
@@ -553,9 +552,6 @@
{
HAL_StatusTypeDef status = HAL_OK;
- /* Process locked */
- __HAL_LOCK(husart);
-
if (HAL_USART_STATE_READY == husart->State)
{
switch (CallbackID)
@@ -643,9 +639,6 @@
status = HAL_ERROR;
}
- /* Release Lock */
- __HAL_UNLOCK(husart);
-
return status;
}
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
diff --git a/Src/stm32wbxx_ll_adc.c b/Src/stm32wbxx_ll_adc.c
index b7325b3..91a4e7f 100644
--- a/Src/stm32wbxx_ll_adc.c
+++ b/Src/stm32wbxx_ll_adc.c
@@ -66,12 +66,12 @@
#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (512UL * 16UL * 4UL)
#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Note: CCRDY handshake requires 1APB + 2 ADC + 3 APB cycles */
/* after the channel configuration has been changed. */
/* Driver timeout is approximated to 6 CPU cycles. */
#define ADC_TIMEOUT_CCRDY_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 6UL)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/**
* @}
@@ -85,7 +85,7 @@
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
@@ -118,11 +118,11 @@
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_CLOCK(__CLOCK__) \
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
@@ -130,7 +130,7 @@
|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
@@ -143,7 +143,7 @@
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
@@ -155,10 +155,10 @@
( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group regular */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
@@ -180,7 +180,7 @@
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
@@ -198,14 +198,14 @@
|| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
)
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_REG_SEQ_MODE(__REG_SEQ_MODE__) \
( ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_FIXED) \
|| ((__REG_SEQ_MODE__) == LL_ADC_REG_SEQ_CONFIGURABLE) \
)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
@@ -235,8 +235,8 @@
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
)
-#endif
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#endif /* ADC_SUPPORT_2_5_MSPS */
+#if defined(ADC_SUPPORT_2_5_MSPS)
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
@@ -253,7 +253,7 @@
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group injected */
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
@@ -324,7 +324,7 @@
/* Prevent unused argument compilation warning */
(void)(ADCxy_COMMON);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Force reset of ADC clock (core clock) */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
@@ -356,7 +356,7 @@
* - SUCCESS: ADC common registers are initialized
* - ERROR: ADC common registers are not initialized
*/
-ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
{
ErrorStatus status = SUCCESS;
@@ -429,7 +429,7 @@
/* Set ADC_CommonInitStruct fields to default values */
/* Set fields of ADC common */
/* (all ADC instances belonging to the same ADC common instance) */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2;
#else
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
@@ -478,7 +478,7 @@
}
}
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
/* Set ADC group injected trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
@@ -519,15 +519,15 @@
break;
}
}
-#endif /* ADC_SUPPORT_2_5_MSPS */
+#endif /* !ADC_SUPPORT_2_5_MSPS */
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
/* Flush group injected contexts queue (register JSQR): */
/* Note: Bit JQM must be set to empty the contexts queue (otherwise */
/* contexts queue is maintained with the last active context). */
LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
/* Disable the ADC instance */
LL_ADC_Disable(ADCx);
@@ -546,7 +546,7 @@
}
/* Check whether ADC state is compliant with expected state */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if (READ_BIT(ADCx->CR,
(ADC_CR_ADSTP | ADC_CR_ADSTART
| ADC_CR_ADDIS | ADC_CR_ADEN )
@@ -558,7 +558,7 @@
| ADC_CR_ADDIS | ADC_CR_ADEN)
)
== 0UL)
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
{
/* ========== Reset ADC registers ========== */
/* Reset register IER */
@@ -568,17 +568,17 @@
| LL_ADC_IT_EOS
| LL_ADC_IT_OVR
| LL_ADC_IT_EOSMP
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
| LL_ADC_IT_JEOC
| LL_ADC_IT_JEOS
| LL_ADC_IT_JQOVF
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
| LL_ADC_IT_AWD1
| LL_ADC_IT_AWD2
| LL_ADC_IT_AWD3
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
| LL_ADC_IT_CCRDY
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
)
);
@@ -589,21 +589,21 @@
| LL_ADC_FLAG_EOS
| LL_ADC_FLAG_OVR
| LL_ADC_FLAG_EOSMP
-#if !defined (ADC_SUPPORT_2_5_MSPS)
+#if !defined(ADC_SUPPORT_2_5_MSPS)
| LL_ADC_FLAG_JEOC
| LL_ADC_FLAG_JEOS
| LL_ADC_FLAG_JQOVF
-#endif
+#endif /* !ADC_SUPPORT_2_5_MSPS */
| LL_ADC_FLAG_AWD1
| LL_ADC_FLAG_AWD2
| LL_ADC_FLAG_AWD3
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
| LL_ADC_FLAG_CCRDY
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
)
);
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Reset register CR */
/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
/* "read-set": no direct reset applicable. */
@@ -621,9 +621,9 @@
/* already done above. */
CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Reset register CFGR1 */
CLEAR_BIT(ADCx->CFGR1,
( ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN
@@ -662,13 +662,13 @@
/* Clear flag ADC channel configuration ready */
LL_ADC_ClearFlag_CCRDY(ADCx);
-
+
/* Reset register DR */
/* bits in access mode read only, no direct reset applicable */
-
+
/* Reset register CALFACT */
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT);
-
+
/* Reset register CFGR2 */
/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
/* already done above. */
@@ -777,7 +777,7 @@
/* Reset register CALFACT */
CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
else
{
@@ -826,16 +826,16 @@
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
-ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *ADC_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
@@ -849,7 +849,7 @@
/* - Set ADC data resolution */
/* - Set ADC conversion data alignment */
/* - Set ADC low power mode */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
MODIFY_REG(ADCx->CFGR1,
ADC_CFGR1_RES
| ADC_CFGR1_ALIGN
@@ -876,7 +876,7 @@
| ADC_InitStruct->DataAlignment
| ADC_InitStruct->LowPowerMode
);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
else
{
@@ -896,9 +896,9 @@
{
/* Set ADC_InitStruct fields to default values */
/* Set fields of ADC instance */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
@@ -940,14 +940,14 @@
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
-ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
@@ -974,7 +974,7 @@
assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
|| (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
}
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
@@ -994,7 +994,7 @@
/* - Set ADC group regular overrun behavior */
/* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by */
/* setting of trigger source to SW start. */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if( (LL_ADC_REG_GetSequencerConfigurable(ADCx) == LL_ADC_REG_SEQ_FIXED)
|| (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
)
@@ -1081,14 +1081,14 @@
#endif /* ADC_SUPPORT_2_5_MSPS */
/* Set ADC group regular sequencer length and scan direction */
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
if (LL_ADC_REG_GetSequencerConfigurable(ADCx) != LL_ADC_REG_SEQ_FIXED)
{
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
}
#else
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
-#endif
+#endif /* ADC_SUPPORT_2_5_MSPS */
}
else
{
@@ -1118,7 +1118,7 @@
ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
}
-#if defined (ADC_SUPPORT_2_5_MSPS)
+#if defined(ADC_SUPPORT_2_5_MSPS)
/* Feature "ADC group injected" not available on ADC peripheral of this STM32WB device */
#else
/**
@@ -1159,7 +1159,7 @@
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
-ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
{
ErrorStatus status = SUCCESS;
diff --git a/Src/stm32wbxx_ll_comp.c b/Src/stm32wbxx_ll_comp.c
index b41f12e..dc16d54 100644
--- a/Src/stm32wbxx_ll_comp.c
+++ b/Src/stm32wbxx_ll_comp.c
@@ -182,7 +182,7 @@
* - SUCCESS: COMP registers are initialized
* - ERROR: COMP registers are not initialized
*/
-ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct)
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct)
{
ErrorStatus status = SUCCESS;
diff --git a/Src/stm32wbxx_ll_exti.c b/Src/stm32wbxx_ll_exti.c
index f5ef90c..0c75551 100644
--- a/Src/stm32wbxx_ll_exti.c
+++ b/Src/stm32wbxx_ll_exti.c
@@ -23,7 +23,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32WBxx_LL_Driver
* @{
@@ -47,14 +47,14 @@
#define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U)
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
- || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
- || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
+ || ((__VALUE__) == LL_EXTI_MODE_EVENT) \
+ || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
- || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
+ || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
/**
* @}
@@ -81,40 +81,40 @@
{
/* Rising Trigger selection register set to default reset values */
LL_EXTI_WriteReg(RTSR1, 0x00000000U);
-
+
/* Falling Trigger selection register set to default reset values */
LL_EXTI_WriteReg(FTSR1, 0x00000000U);
-
+
/* Software interrupt event register set to default reset values */
LL_EXTI_WriteReg(SWIER1, 0x00000000U);
-
+
/* Pending register set to default reset values */
LL_EXTI_WriteReg(PR1, 0xFFFFFFFFu);
/* Rising Trigger selection register 2 set to default reset values */
LL_EXTI_WriteReg(RTSR2, 0x00000000U);
-
+
/* Falling Trigger selection register 2 set to default reset values */
LL_EXTI_WriteReg(FTSR2, 0x00000000U);
-
+
/* Software interrupt event register 2 set to default reset values */
LL_EXTI_WriteReg(SWIER2, 0x00000000U);
-
+
/* Pending register 2 set to default reset values */
LL_EXTI_WriteReg(PR2, 0xFFFFFFFFu);
-
+
/* Interrupt mask register set to default reset values */
LL_EXTI_WriteReg(IMR1, 0x00000000U);
LL_EXTI_WriteReg(C2IMR1, 0x00000000U);
-
+
/* Event mask register set to default reset values */
LL_EXTI_WriteReg(EMR1, 0x00000000U);
LL_EXTI_WriteReg(C2EMR1, 0x00000000U);
-
+
/* Interrupt mask register 2 set to default reset values */
LL_EXTI_WriteReg(IMR2, 0x00000000U);
LL_EXTI_WriteReg(C2IMR2, 0x00000000U);
-
+
/* Event mask register 2 set to default reset values */
LL_EXTI_WriteReg(EMR2, 0x00000000U);
LL_EXTI_WriteReg(C2EMR2, 0x00000000U);
diff --git a/Src/stm32wbxx_ll_lptim.c b/Src/stm32wbxx_ll_lptim.c
index 34756ce..d7003f5 100644
--- a/Src/stm32wbxx_ll_lptim.c
+++ b/Src/stm32wbxx_ll_lptim.c
@@ -280,8 +280,7 @@
do
{
rcc_clock.SYSCLK_Frequency--; /* Used for timeout */
- }
- while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
+ } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL));
LL_LPTIM_ClearFlag_ARROK(LPTIMx);
}
diff --git a/Src/stm32wbxx_ll_rtc.c b/Src/stm32wbxx_ll_rtc.c
index 7ed96ba..ae7756d 100644
--- a/Src/stm32wbxx_ll_rtc.c
+++ b/Src/stm32wbxx_ll_rtc.c
@@ -24,7 +24,7 @@
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
-#endif
+#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32WBxx_LL_Driver
* @{
@@ -406,12 +406,14 @@
/* Check the input parameters format */
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
- LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
+ LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month,
+ RTC_DateStruct->Year);
}
else
{
LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
- __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month),
+ __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
}
/* Exit Initialization mode */
diff --git a/Src/stm32wbxx_ll_tim.c b/Src/stm32wbxx_ll_tim.c
index d52f05c..bd7713c 100644
--- a/Src/stm32wbxx_ll_tim.c
+++ b/Src/stm32wbxx_ll_tim.c
@@ -711,13 +711,10 @@
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
- if (IS_TIM_ADVANCED_INSTANCE(TIMx))
- {
- assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
- assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
- MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
- }
+ assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
+ assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
+ MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
if (IS_TIM_BKIN2_INSTANCE(TIMx))
{
diff --git a/Src/stm32wbxx_ll_usb.c b/Src/stm32wbxx_ll_usb.c
index 7703cff..1cd629c 100644
--- a/Src/stm32wbxx_ll_usb.c
+++ b/Src/stm32wbxx_ll_usb.c
@@ -27,7 +27,7 @@
##### How to use this driver #####
==============================================================================
[..]
- (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
+ (#) Fill parameters of Init structure in USB_CfgTypeDef structure.
(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
@@ -749,9 +749,9 @@
/**
* @brief USB_ReadInterrupts return the global USB interrupt status
* @param USBx Selected device
- * @retval HAL status
+ * @retval USB Global Interrupt status
*/
-uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
+uint32_t USB_ReadInterrupts(USB_TypeDef *USBx)
{
uint32_t tmpreg;
