| { |
| "homepage": "https://github.com/hw-bzl/rules_verilog", |
| "maintainers": [ |
| { |
| "name": "MrAMS", |
| "email": "25056812+MrAMS@users.noreply.github.com", |
| "github": "MrAMS", |
| "github_user_id": 25056812 |
| }, |
| { |
| "name": "UebelAndre", |
| "email": "26427366+UebelAndre@users.noreply.github.com", |
| "github": "UebelAndre", |
| "github_user_id": 26427366 |
| } |
| ], |
| "repository": [ |
| "github:hw-bzl/bazel_rules_verilog", |
| "github:hw-bzl/rules_verilog" |
| ], |
| "versions": [ |
| "0.1.0", |
| "1.0.0", |
| "1.1.0", |
| "1.1.1", |
| "1.2.0", |
| "1.3.0", |
| "1.4.0", |
| "1.4.1", |
| "1.4.2" |
| ], |
| "yanked_versions": {} |
| } |