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graham sanderson26653ea2021-01-20 10:44:27 -06001/*
2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
andygpz11a42564b2023-03-21 17:49:20 +00007// For frequency and PLL definitions etc.
graham sanderson26653ea2021-01-20 10:44:27 -06008#include "hardware/clocks.h"
9#include "hardware/pll.h"
majbthrd16209862021-04-06 04:42:18 -050010#include "hardware/resets.h"
graham sanderson26653ea2021-01-20 10:44:27 -060011
12/// \tag::pll_init_calculations[]
graham sanderson503bc8b2021-02-19 12:05:13 -060013void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) {
andygpz11a42564b2023-03-21 17:49:20 +000014 uint32_t ref_freq = XOSC_KHZ * KHZ / refdiv;
graham sanderson26653ea2021-01-20 10:44:27 -060015
Liam Fraser33818dd2022-06-20 16:28:03 +010016 // Check vco freq is in an acceptable range
andygpz11a42564b2023-03-21 17:49:20 +000017 assert(vco_freq >= (PICO_PLL_VCO_MIN_FREQ_KHZ * KHZ) && vco_freq <= (PICO_PLL_VCO_MAX_FREQ_KHZ * KHZ));
Liam Fraser33818dd2022-06-20 16:28:03 +010018
graham sanderson26653ea2021-01-20 10:44:27 -060019 // What are we multiplying the reference clock by to get the vco freq
20 // (The regs are called div, because you divide the vco output and compare it to the refclk)
andygpz11a42564b2023-03-21 17:49:20 +000021 uint32_t fbdiv = vco_freq / ref_freq;
graham sanderson26653ea2021-01-20 10:44:27 -060022/// \end::pll_init_calculations[]
23
24 // fbdiv
25 assert(fbdiv >= 16 && fbdiv <= 320);
26
27 // Check divider ranges
28 assert((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7));
29
30 // post_div1 should be >= post_div2
31 // from appnote page 11
Liam Fraserc5784222023-01-24 15:10:05 +000032 // postdiv1 is designed to operate with a higher input frequency than postdiv2
graham sanderson26653ea2021-01-20 10:44:27 -060033
graham sanderson26653ea2021-01-20 10:44:27 -060034 // Check that reference frequency is no greater than vco / 16
andygpz11a42564b2023-03-21 17:49:20 +000035 assert(ref_freq <= (vco_freq / 16));
graham sanderson26653ea2021-01-20 10:44:27 -060036
majbthrd16209862021-04-06 04:42:18 -050037 // div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10
38 uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) |
39 (post_div2 << PLL_PRIM_POSTDIV2_LSB);
40
41/// \tag::pll_init_finish[]
42 if ((pll->cs & PLL_CS_LOCK_BITS) &&
43 (refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) &&
44 (fbdiv == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) &&
Graham Sandersone1c5fd32022-05-09 14:52:38 -050045 (pdiv == (pll->prim & (PLL_PRIM_POSTDIV1_BITS | PLL_PRIM_POSTDIV2_BITS)))) {
majbthrd16209862021-04-06 04:42:18 -050046 // do not disrupt PLL that is already correctly configured and operating
47 return;
48 }
49
50 uint32_t pll_reset = (pll_usb_hw == pll) ? RESETS_RESET_PLL_USB_BITS : RESETS_RESET_PLL_SYS_BITS;
51 reset_block(pll_reset);
52 unreset_block_wait(pll_reset);
53
54 // Load VCO-related dividers before starting VCO
55 pll->cs = refdiv;
graham sanderson26653ea2021-01-20 10:44:27 -060056 pll->fbdiv_int = fbdiv;
57
58 // Turn on PLL
59 uint32_t power = PLL_PWR_PD_BITS | // Main power
60 PLL_PWR_VCOPD_BITS; // VCO Power
61
62 hw_clear_bits(&pll->pwr, power);
63
64 // Wait for PLL to lock
65 while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents();
66
majbthrd16209862021-04-06 04:42:18 -050067 // Set up post dividers
graham sanderson26653ea2021-01-20 10:44:27 -060068 pll->prim = pdiv;
69
70 // Turn on post divider
71 hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS);
72/// \end::pll_init_finish[]
73}
74
75void pll_deinit(PLL pll) {
76 // todo: Make sure there are no sources running from this pll?
77 pll->pwr = PLL_PWR_BITS;
majbthrd16209862021-04-06 04:42:18 -050078}