| # Microchip XEC ESPI configuration options |
| |
| # Copyright (c) 2019 Intel Corporation |
| # Copyright (c) 2021 Microchip Technology Inc. |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config ESPI_XEC_V2 |
| bool "XEC Microchip ESPI V2 driver" |
| depends on SOC_SERIES_MEC172X |
| help |
| Enable the Microchip XEC ESPI driver for MEC172x series. |
| |
| if ESPI_XEC_V2 |
| |
| config ESPI_OOB_CHANNEL |
| default y |
| |
| config ESPI_FLASH_CHANNEL |
| default y |
| |
| config ESPI_PERIPHERAL_HOST_IO |
| default y |
| |
| config ESPI_PERIPHERAL_HOST_IO_PVT |
| default y |
| |
| config ESPI_PERIPHERAL_DEBUG_PORT_80 |
| default y |
| |
| config ESPI_PERIPHERAL_8042_KBC |
| default y |
| |
| config ESPI_PERIPHERAL_UART |
| default y |
| |
| config ESPI_PERIPHERAL_UART_SOC_MAPPING |
| int "SoC port exposed as logical eSPI UART" |
| default 1 |
| depends on ESPI_PERIPHERAL_UART |
| help |
| This tells the driver to which SoC UART to direct the UART traffic |
| send over eSPI from host. MEC172x implements two UARTs. |
| |
| config ESPI_PERIPHERAL_XEC_MAILBOX |
| bool "SoC Mailbox over eSPI" |
| depends on ESPI_PERIPHERAL_CHANNEL |
| help |
| Enable a 32 byte mailbox interface accessible via Host I/O over the |
| ESPI Peripheral Channel. |
| |
| config ESPI_PERIPHERAL_XEC_ACPI_EC2 |
| bool "SoC ACPI EC 2 over eSPI" |
| depends on ESPI_PERIPHERAL_CHANNEL |
| help |
| Enable ACPI EC2 interface accessible via Host I/O over the |
| ESPI Peripheral Channel. |
| |
| config ESPI_PERIPHERAL_XEC_ACPI_EC3 |
| bool "SoC ACPI EC 3 over eSPI" |
| depends on ESPI_PERIPHERAL_CHANNEL |
| help |
| Enable ACPI EC3 interface accessible via Host I/O over the |
| ESPI Peripheral Channel. |
| |
| config ESPI_PERIPHERAL_XEC_ACPI_EC4 |
| bool "SoC ACPI EC 4 over eSPI" |
| depends on ESPI_PERIPHERAL_CHANNEL |
| help |
| Enable ACPI EC4 interface accessible via Host I/O over the |
| ESPI Peripheral Channel. |
| |
| config ESPI_PERIPHERAL_XEC_ACPI_PM1 |
| bool "SoC ACPI PM1 over eSPI" |
| depends on ESPI_PERIPHERAL_CHANNEL |
| help |
| Enable ACPI PM1 interface accessible via Host I/O over the |
| ESPI Peripheral Channel. |
| |
| config ESPI_PERIPHERAL_XEC_EMI0 |
| bool "SoC EMI 0 over eSPI" |
| depends on ESPI_PERIPHERAL_CHANNEL |
| help |
| Enable EMI 0 interface accessible via Host I/O over the |
| ESPI Peripheral Channel. |
| |
| config ESPI_PERIPHERAL_XEC_EMI1 |
| bool "SoC EMI 1 over eSPI" |
| depends on ESPI_PERIPHERAL_CHANNEL |
| help |
| Enable EMI 1 interface accessible via Host I/O over the |
| ESPI Peripheral Channel. |
| |
| config ESPI_PERIPHERAL_XEC_EMI2 |
| bool "SoC EMI 2 over eSPI" |
| depends on ESPI_PERIPHERAL_CHANNEL |
| help |
| Enable EMI 2 interface accessible via Host I/O over the |
| ESPI Peripheral Channel. |
| |
| config ESPI_OOB_BUFFER_SIZE |
| int "eSPI OOB channel buffer size in bytes" |
| default 128 |
| depends on ESPI_OOB_CHANNEL |
| help |
| Use minimum RAM buffer size by default but allow applications to |
| override the value. |
| Maximum OOB payload is 73 bytes. |
| |
| config ESPI_FLASH_BUFFER_SIZE |
| int "eSPI Flash channel buffer size in bytes" |
| default 256 |
| depends on ESPI_FLASH_CHANNEL |
| help |
| Use maximum RAM buffer size defined by spec but allow applications |
| to override if eSPI host doesn't support it. |
| |
| config ESPI_SAF |
| bool "XEC Microchip ESPI SAF driver" |
| depends on ESPI_FLASH_CHANNEL |
| default n |
| help |
| Enable Slave Attached Flash eSPI driver. SAF depends upon ESPI XEC driver |
| and flash channel. |
| |
| config ESPI_SAF_INIT_PRIORITY |
| int "ESPI SAF driver initialization priority" |
| depends on ESPI_SAF |
| default 4 |
| help |
| Driver initialization priority for eSPI SAF driver. |
| |
| endif #ESPI_XEC_V2 |
