| /* |
| * Copyright 2022-2023 NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/nxp/nxp_s32z27x_r52.dtsi> |
| |
| / { |
| |
| cpus { |
| /delete-node/ cpu@0; |
| /delete-node/ cpu@1; |
| /delete-node/ cpu@2; |
| /delete-node/ cpu@3; |
| }; |
| |
| soc { |
| stm0: stm@76a00000 { |
| compatible = "nxp,s32-sys-timer"; |
| reg = <0x76a00000 0x10000>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>; |
| status = "disabled"; |
| }; |
| |
| stm1: stm@76a10000 { |
| compatible = "nxp,s32-sys-timer"; |
| reg = <0x76a10000 0x10000>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>; |
| status = "disabled"; |
| }; |
| |
| stm2: stm@76820000 { |
| compatible = "nxp,s32-sys-timer"; |
| reg = <0x76820000 0x10000>; |
| interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>; |
| status = "disabled"; |
| }; |
| |
| stm3: stm@76830000 { |
| compatible = "nxp,s32-sys-timer"; |
| reg = <0x76830000 0x10000>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_RTU1_REG_INTF_CLK>; |
| status = "disabled"; |
| }; |
| |
| swt0: watchdog@76800000 { |
| compatible = "nxp,s32-swt"; |
| reg = <0x76800000 0x10000>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_FIRC_CLK>; |
| status = "disabled"; |
| }; |
| |
| swt1: watchdog@76810000 { |
| compatible = "nxp,s32-swt"; |
| reg = <0x76810000 0x10000>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_FIRC_CLK>; |
| status = "disabled"; |
| }; |
| |
| swt2: watchdog@76a20000 { |
| compatible = "nxp,s32-swt"; |
| reg = <0x76a20000 0x10000>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_FIRC_CLK>; |
| status = "disabled"; |
| }; |
| |
| swt3: watchdog@76a30000 { |
| compatible = "nxp,s32-swt"; |
| reg = <0x76a30000 0x10000>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_FIRC_CLK>; |
| status = "disabled"; |
| }; |
| |
| swt4: watchdog@76940000 { |
| compatible = "nxp,s32-swt"; |
| reg = <0x76940000 0x10000>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_FIRC_CLK>; |
| status = "disabled"; |
| }; |
| |
| pit0: pit@76950000 { |
| compatible = "nxp,pit"; |
| reg = <0x76950000 0x10000>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clock NXP_S32_P1_REG_INTF_CLK>; |
| max-load-value = <0x00ffffff>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| pit0_channel0: pit0_channel@0 { |
| compatible = "nxp,pit-channel"; |
| reg = <0>; |
| status = "disabled"; |
| }; |
| |
| pit0_channel1: pit0_channel@1 { |
| compatible = "nxp,pit-channel"; |
| reg = <1>; |
| status = "disabled"; |
| }; |
| |
| pit0_channel2: pit0_channel@2 { |
| compatible = "nxp,pit-channel"; |
| reg = <2>; |
| status = "disabled"; |
| }; |
| |
| pit0_channel3: pit0_channel@3 { |
| compatible = "nxp,pit-channel"; |
| reg = <3>; |
| status = "disabled"; |
| }; |
| |
| pit0_channel4: pit0_channel@4 { |
| compatible = "nxp,pit-channel"; |
| reg = <4>; |
| status = "disabled"; |
| }; |
| |
| pit0_channel5: pit0_channel@5 { |
| compatible = "nxp,pit-channel"; |
| reg = <5>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| }; |