dts/arm/ti/am62x_m4.dtsi

/*
 * Copyright (c) 2023 Texas Instruments Incorporated
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <freq.h>
#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <ti/k3-am62-main.dtsi>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m4f";
			reg = <0>;
		};
	};

	/*
	 * I-RAM and D-RAM can be used in unified mode, i.e. instruction code and data can be placed
	 * in any bank. Since unaligned accesses are converted internally by the CM4 into
	 * aligned accesses of smaller sizes, even accessing unaligned data at the boundary
	 * between I-RAM and D-RAM should not cause problems in unified mode. However, note
	 * that using unified mode can have a performance penalty.
	 */
	sram0: memory@0 {
		compatible = "mmio-sram";
		reg = <0x0 DT_SIZE_K(256)>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;

		/* 192 KB of SRAM (I-Code) */
		sram_icode: memory@0 {
			device_type = "memory";
			reg = <0x00000000 DT_SIZE_K(192)>;
		};

		/* 64 KB of SRAM (D-Code) */
		sram_dcode: memory@30000 {
			device_type = "memory";
			reg = <0x00030000 DT_SIZE_K(64)>;
		};
	};

	sysclk: system-clock {
		compatible = "fixed-clock";
		clock-frequency = <DT_FREQ_M(400)>;
		#clock-cells = <0>;
	};

	mbox0: mailbox@29000000 {
		compatible = "ti,omap-mailbox";
		reg = <0x29000000 0x200>;
		interrupts = <50 4>;
		interrupt-parent = <&nvic>;
		usr-id = <2>;
		#mbox-cells = <1>;
	};

	pinctrl: pinctrl@4084000 {
		compatible = "ti,k3-pinctrl";
		reg = <0x04084000 0x88>;
		status = "okay";
	};

	uart0: serial@4a00000 {
		compatible = "ns16550";
		reg = <0x04a00000 0x200>;
		interrupts = <24 4>;
		interrupt-parent = <&nvic>;
		clock-frequency = <DT_FREQ_M(48)>;
		current-speed = <115200>;
		reg-shift = <2>;
		status = "disabled";
	};

	i2c0: i2c@4900000 {
		compatible = "ti,omap-i2c";
		reg = <0x04900000 0x100>;
		interrupts = <17 4>;
		interrupt-parent = <&nvic>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	gpio0: gpio@4201000 {
		compatible = "ti,davinci-gpio";
		reg = <0x4201000 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		ngpios = <24>;
		status = "disabled";
	};

	mcu_rti0: watchdog@4880000 {
		compatible = "ti,j7-rti-wdt";
		reg = <0x04880000 0x100>;
		clock-frequency = <DT_FREQ_M(25)>;
		status = "disabled";
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};

&systick {
	status = "okay";
};