| /* |
| * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| * |
| */ |
| |
| #include <arm/armv7-a.dtsi> |
| #include <mem.h> |
| #include <zephyr/dt-bindings/clock/microchip_sam_pmc.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| model = "Microchip SAMA7G5 family SoC"; |
| compatible = "microchip,sama7g5"; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a7"; |
| reg = <0>; |
| }; |
| }; |
| |
| clocks { |
| main_xtal: main_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| |
| slow_xtal: slow_xtal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| soc { |
| sram: memory@100000 { |
| compatible = "mmio-sram"; |
| reg = <0x00100000 DT_SIZE_K(128)>; |
| }; |
| |
| pinctrl: pinctrl@e0014000 { |
| compatible = "microchip,sama7g5-pinctrl"; |
| reg = <0xe0014000 0x800>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0xe0014000 0xe0014000 0x800>; |
| |
| pioa: gpio@e0014000 { |
| compatible = "microchip,sam-pio4"; |
| reg = <0xe0014000 0x40>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; |
| }; |
| |
| piob: gpio@e0014040 { |
| compatible = "microchip,sam-pio4"; |
| reg = <0xe0014040 0x40>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; |
| }; |
| |
| pioc: gpio@e0014080 { |
| compatible = "microchip,sam-pio4"; |
| reg = <0xe0014080 0x40>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; |
| }; |
| |
| piod: gpio@e00140c0 { |
| compatible = "microchip,sam-pio4"; |
| reg = <0xe00140c0 0x40>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; |
| }; |
| |
| pioe: gpio@e0014100 { |
| compatible = "microchip,sam-pio4"; |
| reg = <0xe0014100 0x40>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; |
| gpio-reserved-ranges = <8 24>; |
| }; |
| }; |
| |
| pmc: clock-controller@e0018000 { |
| compatible = "microchip,sam-pmc"; |
| reg = <0xe0018000 0x200>; |
| #clock-cells = <2>; |
| clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; |
| clock-names = "td_slck", "md_slck", "main_xtal"; |
| }; |
| |
| clk32k: clock-controller@e001d050 { |
| compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc"; |
| reg = <0xe001d050 0x4>; |
| clocks = <&slow_xtal>; |
| #clock-cells = <1>; |
| }; |
| |
| rtc: rtc@e001d0a8 { |
| compatible = "atmel,sam-rtc"; |
| reg = <0xe001d0a8 0x30>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&clk32k 1>; |
| }; |
| |
| mcan0: mcan@e0828000 { |
| compatible = "atmel,sam-can"; |
| reg = <0xe0828000 0x100>, <0x100000 0x7800>, <0xe1626030 0x4>; |
| reg-names = "m_can", "message_ram", "sram_sel"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 123 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "int0", "int1"; |
| clocks = <&pmc PMC_TYPE_GCK 61>; |
| clock-names = "gck"; |
| bosch,mram-cfg = <0x3400 15 15 8 8 0 15 15>; |
| status = "disabled"; |
| }; |
| |
| mcan1: mcan@e082c000 { |
| compatible = "atmel,sam-can"; |
| reg = <0xe082c000 0x100>, <0x100000 0xbc00>, <0xe1626030 0x4>; |
| reg-names = "m_can", "message_ram", "sram_sel"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 124 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "int0", "int1"; |
| clocks = <&pmc PMC_TYPE_GCK 62>; |
| clock-names = "gck"; |
| bosch,mram-cfg = <0x7800 15 15 8 8 0 15 15>; |
| status = "disabled"; |
| }; |
| |
| mcan2: mcan@e0830000 { |
| compatible = "atmel,sam-can"; |
| reg = <0xe0830000 0x100>, <0x100000 0x10000>, <0xe1626030 0x4>; |
| reg-names = "m_can", "message_ram", "sram_sel"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 125 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "int0", "int1"; |
| clocks = <&pmc PMC_TYPE_GCK 63>; |
| clock-names = "gck"; |
| bosch,mram-cfg = <0xbc00 15 15 8 8 0 15 15>; |
| status = "disabled"; |
| }; |
| |
| mcan3: mcan@e0834000 { |
| compatible = "atmel,sam-can"; |
| reg = <0xe0834000 0x100>, <0x110000 0x4400>, <0xe1626030 0x4>; |
| reg-names = "m_can", "message_ram", "sram_sel"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 126 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "int0", "int1"; |
| clocks = <&pmc PMC_TYPE_GCK 64>; |
| clock-names = "gck"; |
| bosch,mram-cfg = <0x0 15 15 8 8 0 15 15>; |
| status = "disabled"; |
| }; |
| |
| mcan4: mcan@e0838000 { |
| compatible = "atmel,sam-can"; |
| reg = <0xe0838000 0x100>, <0x110000 0x8800>, <0xe1626030 0x4>; |
| reg-names = "m_can", "message_ram", "sram_sel"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 127 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "int0", "int1"; |
| clocks = <&pmc PMC_TYPE_GCK 65>; |
| clock-names = "gck"; |
| bosch,mram-cfg = <0x4400 15 15 8 8 0 15 15>; |
| status = "disabled"; |
| }; |
| |
| mcan5: mcan@e083c000 { |
| compatible = "atmel,sam-can"; |
| reg = <0xe083c000 0x100>, <0x100000 0xcc00>, <0xe1626030 0x4>; |
| reg-names = "m_can", "message_ram", "sram_sel"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 128 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "int0", "int1"; |
| clocks = <&pmc PMC_TYPE_GCK 66>; |
| clock-names = "gck"; |
| bosch,mram-cfg = <0x8800 15 15 8 8 0 15 15>; |
| status = "disabled"; |
| }; |
| |
| dma2: dma-controller@e1200000 { |
| compatible = "atmel,sam-xdmac"; |
| reg = <0xe1200000 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #dma-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; |
| clock-names = "dma_clk"; |
| status = "disabled"; |
| }; |
| |
| sdmmc0: mmc@e1204000 { |
| compatible = "microchip,sama7g5-sdmmc"; |
| reg = <0xe1204000 0x4000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>; |
| clock-names = "hclock", "multclk"; |
| assigned-clock-rates = <200000000>; |
| status = "disabled"; |
| }; |
| |
| sdmmc1: mmc@e1208000 { |
| compatible = "microchip,sama7g5-sdmmc"; |
| reg = <0xe1208000 0x4000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>; |
| clock-names = "hclock", "multclk"; |
| assigned-clock-rates = <200000000>; |
| status = "disabled"; |
| }; |
| |
| pwm: pwm@e1604000 { |
| compatible = "atmel,sam-pwm"; |
| reg = <0xe1604000 0x4000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 77>; |
| prescaler = <10>; |
| divider = <1>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pit64b0: timer@e1800000 { |
| compatible = "microchip,sam-pit64b", "microchip,sam9x60-pit64b"; |
| reg = <0xe1800000 0x4000>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>; |
| clock-names = "pclk", "gclk"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| }; |
| |
| flx0: flexcom@e1818000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe1818000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe1818000 0x800>; |
| status = "disabled"; |
| |
| i2c0: i2c0@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; |
| status = "disabled"; |
| }; |
| |
| usart0: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flx1: flexcom@e181c000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe181c000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe181c000 0x800>; |
| status = "disabled"; |
| |
| i2c1: i2c1@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flx2: flexcom@e1820000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe1820000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe1820000 0x800>; |
| status = "disabled"; |
| |
| i2c2: i2c2@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flx3: flexcom@e1824000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe1824000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe1824000 0x800>; |
| status = "disabled"; |
| |
| i2c3: i2c3@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; |
| status = "disabled"; |
| }; |
| |
| usart3: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| trng: rng@e2010000 { |
| compatible = "atmel,sam-trng"; |
| reg = <0xe2010000 0x100>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 97>; |
| status = "disabled"; |
| }; |
| |
| flx4: flexcom@e2018000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe2018000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe2018000 0x800>; |
| status = "disabled"; |
| |
| i2c4: i2c4@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; |
| status = "disabled"; |
| }; |
| |
| usart4: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flx5: flexcom@e201c000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe201c000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe201c000 0x800>; |
| status = "disabled"; |
| |
| i2c5: i2c5@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; |
| status = "disabled"; |
| }; |
| |
| usart5: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flx6: flexcom@e2020000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe2020000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe2020000 0x800>; |
| status = "disabled"; |
| |
| i2c6: i2c6@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; |
| status = "disabled"; |
| }; |
| |
| usart6: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flx7: flexcom@e2024000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe2024000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe2024000 0x800>; |
| status = "disabled"; |
| |
| i2c7: i2c7@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; |
| status = "disabled"; |
| }; |
| |
| usart7: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| ethernet@e2800000 { |
| compatible = "microchip,sam-ethernet-controller"; |
| reg = <0xe2800000 0x4000>; |
| clocks = <&pmc PMC_TYPE_GCK 51>; |
| |
| gmac0: ethernet { |
| compatible = "atmel,sam-gmac"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 116 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 119 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 120 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "gmac", "q1", "q2", "q3", "q4", "q5"; |
| num-queues = <6>; |
| status = "disabled"; |
| }; |
| |
| gmac0_mdio: mdio { |
| compatible = "atmel,sam-mdio"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| ethernet@e2804000 { |
| compatible = "microchip,sam-ethernet-controller"; |
| reg = <0xe2804000 0x4000>; |
| clocks = <&pmc PMC_TYPE_GCK 52>; |
| |
| gmac1: ethernet { |
| compatible = "atmel,sam-gmac"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, |
| <GIC_SPI 121 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "gmac", "q1"; |
| num-queues = <2>; |
| status = "disabled"; |
| }; |
| |
| gmac1_mdio: mdio { |
| compatible = "atmel,sam-mdio"; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| dma0: dma-controller@e2808000 { |
| compatible = "atmel,sam-xdmac"; |
| reg = <0xe2808000 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #dma-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; |
| clock-names = "dma_clk"; |
| status = "disabled"; |
| }; |
| |
| dma1: dma-controller@e280c000 { |
| compatible = "atmel,sam-xdmac"; |
| reg = <0xe280c000 0x1000>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #dma-cells = <2>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; |
| clock-names = "dma_clk"; |
| status = "disabled"; |
| }; |
| |
| flx8: flexcom@e2818000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe2818000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe2818000 0x800>; |
| status = "disabled"; |
| |
| i2c8: i2c8@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; |
| status = "disabled"; |
| }; |
| |
| usart8: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 46>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flx9: flexcom@e281c000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe281c000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe281c000 0x800>; |
| status = "disabled"; |
| |
| i2c9: i2c9@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; |
| status = "disabled"; |
| }; |
| |
| usart9: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flx10: flexcom@e2820000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe2820000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe2820000 0x800>; |
| status = "disabled"; |
| |
| i2c10: i2c10@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; |
| status = "disabled"; |
| }; |
| |
| usart10: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| flx11: flexcom@e2824000 { |
| compatible = "microchip,sam-flexcom"; |
| reg = <0xe2824000 0x200>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0xe2824000 0x800>; |
| status = "disabled"; |
| |
| i2c11: i2c11@600 { |
| compatible = "atmel,sam-i2c-twi"; |
| reg = <0x600 0x200>; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; |
| status = "disabled"; |
| }; |
| |
| usart11: serial@200 { |
| compatible = "atmel,sam-usart"; |
| reg = <0x200 0x200>; |
| clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| status = "disabled"; |
| }; |
| }; |
| |
| gic: interrupt-controller@e8c11000 { |
| compatible = "arm,gic-v2", "arm,gic"; |
| reg = <0xe8c11000 0x1000>, <0xe8c12000 0x100>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| }; |
| }; |
| }; |
