soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc

# LPC LPC55XXX Series

# Copyright (c) 2019, NXP
# SPDX-License-Identifier: Apache-2.0

choice
	prompt "LPC5500 Series MCU Selection"
	depends on SOC_SERIES_LPC55XXX

config SOC_LPC55S06
	bool "SOC_LPC55S06 M33"
	select CPU_CORTEX_M33
	select CPU_HAS_ARM_SAU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_FPU
	select ARMV8_M_DSP
	select ARM_TRUSTZONE_M
	select CLOCK_CONTROL
	select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
	select HAS_MCUX_RNG

config SOC_LPC55S16
	bool "SOC_LPC55S16 M33"
	select CPU_CORTEX_M33
	select CPU_HAS_ARM_SAU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_FPU
	select ARMV8_M_DSP
	select ARM_TRUSTZONE_M
	select CLOCK_CONTROL
	select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
	select HAS_MCUX_MCAN
	select HAS_MCUX_RNG

config SOC_LPC55S28
	bool "SOC_LPC55S28 M33"
	select CPU_CORTEX_M33
	select CPU_HAS_ARM_MPU
	select CPU_HAS_FPU
	select ARMV8_M_DSP
	select CLOCK_CONTROL
	select HAS_MCUX_IAP
	select HAS_MCUX_LPADC
	select HAS_MCUX_LPC_DMA
	select HAS_MCUX_RNG

config SOC_LPC55S36
	bool "SOC_LPC55S36 M33"
	select CPU_CORTEX_M33
	select CPU_HAS_ARM_SAU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_FPU
	select ARMV8_M_DSP
	select ARM_TRUSTZONE_M
	select CLOCK_CONTROL
	select HAS_MCUX_MCAN
	select HAS_MCUX_PWM

config SOC_LPC55S69_CPU0
	bool "SOC_LPC55S69 M33 [CPU 0]"
	select CPU_CORTEX_M33
	select CPU_HAS_ARM_SAU
	select CPU_HAS_ARM_MPU
	select CPU_HAS_FPU
	select ARMV8_M_DSP
	select ARM_TRUSTZONE_M
	select CLOCK_CONTROL
	select HAS_MCUX_IAP
	select HAS_MCUX_LPADC
	select HAS_MCUX_LPC_DMA
	select HAS_MCUX_USB_LPCIP3511
	select HAS_MCUX_CTIMER
	select HAS_MCUX_SCTIMER
	select HAS_MCUX_RNG

config SOC_LPC55S69_CPU1
	bool "SOC_LPC55S69 M33 [CPU 1]"
	select CPU_CORTEX_M33

endchoice

if SOC_SERIES_LPC55XXX

config SOC_PART_NUMBER_LPC55S06JBD64
	bool

config SOC_PART_NUMBER_LPC55S16JBD64
	bool

config SOC_PART_NUMBER_LPC55S16JBD100
	bool

config SOC_PART_NUMBER_LPC55S28JBD100
	bool

config SOC_PART_NUMBER_LPC55S36JBD100
	bool

config SOC_PART_NUMBER_LPC55S69JBD100
	bool

config SOC_PART_NUMBER_LPC55S69JET98
	bool

config SOC_PART_NUMBER_LPC55XXX
	string
	default "LPC55S06JBD64"  if SOC_PART_NUMBER_LPC55S06JBD64
	default "LPC55S16JBD64" if SOC_PART_NUMBER_LPC55S16JBD64
	default "LPC55S16JBD100" if SOC_PART_NUMBER_LPC55S16JBD100
	default "LPC55S28JBD100" if SOC_PART_NUMBER_LPC55S28JBD100
	default "LPC55S36JBD100" if SOC_PART_NUMBER_LPC55S36JBD100
	default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100
	default "LPC55S69JET98"  if SOC_PART_NUMBER_LPC55S69JET98

	help
	  This string holds the full part number of the SoC. It is a hidden
	  option that you should not set directly. The part number selection
	  choice defines the default value for this string.

config INIT_PLL0
	bool "Initialize PLL0"

config SECOND_CORE_MCUX
	bool "LPC55xxx's second core"
	depends on HAS_MCUX
	help
	  Indicates the second core will be enabled, and the part will run
	  in dual core mode.

# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition

config SECOND_CORE_BOOT_ADDRESS_MCUX
	depends on SECOND_CORE_MCUX
	hex "Address the second core will boot at"
	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))
	help
	  This is the address the second core will boot from.

# Move the LMA for the second core image to be in the flash region of primary
# core, so that JLink flash will load it correctly.
config BUILD_OUTPUT_ADJUST_LMA
	depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1
	default "0x10000000"

config LPC55XXX_SRAM_CLOCKS
	bool "CLock LPC SRAM banks"
	default y
	help
	  SRAM controllers 1,2,3, and 4 are disabled at reset.
	  By default, CMSIS SystemInit will enable the clock to these RAM banks.
	  Disable this Kconfig to leave the ram banks untouched out of reset.

config LPC55XXX_USB_RAM
	bool
	default y
	help
	  Some SoC's in the LPC5500 Series do have a dedicated USB RAM.
	  By default, USB RAM is assumed to be present.
	  Disable this Kconfig in case there is no dedicated USB RAM.

endif # SOC_SERIES_LPC55XXX