tests: arm_irq_vector_table: Use CMSIS NVIC APIs directly

Convert testcases to use the CMSIS NVIC APIs or direct NVIC register
access rather than the internal ones so we can remove them in the future.

Change-Id: I2a5a3eae713e66944cf105e7fffa603b88522681
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

tests/kernel/arm_irq_vector_table/src/main.c

diff --git a/tests/kernel/arm_irq_vector_table/src/main.c b/tests/kernel/arm_irq_vector_table/src/main.c
index 81e1db1..bc6d9fe 100644
--- a/tests/kernel/arm_irq_vector_table/src/main.c
+++ b/tests/kernel/arm_irq_vector_table/src/main.c
@@ -19,6 +19,7 @@
 
 #include <ztest.h>
 #include <arch/cpu.h>
+#include <arch/arm/cortex_m/cmsis.h>
 #include <sections.h>
 
 
@@ -83,9 +84,9 @@
 	for (int ii = 0; ii < 3; ii++) {
 #if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
 		/* the QEMU does not simulate the STIR register: this is a workaround */
-		_NvicIrqPend(ii);
+		NVIC_SetPendingIRQ(ii);
 #else
-		__scs.stir = ii;
+		NVIC->STIR = ii;
 #endif
 	}
 

tests/legacy/kernel/test_arm_irq_vector_table/src/main.c

diff --git a/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c b/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c
index f678c68..0fb41f0 100644
--- a/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c
+++ b/tests/legacy/kernel/test_arm_irq_vector_table/src/main.c
@@ -20,6 +20,7 @@
 #endif
 
 #include <arch/cpu.h>
+#include <arch/arm/cortex_m/cmsis.h>
 #include <tc_util.h>
 #include <sections.h>
 
@@ -96,9 +97,9 @@
 	for (int ii = 0; ii < 3; ii++) {
 #if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
 		/* the QEMU does not simulate the STIR register: this is a workaround */
-		_NvicIrqPend(ii);
+		NVIC_SetPendingIRQ(ii);
 #else
-		__scs.stir = ii;
+		NVIC->STIR = ii;
 #endif
 	}