boards/amd/versalnet_rpu/versalnet_rpu.dts

/*
 * Copyright (c) 2025, Advanced Micro Devices, Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;
#include <arm/xilinx/versalnet_r52.dtsi>

/ {
	chosen {
		zephyr,sram = &sram0;
		zephyr,console = &uart0;
		zephyr,shell-uart = &uart0;
		zephyr,ocm = &ocm;
	};

	sdhci_ref_clk: sdhci-ref-clk {
		compatible = "fixed-clock";
		clock-frequency = <200000000>;
		#clock-cells = <0>;
	};
};

&cpu0 {
	 clock-frequency = <100000000>;
};

&soc {
	sram0: memory@0 {
		compatible = "mmio-sram";
		reg = <0x00000 DT_SIZE_M(2048)>;
	};
};

&ocm {
	status = "okay";
};

&uart1 {
	status = "okay";
	current-speed = <115200>;
	clock-frequency = <100000000>;
};

&uart0 {
	status = "okay";
	current-speed = <115200>;
	clock-frequency = <100000000>;
};

&sdhci0 {
	status = "okay";
	power-delay-ms = <10>;
	clocks = <&sdhci_ref_clk>;
};

&sdhci1 {
	status = "okay";
	clocks = <&sdhci_ref_clk>;
};