boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi

/*
 * Copyright (c) 2024-2025 Renesas Electronics Corporation
 * SPDX-License-Identifier: Apache-2.0
 */

&pinctrl {
	sci9_default: sci9_default {
		group1 {
			/* tx */
			psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 14)>;
			drive-strength = "medium";
		};
		group2 {
			/* rx */
			psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 15)>;
		};
	};

	sci4_default: sci4_default {
		group1 {
			/* sda scl */
			psels = <RA_PSEL(RA_PSEL_SCI_4, 4, 15)>,<RA_PSEL(RA_PSEL_SCI_4, 4, 14)>;
			drive-strength = "medium";
			drive-open-drain;
		};
	};

	spi1_default: spi1_default {
		group1 {
			/* MISO MOSI RSPCK SSL */
			psels = <RA_PSEL(RA_PSEL_SPI, 4, 10)>,
			<RA_PSEL(RA_PSEL_SPI, 4, 11)>,
			<RA_PSEL(RA_PSEL_SPI, 4, 12)>,
			<RA_PSEL(RA_PSEL_SPI, 4, 13)>;
		};
	};

	i3c0_default: i3c0_default {
		group1 {
			/* SCL SDA */
			psels = <RA_PSEL(RA_PSEL_I3C, 4, 0)>,
				<RA_PSEL(RA_PSEL_I3C, 4, 1)>;
		};
	};

	pwm7_default: pwm7_default {
		group1 {
			/* GTIOC7A */
			psels = <RA_PSEL(RA_PSEL_GPT1, 10, 7)>;
		};
		group2 {
			/* GTIOC7B */
			psels = <RA_PSEL(RA_PSEL_GPT1, 10, 6)>;
		};
	};

	canfd0_default: canfd0_default {
		group1 {
			/* CRX0 CTX0 */
			psels = <RA_PSEL(RA_PSEL_CANFD, 4, 2)>,
			<RA_PSEL(RA_PSEL_CANFD, 4, 1)>;
			drive-strength = "high";
		};
	};

	iic1_default: iic1_default {
		group1 {
			/* SCL1 SDA1*/
			psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
			drive-strength = "medium";
		};
	};

	ether_default: ether_default {
		group1 {
			psels = <RA_PSEL(RA_PSEL_ETH_RMII, 4, 1)>, /* ET0_MDC */
					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 2)>, /* ET0_MDIO */
					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 3)>, /* ET0_LINKSTA */
					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 5)>, /* RMII0_TXD_EN_B */
					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 6)>, /* RMII0_TXD1_BR */
					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */
					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */
					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */
					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 3)>, /* RMII0_RXD1_B */
					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 4)>, /* RMII0_RX_ER_B */
					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 5)>; /* RMII0_CRS_DV_B */
			drive-strength = "high";
		};
	};

	usbhs_default: usbhs_default {
		group1 {
			psels = <RA_PSEL(RA_PSEL_USBHS, 11, 1)>; /* USBHS-VBUS */
			drive-strength = "high";
		};
	};

	adc0_default: adc0_default {
		group1 {
			/* input */
			psels = <RA_PSEL(RA_PSEL_ADC, 0, 4)>;
			renesas,analog-enable;
		};
	};

	dac0_default: dac0_default {
		group1 {
			/* output */
			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
			renesas,analog-enable;
		};
	};

	sdram_default: sdram_default{
		group1 {
			/* SDRAM_DQM1 */
			psels = <RA_PSEL(RA_PSEL_BUS, 1, 12)>,
			/* SDRAM_CKE */
			<RA_PSEL(RA_PSEL_BUS, 1, 13)>,
			/* SDRAM_WE */
			<RA_PSEL(RA_PSEL_BUS, 1, 14)>,
			/* SDRAM_CS */
			<RA_PSEL(RA_PSEL_BUS, 1, 15)>,
			/* SDRAM_A0 */
			<RA_PSEL(RA_PSEL_BUS, 3, 0)>,
			/* SDRAM_A1 */
			<RA_PSEL(RA_PSEL_BUS, 3, 1)>,
			/* SDRAM_A2 */
			<RA_PSEL(RA_PSEL_BUS, 3, 2)>,
			/* SDRAM_A3 */
			<RA_PSEL(RA_PSEL_BUS, 3, 3)>,
			/* SDRAM_A4 */
			<RA_PSEL(RA_PSEL_BUS, 3, 4)>,
			/* SDRAM_A5 */
			<RA_PSEL(RA_PSEL_BUS, 3, 5)>,
			/* SDRAM_A6 */
			<RA_PSEL(RA_PSEL_BUS, 3, 6)>,
			/* SDRAM_A7 */
			<RA_PSEL(RA_PSEL_BUS, 3, 7)>,
			/* SDRAM_A8 */
			<RA_PSEL(RA_PSEL_BUS, 3, 8)>,
			/* SDRAM_A9 */
			<RA_PSEL(RA_PSEL_BUS, 3, 9)>,
			/* SDRAM_A10 */
			<RA_PSEL(RA_PSEL_BUS, 3, 10)>,
			/* SDRAM_A11 */
			<RA_PSEL(RA_PSEL_BUS, 3, 11)>,
			/* SDRAM_A12 */
			<RA_PSEL(RA_PSEL_BUS, 3, 12)>,
			/* SDRAM_D0 */
			<RA_PSEL(RA_PSEL_BUS, 6, 1)>,
			/* SDRAM_D1 */
			<RA_PSEL(RA_PSEL_BUS, 6, 2)>,
			/* SDRAM_D2 */
			<RA_PSEL(RA_PSEL_BUS, 6, 3)>,
			/* SDRAM_D3 */
			<RA_PSEL(RA_PSEL_BUS, 6, 4)>,
			/* SDRAM_D4 */
			<RA_PSEL(RA_PSEL_BUS, 6, 5)>,
			/* SDRAM_D5 */
			<RA_PSEL(RA_PSEL_BUS, 6, 6)>,
			/* SDRAM_D6 */
			<RA_PSEL(RA_PSEL_BUS, 6, 7)>,
			/* SDRAM_D8 */
			<RA_PSEL(RA_PSEL_BUS, 6, 9)>,
			/* SDRAM_D9 */
			<RA_PSEL(RA_PSEL_BUS, 6, 10)>,
			/* SDRAM_D10 */
			<RA_PSEL(RA_PSEL_BUS, 6, 11)>,
			/* SDRAM_D11 */
			<RA_PSEL(RA_PSEL_BUS, 6, 12)>,
			/* SDRAM_D12 */
			<RA_PSEL(RA_PSEL_BUS, 6, 13)>,
			/* SDRAM_D13 */
			<RA_PSEL(RA_PSEL_BUS, 6, 14)>,
			/* SDRAM_D14 */
			<RA_PSEL(RA_PSEL_BUS, 6, 15)>,
			/* SDRAM_BA0 */
			<RA_PSEL(RA_PSEL_BUS, 9, 5)>,
			/* SDRAM_BA1 */
			<RA_PSEL(RA_PSEL_BUS, 9, 6)>,
			/* SDRAM_RAS */
			<RA_PSEL(RA_PSEL_BUS, 9, 8)>,
			/* SDRAM_CAS */
			<RA_PSEL(RA_PSEL_BUS, 9, 9)>,
			/* SDRAM_SDCLK */
			<RA_PSEL(RA_PSEL_BUS, 10, 9)>;
			drive-strength = "high";
		};

		group2 {
			/* SDRAM_SDCLK */
			psels = <RA_PSEL(RA_PSEL_BUS, 10, 9)>;
			drive-strength = "highspeed-high";
		};

		group3 {
			/* SDRAM_D7 */
			psels = <RA_PSEL(RA_PSEL_BUS, 10, 0)>,
			/* SDRAM_D15 */
			<RA_PSEL(RA_PSEL_BUS, 10, 8)>,
			/* SDRAM_DQM0 */
			<RA_PSEL(RA_PSEL_BUS, 10, 10)>;
		};
	};

	/* NOTE: pins conflict with ether_default */
	sdhc1_default: sdhc1_default {
		group1 {
			psels = <RA_PSEL(RA_PSEL_SDHI, 4, 6)>, /* SDCD */
			<RA_PSEL(RA_PSEL_SDHI, 4, 1)>, /* SDCMD */
			<RA_PSEL(RA_PSEL_SDHI, 4, 2)>, /* SDDATA0 */
			<RA_PSEL(RA_PSEL_SDHI, 4, 3)>, /* SDDATA1 */
			<RA_PSEL(RA_PSEL_SDHI, 4, 4)>, /* SDDATA2 */
			<RA_PSEL(RA_PSEL_SDHI, 4, 5)>, /* SDDATA3 */
			<RA_PSEL(RA_PSEL_SDHI, 7, 0)>; /* SDWP */
			drive-strength = "high";
		};
		group2 {
			psels = <RA_PSEL(RA_PSEL_SDHI, 4, 0)>; /* SDCLK */
			drive-strength = "highspeed-high";
		};
	};

	usbfs_default: usbfs_default {
		group1 {
			/* USBP USBN */
			psels = <RA_PSEL(RA_PSEL_USBFS, 8, 15)>,
				<RA_PSEL(RA_PSEL_USBFS, 8, 14)>,
				<RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
			drive-strength = "high";
		};
	};

	/omit-if-no-ref/ acmphs_ivref0: acmphs_ivref0 {
		group1 {
			/* IVREF0 */
			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 1)>;
			renesas,analog-enable;
		};
	};

	/omit-if-no-ref/ acmphs_ivref1: acmphs_ivref1 {
		group1 {
			/* IVREF1 */
			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 3)>;
			renesas,analog-enable;
		};
	};

	/omit-if-no-ref/ acmphs0_ivcmp0: acmphs0_ivcmp0 {
		group1 {
			/* CH0 IVCMP0 */
			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 10)>;
			renesas,analog-enable;
		};
	};

	/omit-if-no-ref/ acmphs0_ivcmp2: acmphs0_ivcmp2 {
		group1 {
			/* CH0 IVCMP2 */
			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 4)>;
			renesas,analog-enable;
		};
	};

	/omit-if-no-ref/ acmphs0_ivcmp3: acmphs0_ivcmp3 {
		group1 {
			/* CH0 IVCMP3 */
			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 6)>;
			renesas,analog-enable;
		};
	};

	/omit-if-no-ref/ acmphs_vcout: acmphs_vcout {
		group1 {
			/* VCOUT */
			psels = <RA_PSEL(RA_PSEL_ACMPHS_VCOUT, 2, 8)>;
		};
	};

	ospi0_default: ospi0_default {
		group1 {
			/* sclk dqs sio0-7 */
			psels = <RA_PSEL(RA_PSEL_OSPI, 8, 8)>, <RA_PSEL(RA_PSEL_OSPI, 8, 1)>,
			<RA_PSEL(RA_PSEL_OSPI, 1, 0)>, <RA_PSEL(RA_PSEL_OSPI, 8, 3)>,
			<RA_PSEL(RA_PSEL_OSPI, 1, 3)>, <RA_PSEL(RA_PSEL_OSPI, 1, 1)>,
			<RA_PSEL(RA_PSEL_OSPI, 1, 2)>, <RA_PSEL(RA_PSEL_OSPI, 8, 0)>,
			<RA_PSEL(RA_PSEL_OSPI, 8, 2)>, <RA_PSEL(RA_PSEL_OSPI, 8, 4)>;
			drive-strength = "highspeed-high";
		};

		group2 {
			/* cs1 rst ecsint1 */
			psels = <RA_PSEL(RA_PSEL_OSPI, 1, 4)>, <RA_PSEL(RA_PSEL_OSPI, 1, 6)>,
			<RA_PSEL(RA_PSEL_OSPI, 1, 5)>;
			drive-strength = "high";
		};
	};
};