soc/intel/intel_adsp/ace/Kconfig

# Copyright (c) 2022-2024 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_INTEL_ADSP_ACE
	select XTENSA
	select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang"))
	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
	select ARCH_HAS_COHERENCE
	select SCHED_IPI_SUPPORTED
	select ARCH_HAS_CUSTOM_CPU_IDLE
	select DW_ICTL_ACE
	select SOC_HAS_RUNTIME_NUM_CPUS
	select HAS_PM
	select XTENSA_CPU_HAS_HIFI3
	select XTENSA_CPU_HAS_HIFI4
	select ARCH_HAS_RESERVED_PAGE_FRAMES if MMU
	select ARCH_HAS_GDBSTUB

config SOC_INTEL_COMM_WIDGET
	bool "Intel Communication Widget driver"
	default y
	depends on DT_HAS_INTEL_ADSP_COMMUNICATION_WIDGET_ENABLED
	help
	  Select this to enable Intel Communication Widget driver.
	  DSP Communication Widget is a device for generic sideband message transmit/receive.

config SRAM_RETENTION_MODE
	bool "SRAM retention mode during initialization"
	default y
	help
	  When this option is enabled, the SRAM retention mode will be
	  activated during the firmware boot-up process. If disabled,
	  the retention mode will not be activated.

config SOC_SERIES_INTEL_ADSP_ACE_CUSTOM_MORE_SPIN_RELAX_NOPS
	bool "Use Intel Audio DSP specific arch_spin_relax() with more NOPs"
	depends on !XTENSA_MORE_SPIN_RELAX_NOPS
	default y if SMP && MP_MAX_NUM_CPUS > 1
	help
	  Add some NOPs after failure to lock a spinlock. This gives
	  the bus extra time to synchronize the RCW transaction
	  among CPUs.

config SOC_SERIES_INTEL_ADSP_ACE_NUM_SPIN_RELAX_NOPS
	int "Number of NOPs to be used in Intel Audio DSP specific arch_spin_relax()"
	depends on SOC_SERIES_INTEL_ADSP_ACE_CUSTOM_MORE_SPIN_RELAX_NOPS
	default 32 if MP_MAX_NUM_CPUS = 1
	default 64 if MP_MAX_NUM_CPUS = 2
	default 96 if MP_MAX_NUM_CPUS = 3
	default 128 if MP_MAX_NUM_CPUS = 4
	default 160 if MP_MAX_NUM_CPUS = 5
	help
	  Specify the number of NOPs in Intel Audio DSP specific
	  arch_spin_relax().