blob: 9b35bbe9f7be0c96089508d245ae7cc1d0d4f398 [file] [log] [blame]
/*
* Copyright (c) 2021 Wouter Cappelle <wouter.cappelle@crodeon.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/l0/stm32l010.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(20)>;
};
soc {
eeprom: eeprom@8080000{
reg = <0x08080000 512>;
};
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
};
};
timers22: timers@40011400 {
compatible = "st,stm32-timers";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
resets = <&rctl STM32_RESET(APB2, 5U)>;
interrupts = <22 0>;
interrupt-names = "global";
status = "disabled";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
#pwm-cells = <3>;
};
};
};
};