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# Copyright 2022-2024 NXP
# SPDX-License-Identifier: Apache-2.0
description: |
Kinetis pinctrl node. This node will define pin configurations in pin groups,
and has the 'pinctrl' node identifier in the SOC's devicetree. Each group
within the pin configuration defines the pin configuration for a peripheral,
and each numbered subgroup in the pin group defines all the pins for that
peripheral with the same configuration properties. The 'pins' property in
a group selects the pins to be configured, and the remaining properties set
configuration values for those pins. Here is an example group for UART0 pins:
uart0_default: uart0_default {
group0 {
pins = <UART0_RX_PTB16
UART0_TX_PTB17>;
drive-strength = "low";
slew-rate = "fast";
};
};
If only the required properties are supplied, the pin configuration register
will be assigned the following values:
PCR_PS=0,
PCR_PE=0,
PCR_ODE=0,
PCR_SRE=<slew-rate selection>,
PCR_DSE=<drive-strength selection>,
PCR_PFE=0
compatible: "nxp,kinetis-pinctrl"
include: base.yaml
child-binding:
description: Kinetis pin controller pin group
child-binding:
description: |
Kinetis pin controller pin configuration node
include:
- name: pincfg-node.yaml
property-allowlist:
- drive-open-drain
- bias-pull-up
- bias-pull-down
- input-enable
properties:
pinmux:
required: true
type: array
description: |
Pin mux selections for this group. See the soc level pinctrl DTSI file
in NXP's HAL for a defined list of these options
drive-strength:
required: true
type: string
enum:
- "low"
- "high"
description: |
Pin output drive strength. Sets the DSE field in the PORTx_PCRn register.
0 DSE_0- low drive strength when pin is configured as output
1 DSE_1- high drive strength when pin is configured as output
slew-rate:
type: string
enum:
- "fast"
- "slow"
description: |
Pin output slew rate. Sets the SRE field in the PORTx_PCRn register.
0 SRE_0_fast- fast slew rate when pin is configured as output
1 SRE_1_slow- slow slew rate when pin is configured as output
nxp,passive-filter:
type: boolean
description: |
Enable passive filter on pin. Sets the PFE field in the PORTx_PCRn register.