| # Copyright (c) 2021 Andes Technology Corporation |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config SOC_SERIES_ANDES_AE350 |
| select RISCV |
| select RISCV_PRIVILEGED |
| select RISCV_HAS_PLIC |
| |
| config SOC_ANDES_AE350 |
| select ATOMIC_OPERATIONS_BUILTIN |
| select INCLUDE_RESET_VECTOR |
| select RISCV_ISA_EXT_M |
| select RISCV_ISA_EXT_A |
| select RISCV_ISA_EXT_C |
| select CPU_HAS_DCACHE |
| select CPU_HAS_ICACHE |
| select RISCV_PMP |
| |
| if SOC_SERIES_ANDES_AE350 |
| |
| choice |
| prompt "Base CPU ISA options" |
| default RV32I_CPU |
| |
| config RV32I_CPU |
| bool "RISCV32 CPU ISA" |
| select RISCV_ISA_RV32I |
| select RISCV_ISA_EXT_ZICSR |
| select RISCV_ISA_EXT_ZIFENCEI |
| |
| config RV32E_CPU |
| bool "RISCV32E CPU ISA" |
| select RISCV_ISA_RV32E |
| select RISCV_ISA_EXT_ZICSR |
| select RISCV_ISA_EXT_ZIFENCEI |
| |
| config RV64I_CPU |
| bool "RISCV64 CPU ISA" |
| select RISCV_ISA_RV64I |
| select RISCV_ISA_EXT_ZICSR |
| select RISCV_ISA_EXT_ZIFENCEI |
| select 64BIT |
| |
| endchoice |
| |
| choice |
| prompt "FPU options" |
| default NO_FPU |
| |
| config NO_FPU |
| bool "No FPU" |
| |
| config SINGLE_PRECISION_FPU |
| bool "Single precision FPU" |
| select CPU_HAS_FPU |
| |
| config DOUBLE_PRECISION_FPU |
| bool "Double precision FPU" |
| select CPU_HAS_FPU_DOUBLE_PRECISION |
| |
| endchoice |
| |
| config SOC_ANDES_V5_HWDSP |
| bool "AndeStar V5 DSP ISA" |
| select RISCV_SOC_CONTEXT_SAVE |
| depends on !RISCV_GENERIC_TOOLCHAIN |
| help |
| This option enables the AndeStar v5 hardware DSP, in order to |
| support using the DSP instructions. |
| |
| config SOC_ANDES_V5_PFT |
| bool "Andes V5 PowerBrake extension" |
| default y |
| select RISCV_SOC_CONTEXT_SAVE |
| help |
| The PowerBrake extension throttles performance by reducing instruction |
| executing rate. |
| |
| config SOC_ANDES_V5_EXECIT |
| bool "Andes V5 EXEC.IT extension" |
| depends on RISCV_ISA_EXT_C |
| depends on !RISCV_GENERIC_TOOLCHAIN |
| depends on !LINKER_USE_NO_RELAX |
| help |
| The EXEC.IT extension (Execution on Instruction Table) generate |
| a look-up table and replaces suitable 32-bit instructions with |
| the 16-bit "exec.it <INDEX>". |
| |
| config SOC_ANDES_V5_PMA |
| bool "Andes V5 Physical Memory Attribute (PMA)" |
| select ARCH_HAS_NOCACHE_MEMORY_SUPPORT |
| help |
| This option enables the Andes V5 PMA, in order to support SW to |
| configure physical memory attribute by PMA CSRs. The address |
| matching of Andes V5 PMA is like RISC-V PMP NAPOT mode |
| (power-of-two alignment). |
| |
| config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE |
| int |
| depends on SOC_ANDES_V5_PMA |
| default 4096 |
| help |
| Minimum size (and alignment) of an PMA region. Use this symbol |
| to guarantee minimum size and alignment of PMA regions. |
| |
| # Workaround for not being able to have commas in macro arguments |
| DT_ANDESTECH_L2C := andestech,l2c |
| |
| config SOC_ANDES_V5_L2C |
| bool |
| default $(dt_compat_enabled,$(DT_ANDESTECH_L2C)) |
| |
| config SOC_ANDES_V5_IOCP |
| bool "Andes V5 I/O Coherence Port (IOCP)" |
| depends on SOC_ANDES_V5_L2C |
| depends on DCACHE |
| help |
| Support Andes V5 I/O Coherence Port to handle cache coherency |
| between cache and external non-caching master, such as DMA |
| controller. |
| |
| endif # SOC_SERIES_ANDES_AE350 |
