| commit | 14e9e7a814ef510e4d72521bb7eb8cab0f3ebbea | [log] [tgz] |
|---|---|---|
| author | Tim Lin <tim2.lin@ite.corp-partner.google.com> | Tue Apr 20 16:40:13 2021 +0800 |
| committer | Anas Nashif <anas.nashif@intel.com> | Fri Apr 23 07:03:10 2021 -0400 |
| tree | dc153b1f29d8517894e8ab5a152908b750612af3 | |
| parent | 256ca5547645843ede6f4c7c5c88f30d79b75bcf [diff] |
soc: riscv/riscv-ite: chip_chipregs: add chip register address Add register address including external timer and watchdog(ETWD), general control(GCTRL), serial peripheral interface(SPI). Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>