tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_csi_ahb_2_100.overlay

/*
 * Copyright (c) 2021 Linaro Limited
 * Copyright (c) 2023 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Warning: This overlay performs configuration from clean sheet.
 * It is assumed that it is applied after clear_clocks.overlay file.
 */

&clk_csi {
	status = "okay";
};

&pll {
	div-m = <1>;
	mul-n = <100>;
	div-p = <2>;
	div-q = <2>;
	div-r = <2>;
	clocks = <&clk_csi>;
	status = "okay";
};

&rcc {
	clocks = <&pll>;
	ahb-prescaler = <2>;              /* Use AHB prescaler to reduce HCLK */
	clock-frequency = <DT_FREQ_M(100)>;
	apb1-prescaler = <1>;
	apb2-prescaler = <1>;
	apb3-prescaler = <1>;
};