| /* |
| * Copyright (c) 2019 Linaro Limited |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <dt-bindings/clock/stm32_clock.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/i2c/i2c.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m4f"; |
| reg = <0>; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| }; |
| |
| soc { |
| flash-controller@58004000 { |
| compatible = "st,stm32wb-flash-controller"; |
| label = "FLASH_CTRL"; |
| reg = <0x58004000 0x400>; |
| interrupts = <4 0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "soc-nv-flash"; |
| label = "FLASH_STM32"; |
| |
| write-block-size = <8>; |
| erase-block-size = <4096>; |
| }; |
| }; |
| |
| rcc: rcc@58000000 { |
| compatible = "st,stm32-rcc"; |
| #clock-cells = <2>; |
| reg = <0x58000000 0x400>; |
| label = "STM32_CLK_RCC"; |
| }; |
| |
| pinctrl: pin-controller@48000000 { |
| compatible = "st,stm32-pinmux"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x48000000 0x2000>; |
| |
| gpioa: gpio@48000000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>; |
| label = "GPIOA"; |
| }; |
| |
| gpiob: gpio@48000400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>; |
| label = "GPIOB"; |
| }; |
| |
| gpioc: gpio@48000800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>; |
| label = "GPIOC"; |
| }; |
| |
| gpiod: gpio@48000c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; |
| label = "GPIOD"; |
| }; |
| |
| gpioe: gpio@48001000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48001000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; |
| label = "GPIOE"; |
| }; |
| |
| gpioh: gpio@48001c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48001c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>; |
| label = "GPIOH"; |
| }; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; |
| label = "WWDG"; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; |
| interrupts = <36 0>; |
| status = "disabled"; |
| label = "UART_1"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; |
| interrupts = <30 0>, <31 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| label= "I2C_1"; |
| }; |
| |
| i2c3: i2c@40005c00 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>; |
| interrupts = <32 0>, <33 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| label= "I2C_3"; |
| }; |
| |
| rtc: rtc@40002800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x40002800 0x400>; |
| interrupts = <41 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>; |
| prescaler = <32768>; |
| status = "disabled"; |
| label = "RTC_0"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi-fifo"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| interrupts = <34 5>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; |
| status = "disabled"; |
| label = "SPI_1"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32-spi-fifo"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| interrupts = <35 5>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; |
| status = "disabled"; |
| label = "SPI_2"; |
| }; |
| |
| lpuart1: serial@40008000 { |
| compatible = "st,stm32-lpuart", "st,stm32-uart"; |
| reg = <0x40008000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| label = "LPUART_1"; |
| }; |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>; |
| status = "disabled"; |
| label = "TIMERS_1"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_1"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>; |
| status = "disabled"; |
| label = "TIMERS_2"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <0>; |
| label = "PWM_2"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers16: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>; |
| status = "disabled"; |
| label = "TIMERS_16"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_16"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| timers17: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>; |
| status = "disabled"; |
| label = "TIMERS_17"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| st,prescaler = <10000>; |
| label = "PWM_17"; |
| #pwm-cells = <2>; |
| }; |
| }; |
| |
| adc1: adc@50040000 { |
| compatible = "st,stm32-adc"; |
| reg = <0x50040000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| label = "ADC_1"; |
| #io-channel-cells = <1>; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| label = "IWDG"; |
| }; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
