dts/xtensa/espressif/esp32.dtsi

/*
 * Copyright (c) 2019 Intel Corporation.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#include <xtensa/xtensa.dtsi>
#include <dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "cadence,tensilica-xtensa-lx6";
			reg = <0>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "cadence,tensilica-xtensa-lx6";
			reg = <1>;
		};

	};

	sram0: memory@3ffb0000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x3FFB0000 0x50000>;
	};

	soc {
		uart0: uart@3ff40000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3ff40000 0x400>;
			/* interrupts = <12>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */
			label = "UART_0";
			status = "disabled";
		};

		uart1: uart@3ff50000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3ff50000 0x400>;
			/* interrupts = <17>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */
			label = "UART_1";
			status = "disabled";
		};

		uart2: uart@3ff6e000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3ff6E000 0x400>;
			/* interrupts = <18>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */
			label = "UART_2";
			status = "disabled";
		};

		gpio0: gpio@3ff44000 {
			compatible = "espressif,esp32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x3ff44000 0x800>;
			label = "GPIO_0";
		};

		gpio1: gpio@3ff44800 {
			compatible = "espressif,esp32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x3ff44800 0x800>;
			label = "GPIO_1";
		};
	};
};