blob: a03906f29a4be83098dd06f5df39e1a0be1b355e [file] [log] [blame]
/*
* Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <arm64/armv8-r.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-r82";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-r82";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-r82";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-r82";
reg = <3>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 14 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 11 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>,
<GIC_PPI 10 IRQ_TYPE_LEVEL
IRQ_DEFAULT_PRIORITY>;
};
uartclk: apb-pclk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
soc {
interrupt-parent = <&gic>;
gic: interrupt-controller@af000000 {
compatible = "arm,gic";
reg = <0xaf000000 0x10000>,
<0xaf100000 0x200000>;
interrupt-controller;
#interrupt-cells = <4>;
status = "okay";
};
uart0: uart@9c090000 {
compatible = "arm,pl011";
reg = <0x9c090000 0x10000>;
status = "disabled";
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_5";
clocks = <&uartclk>;
};
uart1: uart@9c0a0000 {
compatible = "arm,pl011";
reg = <0x9c0a0000 0x10000>;
status = "disabled";
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_6";
clocks = <&uartclk>;
};
uart2: uart@9c0b0000 {
compatible = "arm,pl011";
reg = <0x9c0b0000 0x10000>;
status = "disabled";
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_7";
clocks = <&uartclk>;
};
uart3: uart@9c0c0000 {
compatible = "arm,pl011";
reg = <0x9c0c0000 0x10000>;
status = "disabled";
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "irq_8";
clocks = <&uartclk>;
};
eth: ethernet@9a000000 {
compatible = "smsc,lan91c111";
reg = <0x9a000000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
phy: phy {
compatible = "ethernet-phy";
status = "disabled";
address = <0>;
mdio = <&mdio>;
};
mdio: mdio {
compatible = "smsc,lan91c111-mdio";
status = "disabled";
};
};
};
};