| /* |
| * Copyright (c) 2020 Lemonbeat GmbH |
| * Copyright 2024 NXP |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv8-m.dtsi> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> |
| #include <mem.h> |
| #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h> |
| |
| / { |
| aliases { |
| watchdog0 = &wwdt0; |
| }; |
| |
| chosen { |
| zephyr,flash-controller = &iap; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-m33f"; |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv8m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| }; |
| }; |
| }; |
| }; |
| |
| &sram { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| sramx: memory@4000000 { |
| compatible = "mmio-sram"; |
| reg = <0x4000000 DT_SIZE_K(32)>; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| reg = <0x20000000 DT_SIZE_K(64)>; |
| }; |
| |
| sram1: memory@20010000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x20010000 DT_SIZE_K(64)>; |
| zephyr,memory-region = "SRAM1"; |
| }; |
| |
| sram2: memory@20020000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x20020000 DT_SIZE_K(64)>; |
| zephyr,memory-region = "SRAM2"; |
| }; |
| |
| sram4: memory@20040000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x20040000 DT_SIZE_K(16)>; |
| zephyr,memory-region = "SRAM4"; |
| }; |
| |
| usb_sram: memory@40100000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x40100000 DT_SIZE_K(16)>; |
| zephyr,memory-region = "USB_SRAM"; |
| zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; |
| }; |
| }; |
| |
| &peripheral { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| syscon: syscon@0 { |
| compatible = "nxp,lpc-syscon"; |
| reg = <0x0 0x1000>; |
| #clock-cells = <1>; |
| reset: reset { |
| compatible = "nxp,lpc-syscon-reset"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| iap: flash-controller@34000 { |
| compatible = "nxp,iap-fmc55"; |
| reg = <0x34000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| status = "disabled"; |
| |
| flash0: flash@0 { |
| compatible = "soc-nv-flash"; |
| reg = <0x0 DT_SIZE_K(512)>; |
| erase-block-size = <512>; |
| write-block-size = <512>; |
| }; |
| |
| uuid: flash@9fc70 { |
| compatible = "nxp,lpc-uid"; |
| reg = <0x9fc70 0x10>; |
| }; |
| |
| boot_rom: flash@3000000 { |
| compatible = "soc-nv-flash"; |
| reg = <0x3000000 DT_SIZE_K(128)>; |
| }; |
| }; |
| |
| iocon: iocon@1000 { |
| compatible = "nxp,lpc-iocon"; |
| reg = <0x1000 0x100>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x1000 0x100>; |
| pinctrl: pinctrl { |
| compatible = "nxp,lpc-iocon-pinctrl"; |
| }; |
| }; |
| |
| gpio: gpio@8c000 { |
| compatible = "nxp,lpc-gpio"; |
| reg = <0x8c000 0x2488>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| gpio0: gpio@0 { |
| compatible = "nxp,lpc-gpio-port"; |
| int-source = "pint"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0>; |
| }; |
| |
| gpio1: gpio@1 { |
| compatible = "nxp,lpc-gpio-port"; |
| int-source = "pint"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <1>; |
| }; |
| }; |
| |
| pint: pint@4000 { |
| compatible = "nxp,pint"; |
| reg = <0x4000 0x1000>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <0>; |
| interrupts = <4 2>, <5 2>, <6 2>, <7 2>, |
| <32 2>, <33 2>, <34 2>, <35 2>; |
| num-lines = <8>; |
| num-inputs = <64>; |
| }; |
| |
| dma0: dma-controller@82000 { |
| compatible = "nxp,lpc-dma"; |
| reg = <0x82000 0x1000>; |
| interrupts = <1 0>; |
| dma-channels = <23>; |
| status = "disabled"; |
| #dma-cells = <1>; |
| }; |
| |
| dma1: dma-controller@a7000 { |
| compatible = "nxp,lpc-dma"; |
| reg = <0xa7000 0x1000>; |
| interrupts = <58 0>; |
| dma-channels = <10>; |
| status = "disabled"; |
| #dma-cells = <1>; |
| }; |
| |
| flexcomm0: flexcomm@86000 { |
| compatible = "nxp,lpc-flexcomm"; |
| reg = <0x86000 0x1000>; |
| interrupts = <14 0>; |
| clocks = <&syscon MCUX_FLEXCOMM0_CLK>; |
| resets = <&reset NXP_SYSCON_RESET(1, 11)>; |
| status = "disabled"; |
| }; |
| |
| flexcomm1: flexcomm@87000 { |
| compatible = "nxp,lpc-flexcomm"; |
| reg = <0x87000 0x1000>; |
| interrupts = <15 0>; |
| clocks = <&syscon MCUX_FLEXCOMM1_CLK>; |
| resets = <&reset NXP_SYSCON_RESET(1, 12)>; |
| status = "disabled"; |
| }; |
| |
| flexcomm2: flexcomm@88000 { |
| compatible = "nxp,lpc-flexcomm"; |
| reg = <0x88000 0x1000>; |
| interrupts = <16 0>; |
| clocks = <&syscon MCUX_FLEXCOMM2_CLK>; |
| resets = <&reset NXP_SYSCON_RESET(1, 13)>; |
| status = "disabled"; |
| }; |
| |
| flexcomm3: flexcomm@89000 { |
| compatible = "nxp,lpc-flexcomm"; |
| reg = <0x89000 0x1000>; |
| interrupts = <17 0>; |
| clocks = <&syscon MCUX_FLEXCOMM3_CLK>; |
| resets = <&reset NXP_SYSCON_RESET(1, 14)>; |
| status = "disabled"; |
| }; |
| |
| flexcomm4: flexcomm@8a000 { |
| compatible = "nxp,lpc-flexcomm"; |
| reg = <0x8a000 0x1000>; |
| interrupts = <18 0>; |
| clocks = <&syscon MCUX_FLEXCOMM4_CLK>; |
| resets = <&reset NXP_SYSCON_RESET(1, 15)>; |
| status = "disabled"; |
| }; |
| |
| flexcomm5: flexcomm@96000 { |
| compatible = "nxp,lpc-flexcomm"; |
| reg = <0x96000 0x1000>; |
| interrupts = <19 0>; |
| clocks = <&syscon MCUX_FLEXCOMM5_CLK>; |
| resets = <&reset NXP_SYSCON_RESET(1, 16)>; |
| status = "disabled"; |
| }; |
| |
| flexcomm6: flexcomm@97000 { |
| compatible = "nxp,lpc-flexcomm"; |
| reg = <0x97000 0x1000>; |
| interrupts = <20 0>; |
| clocks = <&syscon MCUX_FLEXCOMM6_CLK>; |
| resets = <&reset NXP_SYSCON_RESET(1, 17)>; |
| status = "disabled"; |
| }; |
| |
| flexcomm7: flexcomm@98000 { |
| compatible = "nxp,lpc-flexcomm"; |
| reg = <0x98000 0x1000>; |
| interrupts = <21 0>; |
| clocks = <&syscon MCUX_FLEXCOMM7_CLK>; |
| resets = <&reset NXP_SYSCON_RESET(1, 18)>; |
| status = "disabled"; |
| }; |
| |
| sc_timer: pwm@85000 { |
| compatible = "nxp,sctimer-pwm"; |
| reg = <0x85000 0x1000>; |
| interrupts = <12 0>; |
| status = "disabled"; |
| clocks = <&syscon MCUX_SCTIMER_CLK>; |
| prescaler = <2>; |
| #pwm-cells = <3>; |
| }; |
| |
| hs_lspi: spi@9f000 { |
| compatible = "nxp,lpc-spi"; |
| /* Enabling cs-gpios below will allow using GPIO CS, |
| rather than Flexcomm SS */ |
| /* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>, |
| <&gpio1 1 GPIO_ACTIVE_LOW>, |
| <&gpio1 12 GPIO_ACTIVE_LOW>, |
| <&gpio1 26 GPIO_ACTIVE_LOW>; */ |
| reg = <0x9f000 0x1000>; |
| interrupts = <59 0>; |
| clocks = <&syscon MCUX_HS_SPI_CLK>; |
| resets = <&reset NXP_SYSCON_RESET(2, 28)>; |
| status = "disabled"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| rng: rng@3a000 { |
| compatible = "nxp,lpc-rng"; |
| reg = <0x3a000 0x1000>; |
| status = "okay"; |
| }; |
| |
| wwdt0: watchdog@c000 { |
| compatible = "nxp,lpc-wwdt"; |
| reg = <0xc000 0x1000>; |
| interrupts = <0 0>; |
| status = "disabled"; |
| clk-divider = <1>; |
| }; |
| |
| adc0: adc@a0000 { |
| compatible = "nxp,lpc-lpadc"; |
| reg = <0xa0000 0x1000>; |
| interrupts = <22 0>; |
| status = "disabled"; |
| clk-divider = <8>; |
| clk-source = <0>; |
| voltage-ref= <1>; |
| calibration-average = <128>; |
| power-level = <0>; |
| offset-value-a = <10>; |
| offset-value-b = <10>; |
| #io-channel-cells = <1>; |
| clocks = <&syscon MCUX_LPADC1_CLK>; |
| }; |
| |
| usbhs: usbhs@94000 { |
| compatible = "nxp,lpcip3511"; |
| reg = <0x94000 0x1000>; |
| interrupts = <47 1>; |
| num-bidir-endpoints = <6>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <3>; |
| }; |
