dts/arm/st/f4/stm32f412.dtsi

/*
 * Copyright (c) 2017 Florian Vaussard, HEIG-VD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/f4/stm32f410.dtsi>

/delete-node/ &dac1;
/delete-node/ &rng;

/ {
	clocks {
		plli2s: plli2s {
			#clock-cells = <0>;
			compatible = "st,stm32f412-plli2s-clock";
			status = "disabled";
		};
	};

	soc {
		compatible = "st,stm32f412", "st,stm32f4", "simple-bus";

		pinctrl: pin-controller@40020000 {
			reg = <0x40020000 0x1c00>;

			gpiof: gpio@40021400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40021400 0x400>;
				clocks = <&rcc STM32_CLOCK(AHB1, 5U)>;
			};

			gpiog: gpio@40021800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40021800 0x400>;
				clocks = <&rcc STM32_CLOCK(AHB1, 6U)>;
			};
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 18U)>;
			resets = <&rctl STM32_RESET(APB1, 18U)>;
			interrupts = <39 0>;
			status = "disabled";
		};

		spi3: spi@40003c00 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003c00 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
			interrupts = <51 5>;
			status = "disabled";
		};

		spi4: spi@40013400 {
			compatible = "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
			interrupts = <84 5>;
			status = "disabled";
		};

		i2s4: i2s@40013400 {
			compatible = "st,stm32-i2s";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
			interrupts = <84 5>;
			dmas = <&dma2 1 4 0x400 0x3
				&dma2 0 4 0x400 0x3>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		timers7: timers@40001400 {
			compatible = "st,stm32-timers";
			reg = <0x40001400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 5U)>;
			resets = <&rctl STM32_RESET(APB1, 5U)>;
			interrupts = <55 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers8: timers@40010400 {
			compatible = "st,stm32-timers";
			reg = <0x40010400 0x400>;
			clocks = <&rcc STM32_CLOCK(APB2, 1U)>;
			resets = <&rctl STM32_RESET(APB2, 1U)>;
			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
			interrupt-names = "brk", "up", "trgcom", "cc";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			qdec {
				compatible = "st,stm32-qdec";
				status = "disabled";
				st,input-filter-level = <NO_FILTER>;
			};
		};

		timers12: timers@40001800 {
			compatible = "st,stm32-timers";
			reg = <0x40001800 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 6U)>;
			resets = <&rctl STM32_RESET(APB1, 6U)>;
			interrupts = <43 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers13: timers@40001c00 {
			compatible = "st,stm32-timers";
			reg = <0x40001c00 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 7U)>;
			resets = <&rctl STM32_RESET(APB1, 7U)>;
			interrupts = <44 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		timers14: timers@40002000 {
			compatible = "st,stm32-timers";
			reg = <0x40002000 0x400>;
			clocks = <&rcc STM32_CLOCK(APB1, 8U)>;
			resets = <&rctl STM32_RESET(APB1, 8U)>;
			interrupts = <45 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};
		};

		rng: rng@50060800 {
			compatible = "st,stm32-rng";
			reg = <0x50060800 0x400>;
			interrupts = <80 0>;
			clocks = <&rcc STM32_CLOCK(AHB2, 6U)>;
			status = "disabled";
		};

		usbotg_fs: usb@50000000 {
			num-bidir-endpoints = <6>;
		};

		sdmmc1: sdmmc@40012c00 {
			clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
				 <&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>;
		};

		quadspi: quadspi@a0001000 {
			compatible = "st,stm32-qspi";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			reg = <0xa0001000 0x400>;
			interrupts = <92 0>;
			clocks = <&rcc STM32_CLOCK(AHB3, 1U)>;
			status = "disabled";
		};

		can1: can@40006400 {
			compatible = "st,stm32-bxcan";
			reg = <0x40006400 0x400>;
			interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
			interrupt-names = "TX", "RX0", "RX1", "SCE";
			clocks = <&rcc STM32_CLOCK(APB1, 25U)>;
			status = "disabled";
		};

		can2: can@40006800 {
			compatible = "st,stm32-bxcan";
			reg = <0x40006800 0x400>;
			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
			interrupt-names = "TX", "RX0", "RX1", "SCE";
			/* also enabling clock for can1 (master instance) */
			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
			master-can-reg = <0x40006400>;
			status = "disabled";
		};
	};
};