| /* |
| * Copyright (c) 2024 STMicroelectronics |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <arm/armv7-m.dtsi> |
| #include <zephyr/dt-bindings/clock/stm32h7rs_clock.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/pwm/stm32_pwm.h> |
| #include <zephyr/dt-bindings/reset/stm32h7rs_reset.h> |
| #include <zephyr/dt-bindings/adc/stm32h7_adc.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/memory-attr/memory-attr.h> |
| #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h> |
| #include <freq.h> |
| |
| /* |
| * STM32H7RS line contains has many common peripherals with STM32H7. |
| */ |
| |
| / { |
| chosen { |
| zephyr,entropy = &rng; |
| zephyr,flash-controller = &flash; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m7"; |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv7m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| }; |
| }; |
| }; |
| |
| /* System data RAM accessible over AXI bus: AXI SRAM1 in CD domain */ |
| sram0: memory@24000000 { |
| compatible = "mmio-sram"; |
| reg = <0x24000000 DT_SIZE_K(128)>; |
| }; |
| |
| /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */ |
| sram1: memory@30000000 { |
| reg = <0x30000000 DT_SIZE_K(16)>; |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| zephyr,memory-region = "SRAM1"; |
| }; |
| |
| /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */ |
| sram2: memory@30004000 { |
| compatible = "zephyr,memory-region", "mmio-sram"; |
| reg = <0x30004000 DT_SIZE_K(16)>; |
| zephyr,memory-region = "SRAM2"; |
| }; |
| |
| dtcm: memory@20000000 { |
| compatible = "zephyr,memory-region", "arm,dtcm"; |
| reg = <0x20000000 DT_SIZE_K(128)>; |
| zephyr,memory-region = "DTCM"; |
| }; |
| |
| itcm: memory@0 { |
| compatible = "zephyr,memory-region", "arm,itcm"; |
| reg = <0x00000000 DT_SIZE_K(64)>; |
| zephyr,memory-region = "ITCM"; |
| }; |
| |
| ext_memory: memory@70000000 { |
| compatible = "zephyr,memory-region"; |
| reg = <0x70000000 DT_SIZE_M(256)>; |
| zephyr,memory-region = "EXTMEM"; |
| zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-hse-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "st,stm32h7-hsi-clock"; |
| clock-frequency = <DT_FREQ_M(64)>; |
| status = "disabled"; |
| }; |
| |
| clk_hsi48: clk-hsi48 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(48)>; |
| status = "disabled"; |
| }; |
| |
| clk_csi: clk-csi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(4)>; |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-lse-clock"; |
| clock-frequency = <32768>; |
| driving-capability = <0>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| status = "disabled"; |
| }; |
| |
| pll: pll@0 { |
| #clock-cells = <0>; |
| compatible = "st,stm32h7rs-pll-clock"; |
| reg = <0>; |
| status = "disabled"; |
| }; |
| |
| pll2: pll@1 { |
| #clock-cells = <0>; |
| compatible = "st,stm32h7rs-pll-clock"; |
| reg = <1>; |
| status = "disabled"; |
| }; |
| |
| pll3: pll@2 { |
| #clock-cells = <0>; |
| compatible = "st,stm32h7rs-pll-clock"; |
| reg = <2>; |
| status = "disabled"; |
| }; |
| |
| perck: perck { |
| #clock-cells = <0>; |
| compatible = "st,stm32-clock-mux"; |
| status = "disabled"; |
| }; |
| }; |
| |
| mcos { |
| mco1: mco1 { |
| compatible = "st,stm32-clock-mco"; |
| status = "disabled"; |
| }; |
| |
| mco2: mco2 { |
| compatible = "st,stm32-clock-mco"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| flash: flash-controller@52002000 { |
| compatible = "st,stm32-flash-controller", "st,stm32h7-flash-controller"; |
| reg = <0x52002000 0x400>; |
| interrupts = <8 0>; |
| clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| write-block-size = <32>; |
| erase-block-size = <DT_SIZE_K(8)>; |
| /* maximum erase time for a 8K sector */ |
| max-erase-time = <3>; |
| }; |
| }; |
| |
| rcc: rcc@58024400 { |
| compatible = "st,stm32h7rs-rcc"; |
| #clock-cells = <2>; |
| reg = <0x58024400 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| exti: interrupt-controller@58000000 { |
| compatible = "st,stm32h7rs-exti", "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| reg = <0x58000000 0x400>; |
| /* SBS for interrupt */ |
| num-lines = <16>; |
| interrupts = <16 0>, <17 0>, <18 0>, <19 0>, |
| <20 0>, <21 0>, <22 0>, <23 0>, |
| <24 0>, <25 0>, <26 0>, <27 0>, |
| <28 0>, <29 0>, <30 0>, <31 0>; |
| interrupt-names = "line0", "line1", "line2", "line3", |
| "line4", "line5", "line6", "line7", |
| "line8", "line9", "line10", "line11", |
| "line12", "line13", "line14", "line15"; |
| line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, |
| <4 1>, <5 1>, <6 1>, <7 1>, |
| <8 1>, <9 1>, <10 1>, <11 1>, |
| <12 1>, <13 1>, <14 1>, <15 1>; |
| }; |
| |
| pinctrl: pin-controller@58020000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x58020000 0x2400>; |
| |
| gpioa: gpio@58020000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58020000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 0U)>; |
| }; |
| |
| gpiob: gpio@58020400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58020400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 1U)>; |
| }; |
| |
| gpioc: gpio@58020800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58020800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 2U)>; |
| }; |
| |
| gpiod: gpio@58020C00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58020C00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 3U)>; |
| }; |
| |
| gpioe: gpio@58021000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58021000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 4U)>; |
| }; |
| |
| gpiof: gpio@58021400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58021400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 5U)>; |
| }; |
| |
| gpiog: gpio@58021800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58021800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 6U)>; |
| }; |
| |
| gpioh: gpio@58021c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58021c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 7U)>; |
| }; |
| |
| gpiom: gpio@58023000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58023000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 12U)>; |
| }; |
| |
| gpion: gpio@58023400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58023400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 13U)>; |
| }; |
| |
| gpioo: gpio@58023800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58023800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 14U)>; |
| }; |
| |
| gpiop: gpio@58023c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x58023c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB4, 15U)>; |
| }; |
| }; |
| |
| usart1: serial@42001000 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x42001000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 4U)>; |
| resets = <&rctl STM32_RESET(APB2, 4U)>; |
| interrupts = <82 0>; |
| status = "disabled"; |
| }; |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 17U)>; |
| resets = <&rctl STM32_RESET(APB1L, 17U)>; |
| interrupts = <83 0>; |
| status = "disabled"; |
| }; |
| usart3: serial@40004800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 18U)>; |
| resets = <&rctl STM32_RESET(APB1L, 18U)>; |
| interrupts = <84 0>; |
| status = "disabled"; |
| }; |
| uart4: serial@40004c00 { |
| compatible ="st,stm32-uart"; |
| reg = <0x40004c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 19U)>; |
| resets = <&rctl STM32_RESET(APB1L, 19U)>; |
| interrupts = <85 0>; |
| status = "disabled"; |
| }; |
| uart5: serial@40005000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40005000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 20U)>; |
| resets = <&rctl STM32_RESET(APB1L, 20U)>; |
| interrupts = <86 0>; |
| status = "disabled"; |
| }; |
| uart7: serial@40007800 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40007800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 30U)>; |
| resets = <&rctl STM32_RESET(APB1L, 30U)>; |
| interrupts = <87 0>; |
| status = "disabled"; |
| }; |
| uart8: serial@40007c00 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40007c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 31U)>; |
| resets = <&rctl STM32_RESET(APB1L, 31U)>; |
| interrupts = <88 0>; |
| status = "disabled"; |
| }; |
| |
| lpuart1: serial@58000c00 { |
| compatible = "st,stm32-lpuart", "st,stm32-uart"; |
| reg = <0x58000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB4, 3U)>; |
| resets = <&rctl STM32_RESET(APB4, 3U)>; |
| interrupts = <131 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 21U)>; |
| interrupts = <76 0>, <77 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 22U)>; |
| interrupts = <78 0>, <79 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@40005c00 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 23U)>; |
| interrupts = <80 0>, <81 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@42003000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x42003000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 12U)>, |
| <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; |
| interrupts = <58 0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 14U)>, |
| <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; |
| interrupts = <59 0>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@40003c00 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 15U)>, |
| <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; |
| interrupts = <60 0>; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@42003400 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x42003400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 13U)>; |
| interrupts = <61 0>; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@42005000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x42005000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 20U)>; |
| interrupts = <62 0>; |
| status = "disabled"; |
| }; |
| |
| i2s1: i2s@40013000 { |
| compatible = "st,stm32h7-i2s", "st,stm32-i2s"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 12U)>, |
| <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; |
| interrupts = <35 3>; |
| status = "disabled"; |
| }; |
| |
| iwdg: iwdg1: watchdog@58004800 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x58004800 0x400>; |
| interrupts = <3 0>; |
| status = "disabled"; |
| }; |
| |
| wwdg: wwdg1: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002c00 0x1000>; |
| clocks = <&rcc STM32_CLOCK(APB1, 11U)>; |
| interrupts = <4 7>; |
| status = "disabled"; |
| }; |
| |
| timers1: timers@42000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x42000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 0U)>; |
| resets = <&rctl STM32_RESET(APB2, 0U)>; |
| interrupts = <47 0>, <48 0>, <49 0>, <50 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 0U)>; |
| resets = <&rctl STM32_RESET(APB1L, 0U)>; |
| interrupts = <51 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 1U)>; |
| resets = <&rctl STM32_RESET(APB1L, 1U)>; |
| interrupts = <52 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 2U)>; |
| resets = <&rctl STM32_RESET(APB1L, 2U)>; |
| interrupts = <53 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers5: timers@40000c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 3U)>; |
| resets = <&rctl STM32_RESET(APB1L, 3U)>; |
| interrupts = <54 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers6: timers@40001000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 4U)>; |
| resets = <&rctl STM32_RESET(APB1L, 4U)>; |
| interrupts = <55 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers7: timers@40001400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 5U)>; |
| resets = <&rctl STM32_RESET(APB1L, 5U)>; |
| interrupts = <56 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers9: timers@42004c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x42004c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 19U)>; |
| resets = <&rctl STM32_RESET(APB2, 19U)>; |
| interrupts = <57 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers15: timers@42004000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x42004000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 16U)>; |
| resets = <&rctl STM32_RESET(APB2, 16U)>; |
| interrupts = <116 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers16: timers@42004400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x42004400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 17U)>; |
| resets = <&rctl STM32_RESET(APB2, 17U)>; |
| interrupts = <117 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers17: timers@42004800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x42004800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 18U)>; |
| resets = <&rctl STM32_RESET(APB2, 18U)>; |
| interrupts = <118 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| lptim1: timers@40002400 { |
| compatible = "st,stm32-lptim"; |
| clocks = <&rcc STM32_CLOCK(APB1, 9U)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40002400 0x400>; |
| interrupts = <119 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| adc1: adc@40022000 { |
| compatible = "st,stm32-adc"; |
| reg = <0x40022000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; |
| interrupts = <38 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x2) |
| STM32_ADC_RES(6, 0x3)>; |
| sampling-times = <3 7 13 25 48 93 248 641>; |
| st,adc-sequencer = <FULLY_CONFIGURABLE>; |
| }; |
| |
| adc2: adc@40022100 { |
| compatible = "st,stm32-adc"; |
| reg = <0x40022100 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 5U)>; |
| interrupts = <38 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <3 7 13 25 48 93 248 641>; |
| st,adc-sequencer = <FULLY_CONFIGURABLE>; |
| }; |
| |
| rng: rng@48020000 { |
| compatible = "st,stm32-rng"; |
| reg = <0x48020000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB3, 0U)>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp-cal"; |
| ts-cal1-addr = <0x08FFF814>; |
| ts-cal2-addr = <0x08FFF818>; |
| ts-cal1-temp = <30>; |
| ts-cal2-temp = <130>; |
| ts-cal-vrefanalog = <3300>; |
| ts-cal-resolution = <12>; |
| io-channels = <&adc1 16>; |
| status = "disabled"; |
| }; |
| |
| vbat: vbat { |
| compatible = "st,stm32-vbat"; |
| ratio = <4>; |
| status = "disabled"; |
| io-channels = <&adc2 16>; |
| }; |
| |
| vref: vref { |
| compatible = "st,stm32-vref"; |
| vrefint-cal-addr = <0x08fff810>; |
| vrefint-cal-mv = <3300>; |
| status = "disabled"; |
| io-channels = <&adc1 17>; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
