| /* |
| * Copyright (c) 2017 Linaro Limited |
| * Copyright (c) 2019 Centaur Analytics, Inc |
| * Copyright (c) 2024 STMicroelectronics |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| |
| #include <arm/armv7-m.dtsi> |
| #include <zephyr/dt-bindings/clock/stm32l4_clock.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/adc/adc.h> |
| #include <zephyr/dt-bindings/pwm/stm32_pwm.h> |
| #include <zephyr/dt-bindings/dma/stm32_dma.h> |
| #include <zephyr/dt-bindings/adc/stm32l4_adc.h> |
| #include <zephyr/dt-bindings/reset/stm32g4_l4_5_reset.h> |
| #include <zephyr/dt-bindings/power/stm32_pwr.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,entropy = &rng; |
| zephyr,flash-controller = &flash; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m4f"; |
| reg = <0>; |
| cpu-power-states = <&stop0 &stop1 &stop2>; |
| }; |
| |
| power-states { |
| stop0: state0 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <1>; |
| min-residency-us = <500>; |
| }; |
| stop1: state1 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <2>; |
| min-residency-us = <700>; |
| }; |
| stop2: state2 { |
| compatible = "zephyr,power-state"; |
| power-state-name = "suspend-to-idle"; |
| substate-id = <3>; |
| min-residency-us = <1000>; |
| }; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-hse-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(16)>; |
| status = "disabled"; |
| }; |
| |
| clk_msi: clk-msi { |
| #clock-cells = <0>; |
| compatible = "st,stm32-msi-clock"; |
| msi-range = <6>; /* 4MHz (reset value) */ |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-lse-clock"; |
| clock-frequency = <32768>; |
| driving-capability = <0>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| status = "disabled"; |
| }; |
| |
| pll: pll { |
| #clock-cells = <0>; |
| compatible = "st,stm32l4-pll-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| mcos { |
| mco1: mco1 { |
| compatible = "st,stm32-clock-mco"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| flash: flash-controller@40022000 { |
| compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller"; |
| reg = <0x40022000 0x400>; |
| interrupts = <4 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| |
| write-block-size = <8>; |
| erase-block-size = <2048>; |
| /* maximum erase time(ms) for a 2K sector */ |
| max-erase-time = <25>; |
| }; |
| }; |
| |
| rcc: rcc@40021000 { |
| compatible = "st,stm32-rcc"; |
| #clock-cells = <2>; |
| reg = <0x40021000 0x400>; |
| |
| rctl: reset-controller { |
| compatible = "st,stm32-rcc-rctl"; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| exti: interrupt-controller@40010400 { |
| compatible = "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| #address-cells = <1>; |
| reg = <0x40010400 0x400>; |
| num-lines = <16>; |
| interrupts = <6 0>, <7 0>, <8 0>, <9 0>, |
| <10 0>, <23 0>, <40 0>; |
| interrupt-names = "line0", "line1", "line2", "line3", |
| "line4", "line5-9", "line10-15"; |
| line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, |
| <4 1>, <5 5>, <10 6>; |
| }; |
| |
| pinctrl: pin-controller@48000000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x48000000 0x2000>; |
| |
| gpioa: gpio@48000000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 0U)>; |
| }; |
| |
| gpiob: gpio@48000400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000400 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 1U)>; |
| }; |
| |
| gpioc: gpio@48000800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48000800 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 2U)>; |
| }; |
| |
| gpioh: gpio@48001c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x48001c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 7U)>; |
| }; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| status = "disabled"; |
| }; |
| |
| wwdg: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002C00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 11U)>; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 14U)>; |
| resets = <&rctl STM32_RESET(APB2, 14U)>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 17U)>; |
| resets = <&rctl STM32_RESET(APB1L, 17U)>; |
| interrupts = <38 0>; |
| status = "disabled"; |
| }; |
| |
| lpuart1: serial@40008000 { |
| compatible = "st,stm32-lpuart", "st,stm32-uart"; |
| reg = <0x40008000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 0U)>; |
| resets = <&rctl STM32_RESET(APB1H, 0U)>; |
| interrupts = <70 0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 21U)>; |
| interrupts = <31 0>, <32 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@40005c00 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 23U)>; |
| interrupts = <72 0>, <73 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| quadspi: quadspi@a0001000 { |
| compatible = "st,stm32-qspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0xa0001000 0x400>; |
| interrupts = <71 0>; |
| clocks = <&rcc STM32_CLOCK(AHB3, 8U)>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| interrupts = <35 5>; |
| clocks = <&rcc STM32_CLOCK(APB2, 12U)>; |
| status = "disabled"; |
| }; |
| |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 11U)>; |
| resets = <&rctl STM32_RESET(APB2, 11U)>; |
| interrupts = <24 0>, <25 0>, <26 0>, <27 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 0U)>; |
| resets = <&rctl STM32_RESET(APB1L, 0U)>; |
| interrupts = <28 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers6: timers@40001000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40001000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1, 4U)>; |
| resets = <&rctl STM32_RESET(APB1L, 4U)>; |
| interrupts = <54 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers15: timers@40014000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014000 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 16U)>; |
| resets = <&rctl STM32_RESET(APB2, 16U)>; |
| interrupts = <24 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timers16: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB2, 17U)>; |
| resets = <&rctl STM32_RESET(APB2, 17U)>; |
| interrupts = <25 0>; |
| interrupt-names = "global"; |
| st,prescaler = <0>; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| |
| counter { |
| compatible = "st,stm32-counter"; |
| status = "disabled"; |
| }; |
| }; |
| |
| rtc: rtc@40002800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x40002800 0x400>; |
| interrupts = <41 0>; |
| clocks = <&rcc STM32_CLOCK(APB1, 28U)>; |
| prescaler = <32768>; |
| alarms-count = <2>; |
| alrm-exti-line = <18>; |
| status = "disabled"; |
| }; |
| |
| adc1: adc@50040000 { |
| compatible = "st,stm32-adc"; |
| reg = <0x50040000 0x100>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <3 7 13 25 48 93 248 641>; |
| st,adc-sequencer = <FULLY_CONFIGURABLE>; |
| }; |
| |
| adc2: adc@50040100 { |
| compatible = "st,stm32-adc"; |
| reg = <0x50040100 0x100>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 13U)>; |
| interrupts = <18 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| resolutions = <STM32_ADC_RES(12, 0x00) |
| STM32_ADC_RES(10, 0x01) |
| STM32_ADC_RES(8, 0x02) |
| STM32_ADC_RES(6, 0x03)>; |
| sampling-times = <3 7 13 25 48 93 248 641>; |
| st,adc-sequencer = <FULLY_CONFIGURABLE>; |
| }; |
| |
| dma1: dma@40020000 { |
| compatible = "st,stm32-dma-v2"; |
| #dma-cells = <3>; |
| reg = <0x40020000 0x400>; |
| interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; |
| dma-requests = <7>; |
| status = "disabled"; |
| }; |
| |
| dma2: dma@40020400 { |
| compatible = "st,stm32-dma-v2"; |
| #dma-cells = <3>; |
| reg = <0x40020400 0x400>; |
| interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0>; |
| clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; |
| dma-requests = <7>; |
| status = "disabled"; |
| }; |
| |
| lptim1: timers@40007c00 { |
| compatible = "st,stm32-lptim"; |
| clocks = <&rcc STM32_CLOCK(APB1, 31U)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40007c00 0x400>; |
| interrupts = <65 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| lptim2: timers@40009400 { |
| compatible = "st,stm32-lptim"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40009400 0x400>; |
| clocks = <&rcc STM32_CLOCK(APB1_2, 5U)>; |
| interrupts = <66 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| rng: rng@50060800 { |
| compatible = "st,stm32-rng"; |
| reg = <0x50060800 0x400>; |
| interrupts = <80 0>; |
| clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, |
| /* Following domain clock setting requires MSI |
| * clock to be enabled with msi-range = <11>; |
| */ |
| <&rcc STM32_SRC_MSI CLK48_SEL(3)>; |
| status = "disabled"; |
| }; |
| |
| pwr: power@40007000 { |
| compatible = "st,stm32-pwr"; |
| reg = <0x40007000 0x400>; /* PWR register bank */ |
| status = "disabled"; |
| |
| wkup-pins-nb = <5>; /* 5 system wake-up pins */ |
| wkup-pins-pol; |
| wkup-pins-pupd; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| wkup-pin@1 { |
| reg = <0x1>; |
| }; |
| |
| wkup-pin@2 { |
| reg = <0x2>; |
| }; |
| |
| wkup-pin@3 { |
| reg = <0x3>; |
| }; |
| |
| wkup-pin@4 { |
| reg = <0x4>; |
| }; |
| |
| wkup-pin@5 { |
| reg = <0x5>; |
| }; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp-cal"; |
| ts-cal1-addr = <0x1FFF75A8>; |
| ts-cal2-addr = <0x1FFF75CA>; |
| ts-cal1-temp = <30>; |
| ts-cal2-temp = <130>; |
| ts-cal-vrefanalog = <3000>; |
| io-channels = <&adc1 17>; |
| status = "disabled"; |
| }; |
| |
| vref: vref { |
| compatible = "st,stm32-vref"; |
| vrefint-cal-addr = <0x1FFF75AA>; |
| vrefint-cal-mv = <3000>; |
| io-channels = <&adc1 0>; |
| status = "disabled"; |
| }; |
| |
| vbat: vbat { |
| compatible = "st,stm32-vbat"; |
| ratio = <3>; |
| io-channels = <&adc1 18>; |
| status = "disabled"; |
| }; |
| |
| smbus1: smbus1 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c1>; |
| status = "disabled"; |
| }; |
| |
| smbus3: smbus3 { |
| compatible = "st,stm32-smbus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| i2c = <&i2c3>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
