| /* |
| * Copyright (c) 2023 Enphase Energy |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <mem.h> |
| #include <freq.h> |
| #include <arm64/armv8-a.dtsi> |
| #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> |
| #include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0>; |
| }; |
| }; |
| |
| oc_sram: memory@70000000 { |
| reg = <0x70000000 DT_SIZE_K(64)>; |
| }; |
| |
| arch_timer: timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 14 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 11 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 10 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| gic: interrupt-controller@1800000 { |
| compatible = "arm,gic"; |
| reg = <0x01800000 0x10000>, /* GICD */ |
| <0x01880000 0xc0000>; /* GICR */ |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| status = "okay"; |
| }; |
| |
| pinctrl: pinctrl@f4000 { |
| compatible = "ti,k3-pinctrl"; |
| reg = <0x000f4000 0x2ac>; |
| status = "okay"; |
| }; |
| |
| uart0: serial@2800000 { |
| compatible = "ns16550"; |
| reg = <0x02800000 0x100>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@2810000 { |
| compatible = "ns16550"; |
| reg = <0x02810000 0x100>; |
| interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@2820000 { |
| compatible = "ns16550"; |
| reg = <0x02820000 0x100>; |
| interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@2830000 { |
| compatible = "ns16550"; |
| reg = <0x02830000 0x100>; |
| interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@2840000 { |
| compatible = "ns16550"; |
| reg = <0x02840000 0x100>; |
| interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@2850000 { |
| compatible = "ns16550"; |
| reg = <0x02850000 0x100>; |
| interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| |
| uart6: serial@2860000 { |
| compatible = "ns16550"; |
| reg = <0x02860000 0x100>; |
| interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; |
| interrupt-parent = <&gic>; |
| clock-frequency = <48000000>; |
| current-speed = <115200>; |
| reg-shift = <2>; |
| status = "disabled"; |
| }; |
| }; |