| # NPCX Flash driver configuration options |
| |
| # Copyright (c) 2023 Nuvoton Technology Corporation. |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config FLASH_NPCX_FIU_QSPI |
| bool "Nuvoton NPCX QSPI Bus Flash driver" |
| default y |
| depends on DT_HAS_NUVOTON_NPCX_FIU_QSPI_ENABLED |
| select PINCTRL |
| help |
| This option enables the QSPI Bus Flash driver for NPCX family of |
| processors. |
| |
| config FLASH_NPCX_FIU_NOR |
| bool "Nuvoton NPCX embedded controller (EC) QSPI NOR Flash driver" |
| default y |
| depends on DT_HAS_NUVOTON_NPCX_FIU_NOR_ENABLED |
| depends on FLASH_NPCX_FIU_QSPI |
| select FLASH_HAS_DRIVER_ENABLED |
| select FLASH_HAS_PAGE_LAYOUT |
| select FLASH_HAS_EXPLICIT_ERASE |
| select FLASH_JESD216 |
| select FLASH_HAS_EX_OP |
| help |
| This option enables the QSPI NOR Flash driver for NPCX family of |
| processors. |
| |
| config FLASH_NPCX_FIU_USE_DMA |
| bool "Use GDMA for FIU transactions" |
| default y if $(dt_nodelabel_has_prop,qspi_fiu0,dmas) |
| depends on DMA_NPCX_GDMA |
| help |
| Enable GDMA transaction |
| |
| if FLASH_NPCX_FIU_QSPI |
| |
| config FLASH_NPCX_FIU_NOR_INIT |
| bool "QSPI NOR flash feature during driver initialization" |
| default y |
| depends on FLASH_NPCX_FIU_NOR |
| help |
| This option enables the QSPI NOR Flash features such as Quad-Enable, |
| 4-byte address support and so on during driver initialization. Disable |
| it if QSPI NOR devices are not ready during driver initialization. |
| |
| config FLASH_NPCX_FIU_DRA_V1 |
| bool "Direct Read Access version 1 support" |
| default y |
| depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NUVOTON_NPCX_FIU_QSPI),support-npcxn-v1,True) |
| help |
| This option enables DRA V1 support. |
| |
| config FLASH_NPCX_FIU_DRA_V2 |
| bool "Direct Read Access version 2 support" |
| default y |
| depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NUVOTON_NPCX_FIU_QSPI),support-npcxn-v2,True) |
| help |
| This option enables DRA V2 support. |
| |
| config FLASH_NPCX_FIU_DRA_EX |
| bool "Extended Direct Read Access mode support" |
| default y |
| depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NUVOTON_NPCX_FIU_QSPI),support-npckn-v1,True) |
| help |
| This option enables extended DRA mode support for NPCKn variant of |
| processors. |
| |
| config FLASH_NPCX_FIU_UMA_EX |
| bool "Extended User Mode Access mode support" |
| default y |
| depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NUVOTON_NPCX_FIU_QSPI),support-npckn-v1,True) |
| help |
| This option enables extended UMA mode support for NPCKn variant of |
| processors. |
| |
| config FLASH_NPCX_FIU_SUPP_DRA_4B_ADDR |
| bool "4 byte address support in Direct Read Access mode" |
| default y if FLASH_NPCX_FIU_DRA_V1 || \ |
| FLASH_NPCX_FIU_DRA_V2 || \ |
| FLASH_NPCX_FIU_DRA_EX |
| help |
| Selected if NPCX series supports 4 byte address mode in Direct Read |
| Access mode. |
| |
| config FLASH_NPCX_FIU_SUPP_DRA_2_DEV |
| bool "4 byte address support in Direct Read Access mode" |
| default y if FLASH_NPCX_FIU_DRA_V1 || \ |
| FLASH_NPCX_FIU_DRA_V2 |
| help |
| Selected if NPCX series supports two external SPI devices in Direct |
| Read Access (DRA) on QSPI bus. |
| |
| DT_NPCX_FIU_LOW_DEV_SWAP := $(dt_nodelabel_bool_prop,qspi_fiu1,flash-dev-inv) |
| config FLASH_NPCX_FIU_SUPP_LOW_DEV_SWAP |
| bool "Inverse the access of the two external flashes" |
| default y if SOC_SERIES_NPCX4 && FLASH_NPCX_FIU_SUPP_DRA_2_DEV && \ |
| "$(DT_NPCX_FIU_LOW_DEV_SWAP)" |
| help |
| Select if it needs to swap the access of the two external flashes. |
| |
| endif #FLASH_NPCX_FIU_QSPI |
