| /* |
| * Copyright (c) 2018, NXP |
| * Copyright (c) 2020, Bernhard Kraemer |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| #include <init.h> |
| #include <fsl_iomuxc.h> |
| #include <fsl_gpio.h> |
| #include <soc.h> |
| #include <logging/log.h> |
| |
| LOG_MODULE_REGISTER(teensy40, LOG_LEVEL_INF); |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET |
| static gpio_pin_config_t enet_gpio_config = { |
| .direction = kGPIO_DigitalOutput, |
| .outputLogic = 0, |
| .interruptMode = kGPIO_NoIntmode |
| }; |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC |
| |
| /*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR) |
| *Speed Field: medium(100MHz) |
| *Open Drain Enable Field: Open Drain Disabled |
| *Pull / Keep Enable Field: Pull/Keeper Enabled |
| *Pull / Keep Select Field: Pull |
| *Pull Up / Down Config. Field: 47K Ohm Pull Up |
| *Hyst. Enable Field: Hysteresis Enabled. |
| */ |
| |
| static void teensy4_usdhc_pinmux(uint16_t nusdhc, bool init, uint32_t speed, |
| uint32_t strength) |
| { |
| uint32_t cmd_data = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | |
| IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_PUS(1) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(strength); |
| |
| uint32_t clk = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | |
| IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_PUS(0) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(strength); |
| |
| if (nusdhc != 0) { |
| LOG_ERR("Invalid USDHC index"); |
| return; |
| } |
| |
| if (init) { |
| IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_USDHC1_VSELECT, 0U); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, 0U); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, 0U); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, 0U); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, 0U); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, 0U); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U); |
| |
| /* SD0_VSELECT */ |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_USDHC1_VSELECT, |
| 0x0170A1u); |
| } |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD, cmd_data); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK, clk); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0, cmd_data); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1, cmd_data); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2, cmd_data); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, cmd_data); |
| } |
| |
| static void teensy4_usdhc_dat3_pull(bool pullup) |
| { |
| if (pullup) { |
| /* Set pin config to pull up (47k Ohm) */ |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(1)); |
| } else { |
| /* pull down (100k Ohm) */ |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(1) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(1)); |
| } |
| } |
| #endif |
| |
| static int teensy4_init(const struct device *dev) |
| { |
| ARG_UNUSED(dev); |
| |
| CLOCK_EnableClock(kCLOCK_Iomuxc); |
| CLOCK_EnableClock(kCLOCK_IomuxcSnvs); |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart6), okay) && CONFIG_SERIAL |
| /* LPUART6 TX/RX on Teensy-Pins 1/0 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_LPUART6_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_LPUART6_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_LPUART6_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_LPUART6_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart4), okay) && CONFIG_SERIAL |
| /* LPUART4 TX/RX on Teensy-Pins 8/7 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_00_LPUART4_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_01_LPUART4_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_00_LPUART4_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_01_LPUART4_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart2), okay) && CONFIG_SERIAL |
| /* LPUART2 TX/RX on Teensy-Pins 14/15 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_02_LPUART2_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_03_LPUART2_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_02_LPUART2_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_03_LPUART2_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart3), okay) && CONFIG_SERIAL |
| /* LPUART3 TX/RX on Teensy-Pins 17/16 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart8), okay) && CONFIG_SERIAL |
| /* LPUART8 TX/RX on Teensy-Pins 20/21 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_10_LPUART8_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_11_LPUART8_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_10_LPUART8_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_11_LPUART8_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL |
| /* LPUART1 TX/RX on Teensy-Pins 20/21 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart7), okay) && CONFIG_SERIAL |
| /* LPUART7 TX/RX on Teensy-Pins 29/28 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_31_LPUART7_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_32_LPUART7_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_31_LPUART7_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_32_LPUART7_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart5), okay) && CONFIG_SERIAL |
| /* LPUART5 TX/RX on Teensy-Pins 35/34 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_12_LPUART5_TX, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_13_LPUART5_RX, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_12_LPUART5_TX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_13_LPUART5_RX, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c3), okay) && CONFIG_I2C |
| /* LPI2C3 SCL, SDA on Teensy-Pins 16/17 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, 1); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, 1); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL, |
| IOMUXC_SW_PAD_CTL_PAD_PUS(3) | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA, |
| IOMUXC_SW_PAD_CTL_PAD_PUS(3) | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) && CONFIG_I2C |
| /* LPI2C1 SCL, SDA on Teensy-Pins 19/18*/ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, 1); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 1); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL, |
| IOMUXC_SW_PAD_CTL_PAD_PUS(3) | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, |
| IOMUXC_SW_PAD_CTL_PAD_PUS(3) | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c4), okay) && CONFIG_I2C |
| /* LPI2C4 SCL, SDA on Teensy-Pins 24/25*/ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL, 1); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA, 1); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL, |
| IOMUXC_SW_PAD_CTL_PAD_PUS(3) | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA, |
| IOMUXC_SW_PAD_CTL_PAD_PUS(3) | |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi3), okay) && CONFIG_SPI |
| /* LPSPI3 MISO, MOSI, SCK, CS on Teensy-Pins 39/26/27/38 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi4), okay) && CONFIG_SPI |
| /* LPSPI3 MISO, MOSI, SCK, CS on Teensy-Pins 12/11/13/10 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B0_00_LPSPI4_PCS0, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B0_01_LPSPI4_SDI, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B0_02_LPSPI4_SDO, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B0_03_LPSPI4_SCK, 0); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_00_LPSPI4_PCS0, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_LPSPI4_SDI, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_02_LPSPI4_SDO, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_03_LPSPI4_SCK, |
| IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | |
| IOMUXC_SW_PAD_CTL_PAD_SPEED(2) | |
| IOMUXC_SW_PAD_CTL_PAD_DSE(6)); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B0_14_GPIO2_IO14, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B0_15_GPIO2_IO15, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_14_ENET_MDC, 0); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_B1_15_ENET_MDIO, 0); |
| |
| /* Mode Straps configuration DP83825 */ |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0x30E9); /* PhyAdd[0] = 0 */ |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xF0E9); /* RMII Master/Slave = 1*/ |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0x30E9); /* PhyAdd[1] = 0 */ |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0x30E9); /* A-MDIX = 0 */ |
| |
| IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); |
| |
| /* Initialize ENET_INT GPIO */ |
| GPIO_PinInit(GPIO2, 14, &enet_gpio_config); |
| GPIO_PinInit(GPIO2, 15, &enet_gpio_config); |
| |
| /* pull up the ENET_INT before RESET. */ |
| GPIO_WritePinOutput(GPIO2, 15, 1); |
| GPIO_WritePinOutput(GPIO2, 14, 0); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan2), okay) && CONFIG_CAN |
| /* FLEXCAN2 TX, RX on Teensy-Pins 1/0 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX, 1); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX, 1); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX, 0x10B0u); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX, 0x10B0u); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan1), okay) && CONFIG_CAN |
| /* FLEXCAN1 TX, RX on Teensy-Pins 22/23 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX, 1); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX, 1); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX, 0x10B0u); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX, 0x10B0u); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan3), okay) && CONFIG_CAN |
| /* FLEXCAN3 TX, RX on Teensy-Pins 31/30 */ |
| IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_36_FLEXCAN3_TX, 1); |
| IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_37_FLEXCAN3_RX, 1); |
| |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_36_FLEXCAN3_TX, 0x10B0u); |
| IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_37_FLEXCAN3_RX, 0x10B0u); |
| #endif |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC |
| teensy4_usdhc_pinmux(0, true, 2, 1); |
| imxrt_usdhc_pinmux_cb_register(teensy4_usdhc_pinmux); |
| imxrt_usdhc_dat3_cb_register(teensy4_usdhc_dat3_pull); |
| #endif |
| |
| return 0; |
| } |
| |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET |
| static int teensy4_phy_reset(const struct device *dev) |
| { |
| /* RESET PHY chip. */ |
| k_busy_wait(USEC_PER_MSEC * 50U); /* Power up timing T4 of PHY = 50ms */ |
| GPIO_WritePinOutput(GPIO2, 14, 1); |
| |
| return 0; |
| } |
| #endif |
| |
| SYS_INIT(teensy4_init, PRE_KERNEL_1, 0); |
| #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET |
| SYS_INIT(teensy4_phy_reset, PRE_KERNEL_2, 0); |
| #endif |
