| /* |
| * Copyright (c) 2021 The Chromium OS Authors |
| * Copyright (c) 2021 Linaro Limited |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| |
| #include <arm/armv8-m.dtsi> |
| #include <zephyr/dt-bindings/pwm/pwm.h> |
| #include <zephyr/dt-bindings/clock/stm32u5_clock.h> |
| #include <zephyr/dt-bindings/gpio/gpio.h> |
| #include <zephyr/dt-bindings/i2c/i2c.h> |
| #include <zephyr/dt-bindings/flash_controller/ospi.h> |
| #include <freq.h> |
| |
| / { |
| chosen { |
| zephyr,entropy = &rng; |
| zephyr,flash-controller = &flash; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-m33"; |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mpu: mpu@e000ed90 { |
| compatible = "arm,armv8m-mpu"; |
| reg = <0xe000ed90 0x40>; |
| arm,num-mpu-regions = <8>; |
| }; |
| }; |
| }; |
| |
| sram0: memory@20000000 { |
| compatible = "mmio-sram"; |
| }; |
| |
| clocks { |
| clk_hse: clk-hse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-hse-clock"; |
| status = "disabled"; |
| }; |
| |
| clk_hsi: clk-hsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_M(16)>; |
| status = "disabled"; |
| }; |
| |
| clk_msis: clk-msis { |
| #clock-cells = <0>; |
| compatible = "st,stm32u5-msi-clock"; |
| msi-range = <4>; /* 4MHz (reset value) */ |
| status = "disabled"; |
| }; |
| |
| clk_msik: clk-msik { |
| #clock-cells = <0>; |
| compatible = "st,stm32u5-msi-clock"; |
| msi-range = <4>; /* 4MHz (reset value) */ |
| status = "disabled"; |
| }; |
| |
| clk_lse: clk-lse { |
| #clock-cells = <0>; |
| compatible = "st,stm32-lse-clock"; |
| clock-frequency = <32768>; |
| driving-capability = <2>; |
| status = "disabled"; |
| }; |
| |
| clk_lsi: clk-lsi { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <DT_FREQ_K(32)>; |
| status = "disabled"; |
| }; |
| |
| pll1: pll: pll { |
| #clock-cells = <0>; |
| compatible = "st,stm32u5-pll-clock"; |
| status = "disabled"; |
| }; |
| |
| pll2: pll2 { |
| #clock-cells = <0>; |
| compatible = "st,stm32u5-pll-clock"; |
| status = "disabled"; |
| }; |
| |
| pll3: pll3 { |
| #clock-cells = <0>; |
| compatible = "st,stm32u5-pll-clock"; |
| status = "disabled"; |
| }; |
| }; |
| |
| soc { |
| flash: flash-controller@40022000 { |
| compatible = "st,stm32-flash-controller", "st,stm32u5-flash-controller"; |
| reg = <0x40022000 0x400>; |
| interrupts = <6 0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| flash0: flash@8000000 { |
| compatible = "st,stm32-nv-flash", "soc-nv-flash"; |
| |
| write-block-size = <16>; |
| erase-block-size = <8192>; |
| /* maximum erase time(ms) for a 8K sector */ |
| max-erase-time = <5>; |
| }; |
| }; |
| |
| rcc: rcc@46020c00 { |
| compatible = "st,stm32u5-rcc"; |
| clocks-controller; |
| #clock-cells = <2>; |
| reg = <0x46020c00 0x400>; |
| }; |
| |
| exti: interrupt-controller@46022000 { |
| compatible = "st,stm32-exti"; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| reg = <0x46022000 0x400>; |
| }; |
| |
| pinctrl: pin-controller@42020000 { |
| compatible = "st,stm32-pinctrl"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x42020000 0x2000>; |
| |
| gpioa: gpio@42020000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>; |
| }; |
| |
| gpiob: gpio@42020400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>; |
| }; |
| |
| gpioc: gpio@42020800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>; |
| }; |
| |
| gpiod: gpio@42020c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42020c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; |
| }; |
| |
| gpioe: gpio@42021000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; |
| }; |
| |
| gpiof: gpio@42021400 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>; |
| }; |
| |
| gpiog: gpio@42021800 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>; |
| }; |
| |
| gpioh: gpio@42021c00 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42021c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>; |
| }; |
| |
| gpioi: gpio@42022000 { |
| compatible = "st,stm32-gpio"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0x42022000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>; |
| }; |
| }; |
| |
| iwdg: watchdog@40003000 { |
| compatible = "st,stm32-watchdog"; |
| reg = <0x40003000 0x400>; |
| status = "disabled"; |
| }; |
| |
| wwdg: wwdg1: watchdog@40002c00 { |
| compatible = "st,stm32-window-watchdog"; |
| reg = <0x40002c00 0x1000>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; |
| interrupts = <0 7>; |
| status = "disabled"; |
| }; |
| |
| usart1: serial@40013800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40013800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; |
| interrupts = <61 0>; |
| status = "disabled"; |
| }; |
| |
| usart2: serial@40004400 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; |
| interrupts = <62 0>; |
| status = "disabled"; |
| }; |
| |
| usart3: serial@40004800 { |
| compatible = "st,stm32-usart", "st,stm32-uart"; |
| reg = <0x40004800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; |
| interrupts = <63 0>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@40004c00 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40004c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; |
| interrupts = <64 0>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@40005000 { |
| compatible = "st,stm32-uart"; |
| reg = <0x40005000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; |
| interrupts = <65 0>; |
| status = "disabled"; |
| }; |
| |
| lpuart1: serial@46002400 { |
| compatible = "st,stm32-lpuart", "st,stm32-uart"; |
| reg = <0x46002400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000040>; |
| interrupts = <66 0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@40013000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40013000 0x400>; |
| interrupts = <59 5>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@40003800 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40003800 0x400>; |
| interrupts = <60 5>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@46002000 { |
| compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x46002000 0x400>; |
| interrupts = <99 5>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000020>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@40005400 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; |
| interrupts = <55 0>, <56 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@40005800 { |
| compatible = "st,stm32-i2c-v2"; |
| clock-frequency = <I2C_BITRATE_STANDARD>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x40005800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; |
| interrupts = <57 0>, <58 0>; |
| interrupt-names = "event", "error"; |
| status = "disabled"; |
| }; |
| |
| timers1: timers@40012c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40012c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>; |
| interrupts = <41 0>, <42 0>, <43 0>, <44 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers2: timers@40000000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>; |
| interrupts = <45 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers3: timers@40000400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; |
| interrupts = <46 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| lptim1: timers@46004400 { |
| compatible = "st,stm32-lptim"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x46004400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>; |
| interrupts = <67 1>; |
| interrupt-names = "wakeup"; |
| status = "disabled"; |
| }; |
| |
| rtc: rtc@46007800 { |
| compatible = "st,stm32-rtc"; |
| reg = <0x46007800 0x400>; |
| interrupts = <2 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>; |
| prescaler = <32768>; |
| status = "disabled"; |
| }; |
| |
| timers4: timers@40000800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; |
| interrupts = <47 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers5: timers@40000c00 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40000c00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; |
| interrupts = <48 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers8: timers@40013400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40013400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; |
| interrupts = <51 0>, <52 0>, <53 0>, <54 0>; |
| interrupt-names = "brk", "up", "trgcom", "cc"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers15: timers@40014000 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>; |
| interrupts = <69 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers16: timers@40014400 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014400 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>; |
| interrupts = <70 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| timers17: timers@40014800 { |
| compatible = "st,stm32-timers"; |
| reg = <0x40014800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>; |
| interrupts = <71 0>; |
| interrupt-names = "global"; |
| status = "disabled"; |
| |
| pwm { |
| compatible = "st,stm32-pwm"; |
| status = "disabled"; |
| #pwm-cells = <3>; |
| }; |
| }; |
| |
| octospi1: octospi@420d1400 { |
| compatible = "st,stm32-ospi"; |
| reg = <0x420d1400 0x400>; |
| interrupts = <76 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2_2 0x00000010>, |
| <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| octospi2: octospi@420d2400 { |
| compatible = "st,stm32-ospi"; |
| reg = <0x420d2400 0x400>; |
| interrupts = <120 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2_2 0x00000100>, |
| <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| rng: rng@420c0800 { |
| compatible = "st,stm32-rng"; |
| reg = <0x420c0800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>; |
| interrupts = <94 0>; |
| nist-config = <0xf60d00>; |
| health-test-config = <0x9aae>; |
| status = "disabled"; |
| }; |
| |
| dac1: dac@46021800 { |
| compatible = "st,stm32-dac"; |
| reg = <0x46021800 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000040>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| }; |
| |
| adc1: adc@42028000 { |
| compatible = "st,stm32-adc"; |
| reg = <0x42028000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000400>; |
| interrupts = <37 0>; |
| status = "disabled"; |
| vref-mv = <3300>; |
| #io-channel-cells = <1>; |
| has-temp-channel; |
| has-vref-channel; |
| }; |
| |
| adc4: adc@46021000 { |
| compatible = "st,stm32-adc"; |
| reg = <0x46021000 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000020>; |
| interrupts = <113 0>; |
| status = "disabled"; |
| #io-channel-cells = <1>; |
| has-temp-channel; |
| has-vref-channel; |
| }; |
| |
| can { |
| compatible = "bosch,m_can-base"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| std-filter-elements = <28>; |
| ext-filter-elements = <8>; |
| rx-fifo0-elements = <3>; |
| rx-fifo1-elements = <3>; |
| rx-buffer-elements = <0>; |
| tx-buffer-elements = <3>; |
| |
| can1: can@4000a400 { |
| compatible = "st,stm32-fdcan"; |
| reg = <0x4000a400 0x400>, <0x4000ac00 0x350>; |
| reg-names = "m_can", "message_ram"; |
| interrupts = <39 0>, <40 0>; |
| interrupt-names = "LINE_0", "LINE_1"; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>; |
| status = "disabled"; |
| sjw = <1>; |
| sample-point = <875>; |
| sjw-data = <1>; |
| sample-point-data = <875>; |
| }; |
| }; |
| |
| ucpd1: ucpd@4000dc00 { |
| compatible = "st,stm32-ucpd"; |
| reg = <0x4000dc00 0x400>; |
| clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>; |
| interrupts = <106 0>; |
| status = "disabled"; |
| }; |
| |
| gpdma1: dma@40020000 { |
| compatible = "st,stm32u5-dma"; |
| #dma-cells = <3>; |
| reg = <0x40020000 0x400>; |
| interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0 |
| 80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>; |
| clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>; |
| dma-channels = <16>; |
| dma-requests = <114>; |
| dma-offset = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| die_temp: dietemp { |
| compatible = "st,stm32-temp-cal"; |
| ts-cal1-addr = <0x0BFA0710>; |
| ts-cal2-addr = <0x0BFA0742>; |
| ts-cal1-temp = <30>; |
| ts-cal2-temp = <130>; |
| ts-cal-vrefanalog = <3000>; |
| ts-cal-resolution = <14>; |
| io-channels = <&adc1 19>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &nvic { |
| arm,num-irq-priority-bits = <4>; |
| }; |
