dts/riscv/rv32m1_ri5cy.dtsi

/*
 * Copyright 2018 Foundries.io Ltd
 * SPDX-License-Identifier: Apache-2.0
 */

#include <riscv/rv32m1.dtsi>

/ {
	aliases {
		intmux = &intmux0;
		system-lptmr = &lptmr0;
	};

	cpus {
		/delete-node/ cpu@1;
	};
};

&m4_flash {
	partitions {
		compatible = "fixed-partitions";
		#address-cells = <1>;
		#size-cells = <1>;

		/* This configuration assumes the Arm cores are disabled, as
		 * these base addresses contain the Arm core vector tables if
		 * they are used.
		 */

		ri5cy_code_partition: partition@0 {
			label = "ri5cy-code";
			reg = <0x00000000 0x000fff00>;
		};

		ri5cy_vector_partition: partition@fff00 {
			label = "ri5cy-vector";
			reg = <0x000fff00 0x100>;
		};
	};
};

/*
 * INTMUX channels below are somewhat arbitrary.
 *
 * The system timer (assumed at LPTMR0) is placed on channel 0, and peripherals
 * are in channel 1. This can be overridden with overlays, e.g. to manage IRQ
 * priorities, and it will Just Work, but using fewer channels here allows
 * disabling unused ones in Kconfig, making the binary smaller.
 *
 * Each enabled channel requires 256 bytes in _sw_isr_table, so the savings for
 * disabling channels can add up.
 */

&intmux0 {
	interrupt-parent = <&event0>;
	interrupts = <INTMUX_CH0_IRQ>, <INTMUX_CH1_IRQ>, <INTMUX_CH2_IRQ>, <INTMUX_CH3_IRQ>, <INTMUX_CH4_IRQ>, <INTMUX_CH5_IRQ>, <INTMUX_CH6_IRQ>, <INTMUX_CH7_IRQ>;
	status = "okay";
};

&lptmr0 {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH0, 7)>;
};

&lptmr1 {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 8)>;
};

&lptmr2 {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 22)>;
};

&gpioa {
	interrupt-parent = <&event0>;
	interrupts = <18>;
};

&gpiob {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 15)>;
};

&gpioc {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 16)>;
};

&gpiod {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 17)>;
};

&gpioe {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 27)>;
};

&uart0 {
	interrupt-parent = <&event0>;
	interrupts = <17>;
};

&uart1 {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 13)>;
};

&uart2 {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 14)>;
};

&uart3 {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 26)>;
};

&i2c0 {
	interrupt-parent = <&event0>;
	interrupts = <15>;
};

&i2c1 {
	interrupt-parent = <&event0>;
	interrupts = <16>;
};

&i2c2 {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 11)>;
};

&i2c3 {
	interrupt-parent = <&intmux0>;
	interrupts = <INTMUX_LEVEL2_IRQ(INTMUX_CH1, 24)>;
};