soc: riscv: riscv-privilege: opentitan: Enable watchdog reset function
Adds watchdog reset as a reset source at SoC init. This is achieved by:
1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog
reset is enabled.
2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change.
3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the
change has been processed.
This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled. Note that the timer itself is not enabled here, only the
reset function.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
diff --git a/soc/riscv/riscv-privilege/opentitan/soc.c b/soc/riscv/riscv-privilege/opentitan/soc.c
index eb7b671..0b04079 100644
--- a/soc/riscv/riscv-privilege/opentitan/soc.c
+++ b/soc/riscv/riscv-privilege/opentitan/soc.c
@@ -8,10 +8,18 @@
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
+#define PWRMGR_BASE (DT_REG_ADDR(DT_NODELABEL(pwrmgr)))
#define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer)))
static int soc_opentitan_init(void)
{
+ /* Enable the watchdog reset (bit 1). */
+ sys_write32(2u, PWRMGR_BASE + PWRMGR_RESET_EN_REG_OFFSET);
+ /* Write CFG_CDC_SYNC to commit change. */
+ sys_write32(1u, PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET);
+ /* Poll CFG_CDC_SYNC register until it reads 0. */
+ while (sys_read32(PWRMGR_BASE + PWRMGR_CFG_CDC_SYNC_REG_OFFSET)) {
+ }
/* Initialize the Machine Timer, so it behaves as a regular one. */
sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET);
diff --git a/soc/riscv/riscv-privilege/opentitan/soc.h b/soc/riscv/riscv-privilege/opentitan/soc.h
index 4760c99..13bb5c4 100644
--- a/soc/riscv/riscv-privilege/opentitan/soc.h
+++ b/soc/riscv/riscv-privilege/opentitan/soc.h
@@ -10,6 +10,11 @@
#include <soc_common.h>
#include <zephyr/devicetree.h>
+/* OpenTitan power management regs. */
+#define PWRMGR_CFG_CDC_SYNC_REG_OFFSET 0x018
+#define PWRMGR_RESET_EN_REG_OFFSET 0x02c
+#define PWRMGR_RESET_EN_WDOG_SRC_MASK 0x002
+
/* Ibex timer registers. */
#define RV_TIMER_CTRL_REG_OFFSET 0x004
#define RV_TIMER_INTR_ENABLE_REG_OFFSET 0x100
