| * Copyright (c) 2017 Intel Corporation. |
| * SPDX-License-Identifier: Apache-2.0 |
| #include <dt-bindings/interrupt-controller/intel-ioapic.h> |
| compatible = "intel,x86"; |
| d-cache-line-size = <64>; |
| compatible = "intel,ioapic"; |
| reg = <0xfec00000 0x1000>; |
| reg = <DT_DRAM_BASE DT_DRAM_SIZE>; |
| compatible = "simple-bus"; |
| reg = <0x000003f8 0x100>; |
| clock-frequency = <1843200>; |
| interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>; |
| interrupt-parent = <&intc>; |
| reg = <0x000002f8 0x100>; |
| clock-frequency = <1843200>; |
| interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>; |
| interrupt-parent = <&intc>; |
| compatible = "intel,hpet"; |
| reg = <0xfed00000 0x400>; |
| interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; |
| interrupt-parent = <&intc>; |