blob: f4f121660f03386a2c2cd3c00f42c53bcd060aa5 [file] [log] [blame]
/*
* Copyright (c) 2021 SILA Embedded Solutions GmbH
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/h7/stm32h7.dtsi>
/ {
soc {
flash-controller@52002000 {
flash0: flash@8000000 {
write-block-size = <32>;
erase-block-size = <DT_SIZE_K(128)>;
};
};
uart9: serial@40011800 {
compatible = "st,stm32-uart";
reg = <0x40011800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
interrupts = <155 0>;
status = "disabled";
label = "UART_9";
};
usart10: serial@40011c00 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
interrupts = <156 0>;
status = "disabled";
label = "UART_10";
};
dmamux1: dmamux@40020800 {
dma-requests= <129>;
};
cryp: cryp@48021000 {
compatible = "st,stm32-cryp";
reg = <0x48021000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
interrupts = <79 0>;
status = "disabled";
label = "CRYP";
};
rng: rng@48021800 {
health-test-magic = <0x17590abc>;
health-test-config = <0xaa74>;
};
ltdc: display-controller@50001000 {
compatible = "st,stm32-ltdc";
reg = <0x50001000 0x200>;
interrupts = <88 0>, <89 0>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x000000008>;
label = "LTDC";
status = "disabled";
};
};
/* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */
sram0: memory@24000000 {
reg = <0x24000000 DT_SIZE_K(320)>;
compatible = "mmio-sram";
};
/* System data RAM accessible over AHB bus: SRAM1 in D2 domain */
sram1: memory@30000000 {
reg = <0x30000000 DT_SIZE_K(16)>;
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM1";
};
/* System data RAM accessible over AHB bus: SRAM2 in D2 domain */
sram2: memory@30040000 {
reg = <0x30040000 DT_SIZE_K(16)>;
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM2";
};
/* System data RAM accessible over AHB bus: SRAM4 in D3 domain */
sram4: memory@38000000 {
reg = <0x38000000 DT_SIZE_K(16)>;
compatible = "zephyr,memory-region", "mmio-sram";
zephyr,memory-region = "SRAM4";
};
dtcm: memory@20000000 {
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};
};