boards: mimxrt1160_evk: Update RT1160 documentation for dual core support
Update rt1160 documentation for dual core support
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
diff --git a/boards/arm/mimxrt1160_evk/doc/index.rst b/boards/arm/mimxrt1160_evk/doc/index.rst
index 5037ac8..1bd33e5 100644
--- a/boards/arm/mimxrt1160_evk/doc/index.rst
+++ b/boards/arm/mimxrt1160_evk/doc/index.rst
@@ -172,6 +172,35 @@
| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm |
+---------------+-----------------+---------------------------+
+
+Dual Core samples
+*****************
+
++-----------+------------------+----------------------------+
+| Core | Boot Address | Comment |
++===========+==================+============================+
+| Cortex M7 | 0x30000000[630K] | primary core |
++-----------+------------------+----------------------------+
+| Cortex M4 | 0x20020000[96k] | boots from OCRAM |
++-----------+------------------+----------------------------+
+
++----------+------------------+-----------------------+
+| Memory | Address[Size] | Comment |
++==========+==================+=======================+
+| flexspi1 | 0x30000000[16M] | Cortex M7 flash |
++----------+------------------+-----------------------+
+| sdram0 | 0x80030000[64M] | Cortex M7 ram |
++----------+------------------+-----------------------+
+| ocram | 0x20020000[512K] | Cortex M4 "flash" |
++----------+------------------+-----------------------+
+| sram1 | 0x20000000[128K] | Cortex M4 ram |
++----------+------------------+-----------------------+
+| ocram2 | 0x200C0000[512K] | Mailbox/shared memory |
++----------+------------------+-----------------------+
+
+Only the first 16K of ocram2 has the correct MPU region attributes set to be
+used as shared memory
+
System Clock
============
@@ -190,6 +219,20 @@
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
+Building a Dual-Core Image
+==========================
+Dual core samples load the M4 core image from flash into the shared ``ocram``
+region. The M7 core then sets the M4 boot address to this region. The only
+sample currently enabled for dual core builds is the ``openamp`` sample.
+To flash a dual core sample, the M4 image must be flashed first, so that it is
+written to flash. Then, the M7 image must be flashed. The openamp sysbuild
+sample will do this automatically by setting the image order.
+
+The secondary core can be debugged normally in single core builds
+(where the target is ``mimxrt1160_evk_cm4``). For dual core builds, the
+secondary core should be placed into a loop, then a debugger can be attached
+(see `AN13264`_, section 4.2.3 for more information)
+
Configuring a Debug Probe
=========================
@@ -285,3 +328,6 @@
.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK:
https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760
+
+.. _AN13264:
+ https://www.nxp.com/docs/en/application-note/AN13264.pdf
