arm64: cache: Rework cache API
And use the new API.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
diff --git a/arch/arm64/core/cache.c b/arch/arm64/core/cache.c
index d5aefaf..b55e59e 100644
--- a/arch/arm64/core/cache.c
+++ b/arch/arm64/core/cache.c
@@ -13,6 +13,7 @@
* This module contains functions for manipulation of the d-cache.
*/
+#include <zephyr/arch/arm64/cache.h>
#include <zephyr/cache.h>
#define CTR_EL0_DMINLINE_SHIFT 16
@@ -65,7 +66,7 @@
* K_CACHE_WB: clean
* K_CACHE_WB_INVD: clean and invalidate
*/
-int arch_dcache_range(void *addr, size_t size, int op)
+int arm64_dcache_range(void *addr, size_t size, int op)
{
size_t line_size;
uintptr_t start_addr = (uintptr_t)addr;
@@ -136,7 +137,7 @@
* K_CACHE_WB: clean
* K_CACHE_WB_INVD: clean and invalidate
*/
-int arch_dcache_all(int op)
+int arm64_dcache_all(int op)
{
uint32_t clidr_el1, csselr_el1, ccsidr_el1;
uint8_t loc, ctype, cache_level, line_size, way_pos;
@@ -206,13 +207,3 @@
return 0;
}
-
-int arch_icache_range(void *addr, size_t size, int op)
-{
- return -ENOTSUP;
-}
-
-int arch_icache_all(int op)
-{
- return -ENOTSUP;
-}
diff --git a/arch/arm64/core/mmu.c b/arch/arm64/core/mmu.c
index 02b281b..a37ea48 100644
--- a/arch/arm64/core/mmu.c
+++ b/arch/arm64/core/mmu.c
@@ -804,7 +804,7 @@
isb();
/* Invalidate all data caches before enable them */
- sys_cache_data_all(K_CACHE_INVD);
+ sys_cache_data_invd_all();
/* Enable the MMU and data cache */
val = read_sctlr_el1();
diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c
index 97565fb..a868611 100644
--- a/arch/arm64/core/smp.c
+++ b/arch/arm64/core/smp.c
@@ -92,9 +92,8 @@
/* store mpid last as this is our synchronization point */
arm64_cpu_boot_params.mpid = cpu_mpid;
- arch_dcache_range((void *)&arm64_cpu_boot_params,
- sizeof(arm64_cpu_boot_params),
- K_CACHE_WB_INVD);
+ sys_cache_data_invd_range((void *)&arm64_cpu_boot_params,
+ sizeof(arm64_cpu_boot_params));
if (pm_cpu_on(cpu_mpid, (uint64_t)&__start)) {
printk("Failed to boot secondary CPU core %d (MPID:%#llx)\n",
diff --git a/include/zephyr/arch/arm64/cache.h b/include/zephyr/arch/arm64/cache.h
new file mode 100644
index 0000000..a4a155b
--- /dev/null
+++ b/include/zephyr/arch/arm64/cache.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2022 Carlo Caione <ccaione@baylibre.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_CACHE_H_
+#define ZEPHYR_INCLUDE_ARCH_ARM64_CACHE_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <zephyr/types.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/arch/cpu.h>
+#include <errno.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define K_CACHE_WB BIT(0)
+#define K_CACHE_INVD BIT(1)
+#define K_CACHE_WB_INVD (K_CACHE_WB | K_CACHE_INVD)
+
+#if defined(CONFIG_DCACHE)
+
+extern int arm64_dcache_range(void *addr, size_t size, int op);
+extern int arm64_dcache_all(int op);
+
+extern size_t arch_dcache_line_size_get(void);
+
+int ALWAYS_INLINE arch_dcache_flush_all(void)
+{
+ return arm64_dcache_all(K_CACHE_WB);
+}
+
+int ALWAYS_INLINE arch_dcache_invd_all(void)
+{
+ return arm64_dcache_all(K_CACHE_INVD);
+}
+
+int ALWAYS_INLINE arch_dcache_flush_and_invd_all(void)
+{
+ return arm64_dcache_all(K_CACHE_WB_INVD);
+}
+
+int ALWAYS_INLINE arch_dcache_flush_range(void *addr, size_t size)
+{
+ return arm64_dcache_range(addr, size, K_CACHE_WB);
+}
+
+int ALWAYS_INLINE arch_dcache_invd_range(void *addr, size_t size)
+{
+ return arm64_dcache_range(addr, size, K_CACHE_INVD);
+}
+
+int ALWAYS_INLINE arch_dcache_flush_and_invd_range(void *addr, size_t size)
+{
+ return arm64_dcache_range(addr, size, K_CACHE_WB_INVD);
+}
+
+void ALWAYS_INLINE arch_dcache_enable(void)
+{
+ /* nothing */
+}
+
+void ALWAYS_INLINE arch_dcache_disable(void)
+{
+ /* nothing */
+}
+
+#endif /* CONFIG_DCACHE */
+
+#if defined(CONFIG_ICACHE)
+
+size_t arch_icache_line_size_get(void)
+{
+ return -ENOTSUP;
+}
+
+int ALWAYS_INLINE arch_icache_flush_all(void)
+{
+ return -ENOTSUP;
+}
+
+int ALWAYS_INLINE arch_icache_invd_all(void)
+{
+ return -ENOTSUP;
+}
+
+int ALWAYS_INLINE arch_icache_flush_and_invd_all(void)
+{
+ return -ENOTSUP;
+}
+
+int ALWAYS_INLINE arch_icache_flush_range(void *addr, size_t size)
+{
+ return -ENOTSUP;
+}
+
+int ALWAYS_INLINE arch_icache_invd_range(void *addr, size_t size)
+{
+ return -ENOTSUP;
+}
+
+int ALWAYS_INLINE arch_icache_flush_and_invd_range(void *addr, size_t size)
+{
+ return -ENOTSUP;
+}
+
+void ALWAYS_INLINE arch_icache_enable(void)
+{
+ /* nothing */
+}
+
+void ALWAYS_INLINE arch_icache_disable(void)
+{
+ /* nothing */
+}
+
+#endif /* CONFIG_ICACHE */
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_CACHE_H_ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASMLANGUAGE */
