boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp.dts

/*
 * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;
#include <nordic/nrf54l15_cpuapp.dtsi>
#include "ophelia4ev_common.dtsi"

/ {
	model = "Ophelia-IV EV Application MCU";
	compatible = "we,ophelia4ev_nrf54l15-cpuapp";

	chosen {
		zephyr,console = &uart20;
		zephyr,shell-uart = &uart20;
		zephyr,uart-mcumgr = &uart20;
		zephyr,bt-mon-uart = &uart20;
		zephyr,bt-c2h-uart = &uart20;
		zephyr,flash-controller = &rram_controller;
		zephyr,flash = &cpuapp_rram;
		zephyr,ieee802154 = &ieee802154;
		zephyr,boot-mode = &boot_mode0;
		zephyr,code-partition = &slot0_partition;
		zephyr,sram = &cpuapp_sram;
	};

	aliases {
		mcuboot-button0 = &button0;
		mcuboot-led0 = &led0;
	};
};

&cpuapp_sram {
	status = "okay";
};

&lfxo {
	load-capacitors = "internal";
	load-capacitance-femtofarad = <17000>;
};

&hfxo {
	load-capacitors = "internal";
	load-capacitance-femtofarad = <15000>;
};

&regulators {
	status = "okay";
};

&vregmain {
	status = "okay";

	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};

&grtc {
	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;

	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
	child-owned-channels = <3 4 7 8 9 10 11>;

	status = "okay";
};

&uart20 {
	status = "okay";
};

&nfct {
	status = "okay";
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&gpiote20 {
	status = "okay";
};

&gpiote30 {
	status = "okay";
};

&radio {
	status = "okay";
};

&ieee802154 {
	status = "okay";
};

&temp {
	status = "okay";
};

&clock {
	status = "okay";
};

&gpregret1 {
	status = "okay";

	boot_mode0: boot_mode@0 {
		compatible = "zephyr,retention";
		status = "okay";
		reg = <0x0 0x1>;
	};
};

&spi00 {
	status = "okay";

	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
	pinctrl-0 = <&spi00_default>;
	pinctrl-1 = <&spi00_sleep>;
	pinctrl-names = "default", "sleep";

	mx25r64: mx25r6435f@0 {
		compatible = "jedec,spi-nor";
		status = "okay";
		reg = <0>;
		spi-max-frequency = <8000000>;

		jedec-id = [c2 28 17];

		sfdp-bfp = [e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
			    ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
			    10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 48 44
			    30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff];

		size = <67108864>;
		has-dpd;
		t-enter-dpd = <10000>;
		t-exit-dpd = <35000>;
		reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
	};
};

&adc {
	status = "okay";
};

/* Include default memory partition configuration file */
#include <nordic/nrf54l15_partition.dtsi>