drivers/clock_control/Kconfig.stm32f10x

# Kconfig - STM32F1 MCU clock control driver config
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#

if SOC_SERIES_STM32F1X

menuconfig CLOCK_CONTROL_STM32F10X
	bool
	prompt "STM32F10x Reset & Clock Control"
	depends on CLOCK_CONTROL && SOC_SERIES_STM32F1X
	default y if SOC_SERIES_STM32F1X
	help
	 Enable driver for Reset & Clock Control subsystem found
	 in STM32F1 family of MCUs

config CLOCK_CONTROL_STM32F10X_DEVICE_INIT_PRIORITY
	int "Clock Control Device Priority"
	default 1
	depends on CLOCK_CONTROL_STM32F10X
	help
	 This option controls the priority of clock control
	 device initialization. Higher priority ensures that the device
	 is initialized earlier in the startup cycle. If unsure, leave
	 at default value 1

choice
prompt "STM32F10x System Clock Source"
depends on CLOCK_CONTROL_STM32F10X

config CLOCK_STM32F10X_SYSCLK_SRC_HSI
	bool "HSI"
	help
	 Use HSI as source of SYSCLK

config CLOCK_STM32F10X_SYSCLK_SRC_HSE
	bool "HSE"
	help
	 Use HSE as source of SYSCLK

config CLOCK_STM32F10X_SYSCLK_SRC_PLL
	bool "PLL"
	help
	 Use PLL as source of SYSCLK

endchoice

choice
prompt "STM32F10x PLL Clock Source"
depends on CLOCK_CONTROL_STM32F10X && CLOCK_STM32F10X_SYSCLK_SRC_PLL

config CLOCK_STM32F10X_PLL_SRC_HSI
	bool "HSI"
	help
	 Use HSI as source of PLL

config CLOCK_STM32F10X_PLL_SRC_HSE
	bool "HSE"
	help
	 Use HSE as source of PLL

endchoice

config CLOCK_STM32F10X_HSE_BYPASS
	bool "HSE bypass"
	depends on CLOCK_CONTROL_STM32F10X && (CLOCK_STM32F10X_PLL_SRC_HSE || CLOCK_STM32F10X_SYSCLK_SRC_HSE)
	help
	 Enable this option to bypass external high-speed clock (HSE).

config CLOCK_STM32F10X_PLL_XTPRE
	bool "HSE to PLL /2 prescaler"
	depends on CLOCK_CONTROL_STM32F10X && CLOCK_STM32F10X_PLL_SRC_HSE
	help
	 Enable this option to enable /2 prescaler on HSE to PLL clock signal

config CLOCK_STM32F10X_PLL_MULTIPLIER
	int "PLL multiplier"
	depends on CLOCK_CONTROL_STM32F10X && CLOCK_STM32F10X_SYSCLK_SRC_PLL
	default 9
	range 2 16
	help
	 PLL multiplier, allowed values: 2-16. PLL output must not exceed 72MHz.

config CLOCK_STM32F10X_AHB_PRESCALER
	int "AHB prescaler"
	depends on CLOCK_CONTROL_STM32F10X
	default 0
	range 0 512
	help
	 AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
	 256, 512.

config CLOCK_STM32F10X_APB1_PRESCALER
	int "APB1 prescaler"
	depends on CLOCK_CONTROL_STM32F10X
	default 0
	range 0 16
	help
	 APB1 Low speed clock (PCLK1) prescaler, allowed values:
	 0, 2, 4, 8, 16. The APB1 clock must not exceed 36MHz.

config CLOCK_STM32F10X_APB2_PRESCALER
	int "APB2 prescaler"
	depends on CLOCK_CONTROL_STM32F10X
	default 0
	range 0 16
	help
	 APB2 High speed clock (PCLK2) prescaler, allowed values:
	 0, 2, 4, 8, 16

endif