| /* |
| * SPDX-License-Identifier: Apache-2.0 |
| * |
| * Copyright (C) 2021, Intel Corporation |
| * |
| */ |
| |
| #include <arm64/armv8-a.dtsi> |
| #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| cpus { |
| #address-cells = <1>; |
| #size-cells= <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0>; |
| }; |
| }; |
| |
| gic: interrupt-controller@fffc1000 { |
| compatible = "arm,gic"; |
| reg = <0xfffc1000 0x1000>, |
| <0xfffc2000 0x2000>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| label = "gic"; |
| status = "okay"; |
| }; |
| |
| arch_timer: timer { |
| compatible = "arm,armv8-timer"; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_PPI 29 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 30 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 27 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>, |
| <GIC_PPI 26 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| label = "arch_timer"; |
| }; |
| |
| sysmgr: sysmgr@ffd12000 { |
| compatible = "syscon"; |
| reg = <0xffd12000 0x1000>; |
| label = "sysmgr"; |
| }; |
| |
| clock: clock@ffd10000 { |
| compatible = "intel,agilex-clock"; |
| reg = <0xffd10000 0x1000>; |
| #clock-cells = <1>; |
| label = "clock"; |
| }; |
| |
| mem0: memory@10000000 { |
| device_type = "memory"; |
| reg = <0x10000000 0x40000>; |
| label = "mem_0"; |
| }; |
| |
| uart0: uart@ffc02000 { |
| compatible = "ns16550"; |
| reg-shift = <2>; |
| reg = <0xffc02000 0x100>; |
| interrupt-parent = <&gic>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL |
| IRQ_DEFAULT_PRIORITY>; |
| interrupt-names = "irq_0"; |
| clock-frequency = <100000000>; |
| label = "uart_0"; |
| status = "disabled"; |
| }; |
| }; |