blob: 6bf9994d088cf81c6adc129f16d840d05c05ca02 [file] [log] [blame]
/*
* Copyright (c) 2023 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/intel-ioapic.h>
#include <dt-bindings/i2c/i2c.h>
#include <mem.h>
/ {
chosen {
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu0@0 {
device_type = "cpu";
compatible = "intel,ish";
reg = <0>;
};
};
intc: ioapic@fec00000 {
compatible = "intel,ioapic";
reg = <0xfec00000 0x100000>;
interrupt-controller;
#interrupt-cells = <3>;
};
sram: memory@ff200000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xff200000 DT_SIZE_K(640)>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
hpet: hpet@4700000{
compatible = "intel,hpet";
reg = <0x04700000 0x400>;
interrupt-parent = <&intc>;
interrupts = <14 IRQ_TYPE_FIXED_LEVEL_HIGH 2>;
status = "okay";
};
uart0: uart@8100000 {
compatible = "intel,sedi-uart";
reg = <0x08100000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <23 IRQ_TYPE_LOWEST_EDGE_RISING 6>;
peripheral-id = <0>;
current-speed = <115200>;
status = "okay";
};
i2c0: i2c@0 {
compatible = "intel,sedi-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x1000>;
peripheral-id = <0>;
interrupt-parent = <&intc>;
interrupts = <15 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";
};
i2c1: i2c@2000 {
compatible = "intel,sedi-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00002000 0x1000>;
peripheral-id = <1>;
interrupt-parent = <&intc>;
interrupts = <16 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";
};
i2c2: i2c@4000 {
compatible = "intel,sedi-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00004000 0x1000>;
peripheral-id = <2>;
interrupt-parent = <&intc>;
interrupts = <17 IRQ_TYPE_LOWEST_LEVEL_HIGH 2>;
clock-frequency = <I2C_BITRATE_FAST>;
status = "disabled";
};
};
};