soc/riscv/riscv-privilege/mpfs/Kconfig.defconfig.series

# Copyright (c) 2020-2021 Microchip Technology Inc
# SPDX-License-Identifier: Apache-2.0

if SOC_SERIES_RISCV64_MIV

config SOC_SERIES
	default "mpfs"

# MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock...

config SYS_CLOCK_HW_CYCLES_PER_SEC
	default 1000000

config RISCV_SOC_INTERRUPT_INIT
	default y

config RISCV_HAS_CPU_IDLE
	default y

config RISCV_HAS_PLIC
	default y

config RISCV_GP
	default y

config 2ND_LVL_ISR_TBL_OFFSET
	default 13

config 2ND_LVL_INTR_00_OFFSET
	default 11

config MAX_IRQ_PER_AGGREGATOR
	default 30

config NUM_IRQS
	default 187

# config NO_OPTIMIZATIONS
#	default y

endif # SOC_SERIES_RISCV64_MIV