| # Copyright 2022 NXP |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| if BOARD_S32Z270DC2_RTU0_R52 || BOARD_S32Z270DC2_RTU1_R52 |
| |
| config BUILD_OUTPUT_BIN |
| default n |
| |
| config BOARD |
| default "s32z270dc2_rtu0_r52" if BOARD_S32Z270DC2_RTU0_R52 |
| default "s32z270dc2_rtu1_r52" if BOARD_S32Z270DC2_RTU1_R52 |
| |
| config NXP_S32_RTU_INDEX |
| default 0 if BOARD_S32Z270DC2_RTU0_R52 |
| default 1 if BOARD_S32Z270DC2_RTU1_R52 |
| |
| if SERIAL |
| |
| config UART_INTERRUPT_DRIVEN |
| default y |
| |
| config UART_CONSOLE |
| default y |
| |
| endif # SERIAL |
| |
| if SHELL |
| |
| config SHELL_STACK_SIZE |
| default 4096 |
| |
| endif # SHELL |
| |
| endif # BOARD_S32Z270DC2_RTU0_R52 || BOARD_S32Z270DC2_RTU1_R52 |
