soc: arch: synopsys: move timer0/1 IRQ information to DT timer0/1 IRQ information was hardcoded in soc.h, however, Devicetree is nowadays a better place to describe hardware. Note that I have followed existing upstream Linux code to do these changes. Ref. - https://elixir.bootlin.com/linux/latest/source/arch/arc/boot/dts/ hsdk.dts - https://elixir.bootlin.com/linux/latest/source/Documentation/ devicetree/bindings/timer/snps,arc-timer.txt Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
diff --git a/boards/arc/nsim/nsim.dtsi b/boards/arc/nsim/nsim.dtsi index 7c0a570..2cbc927 100644 --- a/boards/arc/nsim/nsim.dtsi +++ b/boards/arc/nsim/nsim.dtsi
@@ -21,6 +21,18 @@ #interrupt-cells = <2>; }; + timer0: timer0 { + compatible = "snps,arc-timer"; + interrupts = <16 1>; + interrupt-parent = <&intc>; + }; + + timer1: timer1 { + compatible = "snps,arc-timer"; + interrupts = <17 1>; + interrupt-parent = <&intc>; + }; + uart0: uart@f0000000 { compatible = "ns16550"; clock-frequency = <50000000>;
diff --git a/boards/arc/qemu_arc/qemu_arc.dtsi b/boards/arc/qemu_arc/qemu_arc.dtsi index a9615a9..740dd54 100644 --- a/boards/arc/qemu_arc/qemu_arc.dtsi +++ b/boards/arc/qemu_arc/qemu_arc.dtsi
@@ -24,6 +24,18 @@ #interrupt-cells = <2>; }; + timer0: timer0 { + compatible = "snps,arc-timer"; + interrupts = <16 1>; + interrupt-parent = <&intc>; + }; + + timer1: timer1 { + compatible = "snps,arc-timer"; + interrupts = <17 1>; + interrupt-parent = <&intc>; + }; + /* We are carving out of DRAM for a pseudo flash and sram region */ flash0: flash@80000000 { compatible = "soc-nv-flash";
diff --git a/drivers/timer/arcv2_timer0.c b/drivers/timer/arcv2_timer0.c index ba72925..04cf077 100644 --- a/drivers/timer/arcv2_timer0.c +++ b/drivers/timer/arcv2_timer0.c
@@ -23,13 +23,14 @@ #undef _ARC_V2_TMR0_COUNT #undef _ARC_V2_TMR0_CONTROL #undef _ARC_V2_TMR0_LIMIT -#undef IRQ_TIMER0 #define _ARC_V2_TMR0_COUNT _ARC_V2_S_TMR0_COUNT #define _ARC_V2_TMR0_CONTROL _ARC_V2_S_TMR0_CONTROL #define _ARC_V2_TMR0_LIMIT _ARC_V2_S_TMR0_LIMIT #define IRQ_TIMER0 IRQ_SEC_TIMER0 +#else +#define IRQ_TIMER0 DT_IRQN(DT_NODELABEL(timer0)) #endif #define _ARC_V2_TMR_CTRL_IE 0x1 /* interrupt enable */
diff --git a/dts/arc/synopsys/arc_hsdk.dtsi b/dts/arc/synopsys/arc_hsdk.dtsi index 92cb07e..fc29fd7 100644 --- a/dts/arc/synopsys/arc_hsdk.dtsi +++ b/dts/arc/synopsys/arc_hsdk.dtsi
@@ -54,6 +54,18 @@ interrupt-parent = <&intc>; }; + timer0: timer0 { + compatible = "snps,arc-timer"; + interrupts = <16 1>; + interrupt-parent = <&intc>; + }; + + timer1: timer1 { + compatible = "snps,arc-timer"; + interrupts = <17 1>; + interrupt-parent = <&intc>; + }; + soc { #address-cells = <1>; #size-cells = <1>;
diff --git a/dts/arc/synopsys/arc_iot.dtsi b/dts/arc/synopsys/arc_iot.dtsi index 83e34a4..8e8450f 100644 --- a/dts/arc/synopsys/arc_iot.dtsi +++ b/dts/arc/synopsys/arc_iot.dtsi
@@ -27,6 +27,12 @@ #interrupt-cells = <2>; }; + timer0: timer0 { + compatible = "snps,arc-timer"; + interrupts = <16 1>; + interrupt-parent = <&intc>; + }; + iccm0: iccm@20000000 { compatible = "arc,iccm"; reg = <0x20000000 0x40000>;
diff --git a/dts/arc/synopsys/emsdp.dtsi b/dts/arc/synopsys/emsdp.dtsi index 8265376..45a7fdd 100644 --- a/dts/arc/synopsys/emsdp.dtsi +++ b/dts/arc/synopsys/emsdp.dtsi
@@ -29,6 +29,12 @@ #interrupt-cells = <2>; }; + timer0: timer0 { + compatible = "snps,arc-timer"; + interrupts = <16 1>; + interrupt-parent = <&intc>; + }; + iccm0: iccm@60000000 { compatible = "arc,iccm"; reg = <0x60000000 0x20000>;
diff --git a/dts/arc/synopsys/emsk.dtsi b/dts/arc/synopsys/emsk.dtsi index 17b2084..e9200df 100644 --- a/dts/arc/synopsys/emsk.dtsi +++ b/dts/arc/synopsys/emsk.dtsi
@@ -28,6 +28,18 @@ #interrupt-cells = <2>; }; + timer0: timer0 { + compatible = "snps,arc-timer"; + interrupts = <16 1>; + interrupt-parent = <&intc>; + }; + + timer1: timer1 { + compatible = "snps,arc-timer"; + interrupts = <17 1>; + interrupt-parent = <&intc>; + }; + sysclk: system-clock { compatible = "fixed-clock"; clock-frequency = <DT_APB_CLK_HZ>;
diff --git a/dts/bindings/timer/snps,arc-timer.yaml b/dts/bindings/timer/snps,arc-timer.yaml new file mode 100644 index 0000000..29bb544 --- /dev/null +++ b/dts/bindings/timer/snps,arc-timer.yaml
@@ -0,0 +1,13 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +description: | + Synopsys ARC Local Timer with Interrupt Capabilities + +compatible: "snps,arc-timer" + +include: base.yaml + +properties: + interrupts: + required: true
diff --git a/samples/boards/arc_secure_services/src/main.c b/samples/boards/arc_secure_services/src/main.c index 2160065..ac7b9be 100644 --- a/samples/boards/arc_secure_services/src/main.c +++ b/samples/boards/arc_secure_services/src/main.c
@@ -6,7 +6,7 @@ #include <zephyr/zephyr.h> #include <zephyr/sys/printk.h> -#include <soc.h> +#include <zephyr/devicetree.h> #if defined(CONFIG_SOC_NSIM_SEM) #define NORMAL_FIRMWARE_ENTRY 0x40000 @@ -45,8 +45,8 @@ int32_t i = 0; /* allocate timer 0 and timer1 to normal mode */ - z_arc_v2_irq_uinit_secure_set(IRQ_TIMER0, 0); - z_arc_v2_irq_uinit_secure_set(IRQ_TIMER1, 0); + z_arc_v2_irq_uinit_secure_set(DT_IRQN(DT_NODELABEL(timer0)), 0); + z_arc_v2_irq_uinit_secure_set(DT_IRQN(DT_NODELABEL(timer1)), 0); /* disable the secure interrupts for debug purpose*/ /* _arc_v2_irq_unit_int_disable(IRQ_S_TIMER0); */
diff --git a/soc/arc/snps_arc_hsdk/soc.h b/soc/arc/snps_arc_hsdk/soc.h index c88ccc7..34da96e 100644 --- a/soc/arc/snps_arc_hsdk/soc.h +++ b/soc/arc/snps_arc_hsdk/soc.h
@@ -18,8 +18,6 @@ /* ARC HS Core IRQs */ -#define IRQ_TIMER0 16 -#define IRQ_TIMER1 17 #define IRQ_ICI 19 #ifndef _ASMLANGUAGE
diff --git a/soc/arc/snps_arc_iot/soc.h b/soc/arc/snps_arc_iot/soc.h index 34c1643..931e1ab 100644 --- a/soc/arc/snps_arc_iot/soc.h +++ b/soc/arc/snps_arc_iot/soc.h
@@ -20,8 +20,6 @@ #define SYSCLK_DEFAULT_IOSC_HZ MHZ(16) /* ARC EM Core IRQs */ -#define IRQ_TIMER0 16 -#define IRQ_TIMER1 17 #include "soc_irq.h" #define BASE_ADDR_SYSCONFIG 0xF000A000
diff --git a/soc/arc/snps_emsdp/soc.h b/soc/arc/snps_emsdp/soc.h index 07ba548..97eebe3 100644 --- a/soc/arc/snps_emsdp/soc.h +++ b/soc/arc/snps_emsdp/soc.h
@@ -20,8 +20,6 @@ #define SYSCLK_DEFAULT_IOSC_HZ MHZ(100) /* ARC EM Core IRQs */ -#define IRQ_TIMER0 16 - #define IRQ_SEC_TIMER0 20 #ifndef _ASMLANGUAGE
diff --git a/soc/arc/snps_emsk/soc.h b/soc/arc/snps_emsk/soc.h index e7c689d..3bca637 100644 --- a/soc/arc/snps_emsk/soc.h +++ b/soc/arc/snps_emsk/soc.h
@@ -21,9 +21,6 @@ #define SYSCLK_DEFAULT_IOSC_HZ MHZ(50) /* ARC EM Core IRQs */ -#define IRQ_TIMER0 16 -#define IRQ_TIMER1 17 - #if defined(CONFIG_BOARD_EM_STARTERKIT_R23) && defined(CONFIG_SOC_EMSK_EM7D) #define IRQ_SEC_TIMER0 20 #endif /* CONFIG_BOARD_EM_STARTERKIT_R23 && CONFIG_SOC_EMSK_EM7D */
diff --git a/soc/arc/snps_nsim/soc.h b/soc/arc/snps_nsim/soc.h index 7feee64..a9770ad 100644 --- a/soc/arc/snps_nsim/soc.h +++ b/soc/arc/snps_nsim/soc.h
@@ -17,9 +17,6 @@ #include <zephyr/sys/util.h> /* ARC EM Core IRQs */ -#define IRQ_TIMER0 16 -#define IRQ_TIMER1 17 - #define IRQ_SEC_TIMER0 20 #ifndef _ASMLANGUAGE
diff --git a/soc/arc/snps_qemu/soc.h b/soc/arc/snps_qemu/soc.h index 3b9e2d0..bfe306d 100644 --- a/soc/arc/snps_qemu/soc.h +++ b/soc/arc/snps_qemu/soc.h
@@ -14,8 +14,4 @@ #ifndef _SOC__H_ #define _SOC__H_ -/* ARC Core IRQs */ -#define IRQ_TIMER0 16 -#define IRQ_TIMER1 17 - #endif /* _SOC__H_ */
diff --git a/tests/kernel/context/src/main.c b/tests/kernel/context/src/main.c index b78de68..4b3c100 100644 --- a/tests/kernel/context/src/main.c +++ b/tests/kernel/context/src/main.c
@@ -27,7 +27,7 @@ #include <zephyr/irq_offload.h> #include <zephyr/sys_clock.h> -#if defined(CONFIG_SOC_POSIX) || defined(CONFIG_ARC) +#if defined(CONFIG_SOC_POSIX) /* TIMER_TICK_IRQ <soc.h> header for certain platforms */ #include <soc.h> #endif