commit 48ee3ee837aaf43d3f89158fab4bd4a9fdad583f
author Jun Li <jun.r.li@intel.com> Thu Mar 21 16:33:39 2019 -0700
committer Kumar Gala <kumar.gala@gmail.com> Tue Mar 26 07:51:20 2019 -0500
tree 4e68bab0bab44bc1971a048a663498327803dd75
parent 7da0053a0cbe323af6f7bf49e60b574691b458a9

board: nucleo_f429zi: fix wrong comment

the clock is 168MHz instead of 180MHz.

Signed-off-by: Jun Li <jun.r.li@intel.com>

boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig

diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig b/boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig
index 3bf37f5..dac4668 100644
--- a/boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig
+++ b/boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig
@@ -31,7 +31,7 @@
 # however, the board does not have an external oscillator, so just use
 # the 8MHz clock signal coming from integrated STLink
 CONFIG_CLOCK_STM32_HSE_BYPASS=y
-# produce 180MHz clock at PLL output
+# produce 168MHz clock at PLL output
 CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=336
 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2