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# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
# SPDX-License-Identifier: Apache-2.0
menu "RISCV Options"
depends on RISCV
config ARCH
string
default "riscv64" if 64BIT
default "riscv32"
config FLOAT_HARD
bool "Hard-float calling convention"
default y
depends on FPU
help
This option enables the hard-float calling convention.
config RISCV_GP
bool "RISC-V global pointer relative addressing"
default n
help
Use global pointer relative addressing for small globals declared
anywhere in the executable. It can benefit performance and reduce
the code size.
Note: To support this feature, RISC-V SoC needs to initialize
global pointer at program start or earlier than any instruction
using GP relative addressing.
menu "RISCV Processor Options"
config INCLUDE_RESET_VECTOR
bool "Include Reset vector"
help
Include the reset vector stub, which initializes the stack and
prepares for running C code.
config RISCV_SOC_CONTEXT_SAVE
bool "SOC-based context saving in IRQ handlers"
select RISCV_SOC_OFFSETS
help
Enable low-level SOC-specific context management, for SOCs
with extra state that must be saved when entering an
interrupt/exception, and restored on exit. If unsure, leave
this at the default value.
Enabling this option requires that the SoC provide a
soc_context.h header which defines the following macros:
- SOC_ESF_MEMBERS: structure component declarations to
allocate space for. The last such declaration should not
end in a semicolon, for portability. The generic RISC-V
architecture code will allocate space for these members in
a "struct soc_esf" type (typedefed to soc_esf_t), which will
be available if arch.h is included.
- SOC_ESF_INIT: structure contents initializer for struct soc_esf
state. The last initialized member should not end in a comma.
The generic architecture IRQ wrapper will also call
\_\_soc_save_context and \_\_soc_restore_context routines at
ISR entry and exit, respectively. These should typically
be implemented in assembly. If they were C functions, they
would have these signatures:
``void __soc_save_context(soc_esf_t *state);``
``void __soc_restore_context(soc_esf_t *state);``
The calls obey standard calling conventions; i.e., the state
pointer address is in a0, and ra contains the return address.
config RISCV_SOC_OFFSETS
bool "SOC-based offsets"
help
Enabling this option requires that the SoC provide a soc_offsets.h
header which defines the following macros:
- GEN_SOC_OFFSET_SYMS(): a macro which expands to
GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
to ensure offset macros for SOC_ESF_MEMBERS are defined
in offsets.h. The last one should not end in a semicolon.
See gen_offset.h for more details.
config RISCV_SOC_INTERRUPT_INIT
bool "SOC-based interrupt initialization"
help
Enable SOC-based interrupt initialization
(call soc_interrupt_init, within _IntLibInit when enabled)
config RISCV_SOC_MCAUSE_EXCEPTION_MASK
hex
default 0x7FFFFFFFFFFFFFFF if 64BIT
default 0x7FFFFFFF
help
Specify the bits to use for exception code in mcause register.
config RISCV_GENERIC_TOOLCHAIN
bool "Compile using generic riscv32 toolchain"
default y
help
Compile using generic riscv32 toolchain.
Allow SOCs that have custom extended riscv ISA to still
compile with generic riscv32 toolchain.
config RISCV_HAS_CPU_IDLE
bool "Does SOC has CPU IDLE instruction"
help
Does SOC has CPU IDLE instruction
config GEN_ISR_TABLES
default y
config GEN_IRQ_VECTOR_TABLE
default n
config NUM_IRQS
int
config RISCV_PMP
bool "RISC-V PMP Support"
select THREAD_STACK_INFO
select CPU_HAS_MPU
select ARCH_HAS_USERSPACE
select ARCH_HAS_STACK_PROTECTION
select MPU
select SRAM_REGION_PERMISSIONS
select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
select ARCH_MEM_DOMAIN_DATA if USERSPACE
select THREAD_LOCAL_STORAGE if USERSPACE
help
MCU implements Physical Memory Protection.
if RISCV_PMP
config PMP_SLOTS
int "Number of PMP slots"
default 8
help
This is the number of PMP entries implemented by the hardware.
Typical values are 8 or 16.
config PMP_POWER_OF_TWO_ALIGNMENT
bool "Enforce power-of-two alignment on PMP memory areas"
depends on USERSPACE
default y if TEST_USERSPACE
default y if (PMP_SLOTS = 8)
select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
select GEN_PRIV_STACKS
help
This option reduces the PMP slot usage but increases
memory consumption. Useful when enabling userspace mode with
many memory domains and/or few PMP slots available.
endif #RISCV_PMP
config PMP_STACK_GUARD
def_bool y
depends on HW_STACK_PROTECTION
config PMP_STACK_GUARD_MIN_SIZE
int "Stack Guard area size"
depends on PMP_STACK_GUARD
default 1024 if 64BIT
default 512
help
The Hardware Stack Protection implements a guard area at the bottom
of the stack using the PMP to catch stack overflows by marking that
guard area not accessible.
This is the size of the guard area. This should be large enough to
catch any sudden jump in stack pointer decrement, plus some
wiggle room to accommodate the eventual overflow exception
stack usage.
endmenu
config MAIN_STACK_SIZE
default 4096 if 64BIT
default 2048 if PMP_STACK_GUARD
config TEST_EXTRA_STACK_SIZE
default 1024
config CMSIS_THREAD_MAX_STACK_SIZE
default 1024 if 64BIT
config CMSIS_V2_THREAD_MAX_STACK_SIZE
default 1024 if 64BIT
rsource "Kconfig.isa"
rsource "Kconfig.core"
endmenu