dts/riscv/openhwgroup/cva6.dtsi

/*
 * SPDX-License-Identifier: Apache-2.0
 * Copyright 2024 CISPA Helmholtz Center for Information Security
 */

#include <freq.h>

/*
 * CVA6 SoC without CPU, which comes in 32 and 64 bit variants
 */
/ {
	#address-cells = <0x01>;
	#size-cells = <0x01>;

	clocks {
		clk_cpu {
			#clock-cells = <0x00>;
			clock-frequency = <DT_FREQ_M(50)>;
			compatible = "fixed-clock";
		};

		clk_bus: clk_bus_0 {
			#clock-cells = <0x00>;
			clock-frequency = <DT_FREQ_M(50)>;
			compatible = "fixed-clock";
		};
	};

	soc {
		#address-cells = <0x01>;
		#size-cells = <0x01>;
		ranges;

		/* Xilinx MIG memory controller */
		memory0: memory@80000000 {
			device_type = "memory";
			reg = <0x80000000 0x40000000>;
			status = "okay";
		};

		/* RISC-V Platform-level interrupt controller */
		plic: interrupt-controller@c000000 {
			compatible = "sifive,plic-1.0.0";
			#address-cells = <0>;
			#interrupt-cells = <2>;
			interrupt-controller;
			interrupts-extended = <&hlic 11 &hlic 9>;
			reg = <0x0c000000 0x4000000>;
			riscv,max-priority = <7>;
			riscv,ndev = <30>;
			status = "okay";
		};

		/* USB UART */
		uart0: serial@10000000 {
			clock-frequency = <50000000>;
			clocks = <&clk_bus>;
			compatible = "ns16550";
			current-speed = <115200>;
			device_type = "serial";
			reg = <0x10000000 0x10000>;
			reg-shift = <0x02>;
			parity = "none";
			stop-bits = "1";
			data-bits = <8>;
			interrupt-parent = <&plic>;
			interrupts = <1 0x04>;
			status = "disabled";
		};

		/* SPI controller, connected to SD card */
		spi0: axi_quad_spi@20000000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "xlnx,xps-spi-2.00.a";
			reg = <0x20000000 0x10000>;
			xlnx,num-ss-bits = <0x01>;
			xlnx,num-transfer-bits = <0x8>;
			interrupts = <2 0x2>;
			interrupt-parent = <&plic>;
			clocks = <&clk_bus>;
			status = "disabled";
		};

		/*
		 * Core-local interrupt controller according to RISC-V spec
		 */
		clint: clint@2000000 {
			compatible = "sifive,clint0";
			reg = <0x2000000 0x40000>;
			interrupts-extended = <&hlic 3 &hlic 7>;
			status = "disabled";
		};

		mtimer: timer@200bff8 {
			compatible = "riscv,machine-timer";
			interrupts-extended = <&hlic 7>;
			reg = <0x200bff8 0x8 0x2004000 0x8>;
			reg-names = "mtime", "mtimecmp";
			status = "disabled";
		};

		/*
		 * Xilinx AXI DMA.
		 * Part of the Xilinx AXI Ethernet Subsystem.
		 * Only on CISPA board.
		 */
		dma0: dma@41e00000 {
			#dma-cells = <0x01>;
			clock-frequency = <DT_FREQ_M(50)>;
			clock-names = "s_axi_lite_aclk";
			clocks = <&clk_bus>;
			compatible = "xlnx,eth-dma";
			reg = <0x41e00000 0x10000>;
			xlnx,addrwidth = <0x40>;
			xlnx,include-dre;
			xlnx,num-queues = <0x1>;
			interrupt-parent = <&plic>;
			// TX - RX
			// active-high level-triggered
			interrupts = <8 4>, <9 4>;
			// TX and RX
			dma-channels = <2>;
			status = "disabled";
		};

		/*
		 * LowRISC ethernet subsystem.
		 * Only on OpenHW Group board.
		 */
		eth: lowrisc-eth@30000000 {
			compatible = "lowrisc-eth";
			device_type = "network";
			interrupt-parent = <&plic>;
			interrupts = <3 0>;
			reg = <0x0 0x30000000 0x0 0x8000>;
			status = "disabled";
		};

		/* Xilinx GPIO, connected to LEDs */
		xlnx_gpio: gpio@40000000 {
			#gpio-cells = <2>;
			compatible = "xlnx,xps-gpio-1.00.a";
			gpio-controller;
			reg = <0x0 0x40000000 0x0 0x10000>;
			xlnx,all-inputs = <0x0>;
			xlnx,all-inputs-2 = <0x0>;
			xlnx,dout-default = <0x0>;
			xlnx,dout-default-2 = <0x0>;
			xlnx,gpio-width = <0x8>;
			xlnx,gpio2-width = <0x8>;
			xlnx,is-dual = <0x1>;
			xlnx,tri-default = <0xffffffff>;
			xlnx,tri-default-2 = <0xffffffff>;
			status = "disabled";
		};
	};
};