| # Copyright 2022-2024 NXP |
| # SPDX-License-Identifier: Apache-2.0 |
| |
| config SOC_SERIES_RW6XX |
| select ARM |
| select CPU_CORTEX_M33 |
| select CPU_CORTEX_M_HAS_DWT |
| select CLOCK_CONTROL |
| select PLATFORM_SPECIFIC_INIT |
| select CPU_HAS_ARM_SAU |
| select CPU_HAS_ARM_MPU |
| select CPU_HAS_FPU |
| select HAS_MCUX_OS_TIMER |
| select ARM_TRUSTZONE_M |
| select CPU_CORTEX_M_HAS_SYSTICK |
| select HAS_MCUX |
| select HAS_MCUX_FLEXCOMM |
| select INIT_SYS_PLL |
| select HAS_MCUX_CACHE |
| |
| if SOC_SERIES_RW6XX |
| |
| config INIT_SYS_PLL |
| bool "Initialize SYS PLL" |
| |
| menuconfig NXP_RW6XX_BOOT_HEADER |
| bool "Create boot header" |
| default y if !BOOTLOADER_MCUBOOT |
| help |
| Create data structures required by the boot ROM to boot the |
| application from an external flash device. |
| |
| if NXP_RW6XX_BOOT_HEADER |
| |
| choice BOOT_DEVICE |
| prompt "Boot device selection" |
| default BOOT_FLEXSPI_NOR |
| |
| config BOOT_FLEXSPI_NOR |
| bool "FlexSPI serial NOR" |
| |
| endchoice |
| |
| config FLASH_CONFIG_OFFSET |
| hex "Flash config data offset" |
| default 0x400 |
| help |
| The flash config offset provides the boot ROM with the on-board |
| flash type and parameters. The boot ROM requires a fixed flash conifg |
| offset for FlexSPI device. |
| |
| config IMAGE_VECTOR_TABLE_OFFSET |
| hex "Image vector table offset" |
| default 0x1000 |
| help |
| The Image Vector Table (IVT) provides the boot ROM with pointers to |
| the application entry point and device configuration data. The boot |
| ROM requires a fixed IVT offset for each type of boot device. |
| |
| endif # NXP_RW6XX_BOOT_HEADER |
| |
| # Used for default value in FLASH_MCUX_FLEXSPI_XIP |
| DT_CHOSEN_Z_FLASH := zephyr,flash |
| DT_COMPAT_FLEXSPI := nxp,imx-flexspi |
| # Macros to shorten Kconfig definitions |
| DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) |
| DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) |
| |
| config FLASH_MCUX_FLEXSPI_XIP |
| bool "MCUX FlexSPI flash access with xip" |
| default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) |
| select XIP |
| help |
| Allows for the soc to safely initialize the clocks for the |
| FlexSpi when planning to execute code in FlexSpi Memory. |
| |
| config NXP_RW_ROM_RAMLOADER |
| depends on !FLASH_MCUX_FLEXSPI_XIP |
| # Required so that debugger will load image to correct offset |
| select BUILD_OUTPUT_HEX |
| bool "Create output image that RW ROM can load from FlexSPI to ram" |
| help |
| Builds an output image that the RW BootROM can load from the |
| FlexSPI boot device into RAM region. The image will be loaded |
| from FLEXSPI into the region specified by `zephyr,flash` node. |
| |
| config FLASH_MCUX_FLEXSPI_XIP_MEM |
| string |
| default "RAM" |
| depends on MEMC_MCUX_FLEXSPI |
| |
| endif # SOC_SERIES_RW6XX |