| /* |
| * Copyright (c) 2020 Linaro Limited |
| * |
| * SPDX-License-Identifier: Apache-2.0 |
| */ |
| |
| /** |
| * @file |
| * @brief System/hardware module for STM32L5 processor |
| */ |
| |
| #include <device.h> |
| #include <init.h> |
| #include <stm32_ll_bus.h> |
| #include <stm32_ll_pwr.h> |
| #include <arch/cpu.h> |
| #include <arch/arm/aarch32/cortex_m/cmsis.h> |
| |
| /** |
| * @brief Perform basic hardware initialization at boot. |
| * |
| * This needs to be run from the very beginning. |
| * So the init priority has to be 0 (zero). |
| * |
| * @return 0 |
| */ |
| static int stm32l5_init(const struct device *arg) |
| { |
| uint32_t key; |
| |
| ARG_UNUSED(arg); |
| |
| key = irq_lock(); |
| |
| /* Install default handler that simply resets the CPU |
| * if configured in the kernel, NOP otherwise |
| */ |
| NMI_INIT(); |
| |
| irq_unlock(key); |
| |
| /* Update CMSIS SystemCoreClock variable (HCLK) */ |
| /* At reset, system core clock is set to 4 MHz from MSI */ |
| SystemCoreClock = 4000000; |
| |
| /* Enable Scale 0 to achieve 110MHz */ |
| LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); |
| LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0); |
| LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_PWR); |
| |
| return 0; |
| } |
| |
| SYS_INIT(stm32l5_init, PRE_KERNEL_1, 0); |