| # Kconfig - GPIO configuration options |
| |
| # |
| # Copyright (c) 2015 Intel Corporation |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are met: |
| # |
| # 1) Redistributions of source code must retain the above copyright notice, |
| # this list of conditions and the following disclaimer. |
| # |
| # 2) Redistributions in binary form must reproduce the above copyright notice, |
| # this list of conditions and the following disclaimer in the documentation |
| # and/or other materials provided with the distribution. |
| # |
| # 3) Neither the name of Intel Corporation nor the names of its contributors |
| # may be used to endorse or promote products derived from this software without |
| # specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| # POSSIBILITY OF SUCH DAMAGE. |
| # |
| |
| menuconfig GPIO |
| bool |
| prompt "GPIO Drivers" |
| default n |
| help |
| Include GPIO drivers in system config |
| |
| if GPIO |
| config GPIO_DW |
| prompt "Designware GPIO" |
| default n |
| depends on GPIO |
| bool |
| help |
| Enable driver for Designware GPIO |
| |
| config GPIO_DW_SHARED_IRQ |
| bool |
| default n |
| depends on GPIO_DW |
| |
| config GPIO_DW_VENDOR_ID |
| hex "PCI Vendor ID" |
| depends on GPIO_DW && PCI |
| default 0x8086 |
| |
| config GPIO_DW_DEVICE_ID |
| hex "PCI Device ID" |
| depends on GPIO_DW && PCI |
| default 0x934 |
| |
| config GPIO_DW_CLASS |
| hex "PCI class" |
| depends on GPIO_DW && PCI |
| default 0x0C |
| |
| config GPIO_DW_0 |
| bool "Designware GPIO block 0" |
| depends on GPIO_DW |
| default n |
| help |
| Include Designware GPIO driver |
| |
| config GPIO_DW_0_NAME |
| string "Driver name" |
| depends on GPIO_DW_0 |
| default "GPIO_0" |
| |
| config GPIO_DW_0_BASE_ADDR |
| hex "Controller base address" |
| depends on GPIO_DW_0 |
| default 0x00000000 |
| |
| config GPIO_DW_0_BUS |
| int "Port 0 PCI Bus" |
| depends on GPIO_DW_0 && PCI |
| default 0 |
| |
| config GPIO_DW_0_DEV |
| int "Port 0 PCI Dev" |
| depends on GPIO_DW_0 && PCI |
| default 0 |
| |
| config GPIO_DW_0_FUNCTION |
| int "PCI function number" |
| depends on GPIO_DW_0 && PCI |
| default 0 |
| |
| config GPIO_DW_0_BAR |
| int "PCI BAR slot" |
| depends on GPIO_DW_0 && PCI |
| default 0 |
| |
| config GPIO_DW_0_BITS |
| int "number of pins controlled" |
| depends on GPIO_DW_0 |
| default 32 |
| help |
| Number of pins controlled by controller |
| |
| choice |
| prompt "Port 0 Interrupts via" |
| default GPIO_DW_0_IRQ_DIRECT |
| depends on GPIO_DW_0 |
| |
| config GPIO_DW_0_IRQ_DIRECT |
| bool "Direct Hardware Interrupt" |
| help |
| When interrupts fire, the driver's ISR function is being called directly. |
| |
| config GPIO_DW_0_IRQ_SHARED |
| bool "Shared IRQ" |
| depends on SHARED_IRQ |
| select GPIO_DW_SHARED_IRQ |
| help |
| When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ |
| driver dispatches the interrupt to other drivers. |
| |
| endchoice |
| |
| config GPIO_DW_0_IRQ_SHARED_NAME |
| string "Device name for Shared IRQ" |
| depends on GPIO_DW_0 && GPIO_DW_0_IRQ_SHARED |
| help |
| Specify the device name for the shared IRQ driver. It is used to register |
| this driver with the shared IRQ driver, so interrupts can be dispatched |
| correctly. |
| |
| config GPIO_DW_0_IRQ |
| int "Controller interrupt number" |
| depends on GPIO_DW_0 && GPIO_DW_0_IRQ_DIRECT |
| default 0 |
| help |
| IRQ number for the controller |
| |
| config GPIO_DW_0_PRI |
| int "Controller interrupt priority" |
| depends on GPIO_DW_0 && GPIO_DW_0_IRQ_DIRECT |
| default 0 |
| help |
| IRQ priority |
| |
| config GPIO_DW_1 |
| bool "Designware GPIO block 1" |
| depends on GPIO_DW |
| default n |
| help |
| Include Designware GPIO driver |
| |
| config GPIO_DW_1_NAME |
| string "Driver name" |
| depends on GPIO_DW_1 |
| default "GPIO_1" |
| |
| config GPIO_DW_1_BASE_ADDR |
| hex "Controller base address" |
| depends on GPIO_DW_1 |
| default 0x00000000 |
| |
| config GPIO_DW_1_BITS |
| int "number of pins controlled" |
| depends on GPIO_DW_1 |
| default 32 |
| help |
| Number of pins controlled by controller |
| |
| choice |
| prompt "Port 1 Interrupts via" |
| default GPIO_DW_1_IRQ_DIRECT |
| depends on GPIO_DW_1 |
| |
| config GPIO_DW_1_IRQ_DIRECT |
| bool "Direct Hardware Interrupt" |
| help |
| When interrupts fire, the driver's ISR function is being called directly. |
| |
| config GPIO_DW_1_IRQ_SHARED |
| bool "Shared IRQ" |
| depends on SHARED_IRQ |
| select GPIO_DW_SHARED_IRQ |
| help |
| When interrupts fire, the shared IRQ driver is notified. Then the shared IRQ |
| driver dispatches the interrupt to other drivers. |
| |
| endchoice |
| |
| config GPIO_DW_1_IRQ_SHARED_NAME |
| string "Device name for Shared IRQ" |
| depends on GPIO_DW_1_IRQ_SHARED |
| help |
| Specify the device name for the shared IRQ driver. It is used to register |
| this driver with the shared IRQ driver, so interrupts can be dispatched |
| correctly. |
| |
| config GPIO_DW_1_IRQ |
| int "Controller interrupt number" |
| depends on GPIO_DW_1 && GPIO_DW_1_IRQ_DIRECT |
| default 0 |
| help |
| IRQ number for the controller |
| |
| config GPIO_DW_1_PRI |
| int "Controller interrupt priority" |
| depends on GPIO_DW_1 && GPIO_DW_1_IRQ_DIRECT |
| default 0 |
| help |
| IRQ priority |
| |
| choice |
| prompt "DW GPIO port 0 trigger condition" |
| default GPIO_DW_0_RISING_EDGE |
| depends on GPIO_DW_0 && GPIO_DW_0_IRQ_DIRECT |
| |
| config GPIO_DW_0_FALLING_EDGE |
| bool "Falling edge" |
| help |
| DW GPIO port 0 uses falling edge interrupt |
| |
| config GPIO_DW_0_RISING_EDGE |
| bool "Rising edge" |
| help |
| DW GPIO port 0 uses rising edge interrupt |
| |
| config GPIO_DW_0_LEVEL_HIGH |
| bool "Level high" |
| help |
| DW GPIO port 0 uses level high interrupt |
| |
| config GPIO_DW_0_LEVEL_LOW |
| bool "Level low" |
| help |
| DW GPIO port 0 uses level low interrupt |
| |
| endchoice |
| |
| config GPIO_PCAL9535A |
| bool "PCAL9535A I2C-based GPIO chip" |
| depends on GPIO && I2C |
| default n |
| select NANO_TIMERS |
| help |
| Enable driver for PCAL9535A I2C-based GPIO chip. |
| |
| if GPIO_PCAL9535A |
| config GPIO_PCAL9535A_DEBUG |
| bool "Enable PCAL9535A Debugging" |
| depends on GPIO_PCAL9535A |
| default n |
| help |
| Enable debugging for PCAL9535A driver. |
| |
| config GPIO_PCAL9535A_0 |
| bool "PCAL9535A GPIO chip #0" |
| depends on GPIO_PCAL9535A |
| default n |
| help |
| Enable config options for the PCAL9535A I2C-based GPIO chip #0. |
| |
| config GPIO_PCAL9535A_0_DEV_NAME |
| string "PCAL9535A GPIO chip #0 Device Name" |
| depends on GPIO_PCAL9535A_0 |
| default "GPIO_P0" |
| help |
| Specify the device name for the PCAL9535A I2C-based GPIO chip #0. |
| |
| config GPIO_PCAL9535A_0_I2C_ADDR |
| hex "PCAL9535A GPIO chip #0 I2C slave address" |
| depends on GPIO_PCAL9535A_0 |
| default 0x0 |
| help |
| Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #0. |
| |
| config GPIO_PCAL9535A_0_I2C_MASTER_DEV_NAME |
| string "I2C Master where PCAL9535A GPIO chip #0 is connected" |
| depends on GPIO_PCAL9535A_0 |
| default "" |
| help |
| Specify the device name of the I2C master device to which this |
| PCAL9535A chip #0 is binded. |
| |
| config GPIO_PCAL9535A_1 |
| bool "PCAL9535A GPIO chip #1" |
| depends on GPIO_PCAL9535A |
| default n |
| help |
| Enable config options for the PCAL9535A I2C-based GPIO chip #1. |
| |
| config GPIO_PCAL9535A_1_DEV_NAME |
| string "PCAL9535A GPIO chip #1 Device Name" |
| depends on GPIO_PCAL9535A_1 |
| default "GPIO_P1" |
| help |
| Specify the device name for the PCAL9535A I2C-based GPIO chip #1. |
| |
| config GPIO_PCAL9535A_1_I2C_ADDR |
| hex "PCAL9535A GPIO chip #1 I2C slave address" |
| depends on GPIO_PCAL9535A_1 |
| default 0x0 |
| help |
| Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #1. |
| |
| config GPIO_PCAL9535A_1_I2C_MASTER_DEV_NAME |
| string "I2C Master where PCAL9535A GPIO chip #1 is connected" |
| depends on GPIO_PCAL9535A_1 |
| default "" |
| help |
| Specify the device name of the I2C master device to which this |
| PCAL9535A chip #1 is binded. |
| |
| config GPIO_PCAL9535A_2 |
| bool "PCAL9535A GPIO chip #2" |
| depends on GPIO_PCAL9535A |
| default n |
| help |
| Enable config options for the PCAL9535A I2C-based GPIO chip #2. |
| |
| config GPIO_PCAL9535A_2_DEV_NAME |
| string "PCAL9535A GPIO chip #2 Device Name" |
| depends on GPIO_PCAL9535A_2 |
| default "GPIO_P2" |
| help |
| Specify the device name for the PCAL9535A I2C-based GPIO chip #2. |
| |
| config GPIO_PCAL9535A_2_I2C_ADDR |
| hex "PCAL9535A GPIO chip #2 I2C slave address" |
| depends on GPIO_PCAL9535A_2 |
| default 0x0 |
| help |
| Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #2. |
| |
| config GPIO_PCAL9535A_2_I2C_MASTER_DEV_NAME |
| string "I2C Master where PCAL9535A GPIO chip #2 is connected" |
| depends on GPIO_PCAL9535A_2 |
| default "" |
| help |
| Specify the device name of the I2C master device to which this |
| PCAL9535A chip #2 is binded. |
| |
| config GPIO_PCAL9535A_3 |
| bool "PCAL9535A GPIO chip #3" |
| depends on GPIO_PCAL9535A |
| default n |
| help |
| Enable config options for the PCAL9535A I2C-based GPIO chip #3. |
| |
| config GPIO_PCAL9535A_3_DEV_NAME |
| string "PCAL9535A GPIO chip #3 Device Name" |
| depends on GPIO_PCAL9535A_3 |
| default "GPIO_P3" |
| help |
| Specify the device name for the PCAL9535A I2C-based GPIO chip #3. |
| |
| config GPIO_PCAL9535A_3_I2C_ADDR |
| hex "PCAL9535A GPIO chip #3 I2C slave address" |
| depends on GPIO_PCAL9535A_3 |
| default 0x0 |
| help |
| Specify the I2C slave address for the PCAL9535A I2C-based GPIO chip #3. |
| |
| config GPIO_PCAL9535A_3_I2C_MASTER_DEV_NAME |
| string "I2C Master where PCAL9535A GPIO chip #3 is connected" |
| depends on GPIO_PCAL9535A_3 |
| default "" |
| help |
| Specify the device name of the I2C master device to which this |
| PCAL9535A chip #3 is binded. |
| endif #GPIO_PCAL9535A |
| |
| config GPIO_MMIO |
| bool "MMIO-based GPIO driver" |
| depends on GPIO |
| default n |
| help |
| Enable driver for MMIO-based GPIOs. |
| |
| config GPIO_MMIO_0 |
| bool "MMIO-based GPIO Port #0" |
| depends on GPIO_MMIO |
| default n |
| help |
| Enable config options for MMIO-based GPIO port #0. |
| |
| config GPIO_MMIO_0_DEV_NAME |
| string "MMIO-based GPIO Port #0 Device Name" |
| depends on GPIO_MMIO_0 |
| default "GPIO_M0" |
| help |
| Specify the device name. |
| |
| choice |
| prompt "MMIO-based GPIO Port #0 Access Method" |
| default GPIO_MMIO_0_ACCESS_MM |
| depends on GPIO_MMIO_0 |
| |
| config GPIO_MMIO_0_ACCESS_MM |
| bool "Direct Memory Access" |
| |
| config GPIO_MMIO_0_ACCESS_IO |
| bool "I/O Port" |
| |
| endchoice |
| |
| config GPIO_MMIO_0_CFG |
| hex "MMIO-based GPIO Port #0 Configuration" |
| depends on GPIO_MMIO_0 |
| default 0x0 |
| help |
| Configuration for this GPIO port. |
| |
| Refer to <drivers/gpio/gpio-mmio.h> for more information. |
| |
| config GPIO_MMIO_0_EN |
| hex "MMIO-based GPIO Port #0 Enable Register Address" |
| depends on GPIO_MMIO_0 |
| default 0x0 |
| help |
| The memory address for enable register. |
| |
| config GPIO_MMIO_0_DIR |
| hex "MMIO-based GPIO Port #0 Direction Register Address" |
| depends on GPIO_MMIO_0 |
| default 0x0 |
| help |
| The memory address for direction register. |
| |
| config GPIO_MMIO_0_INPUT |
| hex "MMIO-based GPIO Port #0 Input Pin Level Register Address" |
| depends on GPIO_MMIO_0 |
| default 0x0 |
| help |
| The memory address for input pin level register. |
| |
| config GPIO_MMIO_0_OUTPUT |
| hex "MMIO-based GPIO Port #0 Output Pin Level Register Address" |
| depends on GPIO_MMIO_0 |
| default 0x0 |
| help |
| The memory address for output pin level register. |
| |
| config GPIO_MMIO_1 |
| bool "MMIO-based GPIO Port #1" |
| depends on GPIO_MMIO |
| default n |
| help |
| Enable config options for MMIO-based GPIO port #1. |
| |
| config GPIO_MMIO_1_DEV_NAME |
| string "MMIO-based GPIO Port #1 Device Name" |
| depends on GPIO_MMIO_1 |
| default "GPIO_M1" |
| help |
| Specify the device name. |
| |
| choice |
| prompt "MMIO-based GPIO Port #1 Access Method" |
| default GPIO_MMIO_1_ACCESS_MM |
| depends on GPIO_MMIO_1 |
| |
| config GPIO_MMIO_1_ACCESS_MM |
| bool "Direct Memory Access" |
| |
| config GPIO_MMIO_1_ACCESS_IO |
| bool "I/O Port" |
| |
| endchoice |
| |
| config GPIO_MMIO_1_CFG |
| hex "MMIO-based GPIO Port #1 Configuration" |
| depends on GPIO_MMIO_1 |
| default 0x0 |
| help |
| Configuration for this GPIO port. |
| |
| Refer to <drivers/gpio/gpio-mmio.h> for more information. |
| |
| config GPIO_MMIO_1_EN |
| hex "MMIO-based GPIO Port #1 Enable Register Address" |
| depends on GPIO_MMIO_1 |
| default 0x0 |
| help |
| The memory address for enable register. |
| |
| config GPIO_MMIO_1_DIR |
| hex "MMIO-based GPIO Port #1 Direction Register Address" |
| depends on GPIO_MMIO_1 |
| default 0x0 |
| help |
| The memory address for direction register. |
| |
| config GPIO_MMIO_1_INPUT |
| hex "MMIO-based GPIO Port #1 Input Pin Level Register Address" |
| depends on GPIO_MMIO_1 |
| default 0x0 |
| help |
| The memory address for input pin level register. |
| |
| config GPIO_MMIO_1_OUTPUT |
| hex "MMIO-based GPIO Port #1 Output Pin Level Register Address" |
| depends on GPIO_MMIO_1 |
| default 0x0 |
| help |
| The memory address for output pin level register. |
| |
| endif # GPIO |
