| # Kconfig - interrupt controller configuration options |
| |
| # |
| # Copyright (c) 2015 Intel Corporation |
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| |
| |
| menu "Interrupt Controllers" |
| |
| config LOAPIC |
| bool "LOAPIC" |
| default n |
| select IOAPIC |
| depends on X86_32 |
| help |
| This option selects local APIC as the interrupt controller. |
| |
| config LOAPIC_DEBUG |
| bool "LOAPIC Debug" |
| default n |
| depends on LOAPIC |
| help |
| This option enable debugging for the LOAPIC driver. |
| |
| config LOAPIC_BASE_ADDRESS |
| hex "Local APIC Base Address" |
| default 0xFEE00000 |
| depends on LOAPIC |
| help |
| This option specifies the base address of the Local APIC device. |
| |
| config IOAPIC |
| bool "IO-APIC" |
| default y |
| depends on LOAPIC |
| help |
| This option signifies that the target has an IO-APIC device. This |
| capability allows IO-APIC-dependent code to be included. |
| |
| config IOAPIC_DEBUG |
| bool "IO-APIC Debugging" |
| default n |
| depends on IOAPIC |
| help |
| Enable debugging for IO-APIC driver. |
| |
| config IOAPIC_BASE_ADDRESS |
| hex "IO-APIC Base Address" |
| default 0xFEC00000 |
| depends on IOAPIC |
| help |
| This option specifies the base address of the IO-APIC device. |
| |
| config IOAPIC_NUM_RTES |
| int "Number of Redirection Table Entries available" |
| default 24 |
| depends on IOAPIC |
| help |
| This option indicates the maximum number of Redirection Table Entries |
| (RTEs) (one per IRQ available to the IO-APIC) made available to the |
| kernel, regardless of the number provided by the hardware itself. For |
| most efficient usage of memory, it should match the number of IRQ lines |
| needed by devices connected to the IO-APIC. |
| |
| config ARCV2_INTERRUPT_UNIT |
| bool "ARCv2 Interrupt Unit" |
| default y |
| depends on ARC |
| help |
| The ARCv2 interrupt unit has 16 allocated exceptions associated with |
| vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255. |
| The interrupt unit is optional in the ARCv2-based processors. When |
| building a processor, you can configure the processor to include an |
| interrupt unit. The ARCv2 interrupt unit is highly programmable. |
| endmenu |
